Low-Power, Low-Glitch, Octal 12-Bit Voltage- Output DACs with Serial Interface

Transcription

1 9-232; Rev 0; 8/0 Low-Power, Low-Glitch, Octal 2-Bit Voltage- Output s with Serial Interface General Description The are 2-bit, eight channel, lowpower, voltage-output, digital-to-analog converters (s) in a space-saving 6-pin TSSOP package. The wide +2.7V to +5.5V supply voltage range and less than 25µA (max) supply current per are excellent for low-power and low-voltage applications. The low 2nV/s glitch energy of the makes them ideal for digital control of fast-response, closedloop systems. The has a digital output (DOUT) that can be used for daisy-chaining multiple devices. The MAX5307 has a hardware reset input (CLR) which clears all registers and s to zero. The have a software shutdown feature that reduces the supply current to µa. The feature a load (L) function that updates the output of all eight s simultaneously. The 3-wire SPI, QSPI, MICROWIRE and DSPcompatible serial interface allows the input and registers to be updated independently or simultaneously with a single software command. These devices use a double-buffered design to minimize the digital-noise feedthrough from the digital inputs to the outputs. The operating temperature range is from -40 C to +85 C. Features Eight Highly Integrated 2-Bit s in 6-Pin TSSOP (6.4mm x 5mm) Package Ultra-Low Glitch Energy < 2nV/s Low Total Supply Current:.7mA (max) with V REF = V DD = +5.5V +2.7V to +5.5V Wide Single-Supply Range Fast 5µs Settling Time Software-Selectable Shutdown Mode < µa 5MHz 3-Wire SPI, QSPI, and MICROWIRE- Compatible Serial Interface Power-Up Reset to Zero Scale Ordering Information PART TEMP. RANGE PIN-PACKAGE EUE -40 C to +85 C 6 TSSOP MAX5307EUE -40 C to +85 C 6 TSSOP Gain and Offset Adjustment Applications Pin Configuration Power Amplifier Control Process Control I/O Boards Portable Instrumentation Equipment Control of Optical Components TOP VIEW L DOUT (CLR) V DD REF OUT 4 5 MAX GND OUT8 OUT2 6 OUT7 OUT3 7 0 OUT6 OUT4 8 9 OUT5 () FOR MAX5307 ONLY 6-TSSOP SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 Output s with Serial Interface ABSOLUTE MAXIMUM RATINGS V DD to GND V to +6V All Other Pins to GND V to (V DD + 0.3V) Continuous Power Dissipation (T A = +70 C) 6-Pin TSSOP (derate 9.4mW/ C above +70 C)...775mW Maximum Current Into Any Pin...±50mA Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +50 C Lead Temperature (soldering, 0s) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI (V DD = +2.7V to +5.5V, GND = 0, V REF = V DD, C L = 200pF, R L = 2kΩ, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V DD = +5V, T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Notes, 2) Resolution N 2 Bits Integral Nonlinearity INL ± ±4 LSB Differential Nonlinearity DNL Guaranteed monotonic ±.0 LSB Offset Error (Note 3) V OE ±0 ±60 mv Offset Error Temperature Coefficient ±0 µv/ C Gain Error (Note 3) V GE ±0. ± % of FS Gain Error Temperature Coefficient ±5 ppm/ C REFERENCE Reference Input Voltage Range (Note 4) V REF 0.8 V DD V Reference Input Impedance R REFIN kω Reference Current I REFPD In power-down mode 0 µa OUTPUTS Output Voltage Range With no load V DD DC Output Impedance 0.5 Ω Capacitive Load C L 500 pf Resistive Load R L 2 kω Short-Circuit Current V DD = +5V 33 V DD = +2.7V 20 Wake-Up Time From shutdown mode 24 µs V ma 2

3 Output s with Serial Interface ELECTRICAL CHARACTERISTI (continued) (V DD = +2.7V to +5.5V, GND = 0, V REF = V DD, C L = 200pF, R L = 2kΩ, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V DD = +5V, T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL S (,,, L, CLR-MAX5307) V DD = +5V ±0% 2.4 Input High Voltage V IH V DD = +3V ±0% 2. V DD = +5V ±0% 0.8 Input Low Voltage V IL V DD = +3V ±0% 0.6 Input Leakage Current I IN All digital inputs 0 or V DD ±0. ±0 µa Input Capacitance C IN 0 pf DIGITAL OUTPUT () Output Low Voltage V OL I SINK = ma 0.5 V Output High Voltage V OH I SOURCE = ma DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Positive and negative V/µs Voltage-Output Settling Time t S 400hex to C00hex 5 µs Digital Feedthrough V DD Code 0, all digital inputs from 0V to V DD 0.5 nv/s Glitch Impulse Major carry transition 2 nv/s V V V Output Noise 600 µvp-p to Crosstalk 0.5 nv/s POWER REQUIREMENTS Supply Voltage Range V DD V Supply Current with No Load (Note 5) I DD All digital inputs at 0 or V DD, V DD = V REF = +5.5V All digital inputs at 0 or V DD, V DD = +5.5V, V REF = +.2V All digital inputs at 0 or V DD, V DD = V REF = +3V Shutdown mode 0 µa.3 ma 3

4 Output s with Serial Interface ELECTRICAL CHARACTERISTI (continued) (V DD = +2.7V to +5.5V, GND = 0, V REF = V DD, C L = 200pF, R L = 2kΩ, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V DD = +5V, T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTI Serial Clock Frequency f 0 5 MHz Pulse Width High t CH 33 ns Pulse Width Low t CL 33 ns Fall to Fall Setup Time t S 6 ns Fall to Rise Setup Time t H 20 ns L Pulse Width Low t LPWL 20 ns CLR Pulse Width Low t CLRPWL MAX5307 only 20 ns to Fall Setup Time t DS 6 ns to Fall Hold Time t DH 0 ns Pulse Width High t PWH 20 ns Rise to DOUT Fall t SDL Load capacitance = 20pF 50 ns Rise to DOUT Rise t SDH Load capacitance = 20pF 50 ns Note : Static accuracy tested without load. Note 2: Linearity is tested within codes 73hex to F8Dhex. Note 3: Gain and offset tested within codes 73hex to F8Dhex. Note 4: Static accuracy specifications valid for V REF =.2V to V DD. Note 5: Current scales linearly between these two extremes of V REF. 4

5 Output s with Serial Interface (V DD = +5V, T A = +25 C, unless otherwise noted.) INL (LSB) INTEGRAL NONLINEARITY vs. DIGITAL CODE DIGITAL CODE toc0 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE DIGITAL CODE Typical Operating Characteristics toc02 RELATIVE OUTPUT (db) REFERENCE VOLTAGE FREQUENCY RESPONSE V REF SWEPT Vp-p R L = 2kΩ, C L = 200pF FREQUENCY (khz) toc03 SUPPLY CURRENT (ma) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) V REF = +2.5V CODE = 000 SUPPLY CURRENT VS. SUPPLY VOLTAGE (CODE = FFFHEX) T A = -40 C T A = +25 C T A = +85 C VREF =.2V CODE = FFFHEX SUPPLY VOLTAGE (V) toc04 toc07 SUPPLY CURRENT (ma) VOUT (V) SUPPLY CURRENT vs. REFERENCE VOLTAGE V DD = +5V V DD = +3V REFERENCE VOLTAGE (V) SOURCE-AND-SINK CURRENT CAPABILITY V DD = V REF = +5V CODE = FFFHEX, SOURCING 5.0 CURRENT FROM OUT_ CODE = C00HEX, 3.0 SOURCING CURRENT 2.5 FROM OUT_ 2.0 CODE = 400HEX,.5 SINKING CURRENT.0 INTO OUT_ 0.5 CODE = 000HEX, SINKING CURRENT INTO OUT_ I SOURCE/SINK (ma) toc05 toc08 SUPPLY CURRENT (ma) FULL-SCALE ERROR (LSB) SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = -40 C T A = +25 C T A = +85 C V REF = +.2V CODE = SUPPLY VOLTAGE (V) FULL-SCALE ERROR vs. REFERENCE VOLTAGE V DD = +5V, CODE = FFFHEX NORMALIZED TO V REF = +5V REFERENCE VOLTAGE (V) toc06 toc09 5

6 Output s with Serial Interface Typical Operating Characteristics (continued) (V DD = +5V, T A = +25 C, unless otherwise noted.) FULL-SCALE ERROR (LSB) FULL-SCALE ERROR vs. LOAD CURRENT -6 V REF = V NORMALIZED TO 0.mA LOAD CURRENT (ma) toc0 REFERENCE FEEDTHROUGH AT khz, R L = 2kΩ, C L = 200pF CODE = μs toc REF, 2V/div O OUT_ mvp-p -TO- CROSSTALK 0μs/div toc2 OUT 2V/div OUT2 AC-COUPLED 0mV/div DYNAMIC RESPONSE MAJOR-CARRY TRANSITION DIGITAL FEEDTHROUGH ( =.4MHz) toc3 OUT_ V/div toc4 5V/div toc5 2V/div O OUT_ AC-COUPLED 5mV/div OUT_ AC-COUPLED 5mV/div 0μs/div 4μs/div 400ns/div V REF = +2.5V, R L = 2kΩ, C L = 200pF SWITCHING FROM CODE 000HEX TO FFFHEX V REF = +2.5V, R L = 2kΩ, C L = 200pF V REF = +2.5V, R L = 2kΩ, C L = 200pF = +5V, = 0 CODE SET to 800HEX NEGATIVE FULL-SCALE SETTLING TIME POSITIVE FULL-SCALE SETTLING TIME toc6 toc7 OUT_ 500mV/div OUT_ 500mV/div O O μs/div μs/div 6

7 Output s with Serial Interface PIN NAME FUNCTION Serial Clock Input. Serial data is loaded on the falling edge of. 2 Serial Data Input 3 L Load. L is an asynchronous active-low input that updates the outputs simultaneously. If L is driven low, the registers are transparent. 4 REF Reference Voltage Input 5 2 OUT_ Analog Output Signal 3 GND Ground 4 V DD Power Supply. Bypass V DD to GND with a 0.µF capacitor. DOUT Data Output (). DOUT is updated on the falling edge of. Pin Description 5 Asynchronous Clear (MAX5307). Active-low input to clear all s and registers. Resets all CLR outputs to zero. 6 Chip-Select Input (active-low) Detailed Description The are 2-bit, eight-channel, lowpower, voltage-output digital-to-analog converters (s) that are easily addressed using a simple 3-wire serial interface. These devices feature eight doublebuffered s using a common 6-bit serial to parallel shift register, a power-on reset (POR) circuit and eight output buffer amplifiers. Figure shows the block diagram of / MAX5307. The shift register converts a serial 6-bit word to parallel data for each input register operating with a clock rate of up to 5MHz. The 3-wire digital interface to the shift register consist of chip-select (), serial clock (), and data input (). Serial data at is loaded on the falling edge of. The eight double-buffered s consist of input and registers. The input registers are directly connected to the shift register and hold the result of the most recent write operation. The eight 2-bit registers hold the current output code for the respective. Data can be transferred from the input registers to the registers by either the hardware interface (L) or by software command. The output of s are buffered through eight Rail-to-Rail op amps. The has a digital output (DOUT) which can be used to daisy chain multiple devices on a single serial bus. The MAX5307 contains a hardware shutdown (CLR) to clear all internal registers and power-down all s. The require an external reference such as the MAX66 family. The reference voltage range is from 0.8V to V DD. POR circuitry gives the s a defined state during startup. At power-on, the outputs reset to zero through a 00kΩ resistor, providing additional safety for applications that drive valves or other transducers that need to be off at power-up. The feature low digital feedthrough and minimize glitch energy on MSB transitions. The 3- wire SPI, QSPI, MICROWIRE and DSP-compatible serial interface saves additional circuit board space. Serial Interface Configuration The 3-wire serial interface are compatible with MICROWIRE, SPI, QSPI, and DSPs (Figure 2 and Figure 3). The chip-select input () frames the serial data loading at. Following s high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial clock input (). Each serial word is 6 bits, the first four bits are the control word followed by 2 data bits (MSB first) as shown in Table. The 2-bit code is unipolar binary with LSB = V REF /4096. The serial input register transfers its contents to the input registers after loading 6 bits of data and driving high. must be brought high for a minimum of 20ns before the next write sequence since a write Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. 7

8 Output s with Serial Interface Table. Serial Interface Configuration CONTROL BITS MSB 6-BIT SERIAL WORD DATA BITS LSB C3 C2 C C0 D D0 D09 D08 D07 D06 D05 D04 D03 D02 D0 D00 DESC. FUNCTION X X X X X X X X X X X X NOP No Operation X X X X X X X X X X X X RESET RESET All Internal Registers. Power-down s, outputs pulled down with 00kΩ. Equivalent to software CLR. D D0 to Input Register, D D0 to Input Register 2, D D0 to Input Register 3, D D0 to Input Register 4, D D0 to Input Register 5, D D0 to Input Register 6, D D0 to Input Register 7, D D0 to Input Register 8, D D0 to Input Registers 4 and Registers 4, Outputs Updated (Write-Thru). D D0 to Input Registers and Registers, Outputs Updated (Write-Thru). D D0 to Input Registers and Registers, Outputs Updated (Write-Thru). D D0 to Input Registers, Outputs Unchanged X X X X 8 Input Registers to Registers Indicated by Ones, Outputs Updated, Equivalent to Software L (No effect on s indicated by 0 s.) X = Don t Care 8

9 Output s with Serial Interface V DD (MAX5307) CLR MAX5307 SERIAL TO PARALLEL SHIFT OUT OUT2 OUT3 OUT4 () DOUT 5 5 OUT5 6 6 OUT6 7 7 OUT7 8 8 OUT8 L GND REF Figure. Functional Block Diagram sequence is initiated on a falling edge of. If goes high prior to completing 6 cycles of, the input data is discarded. To initiate a new data transfer, drive low again. The serial clock () can be either high or low between write pulses. Figure 4 shows the timing diagram for the complete 3-wire serial interface transmission. The digital inputs are doublebuffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the register(s), the register(s) can be loaded directly, or all eight registers can be updated simultaneously from the input registers. Shutdown Modes The include three software-controlled shutdown modes that reduce the supply current to less than µa. In two of the three shutdown modes (shutdown 2 and 3) the outputs are independently con- 9

10 Output s with Serial Interface Table 2. Serial Interface Power-up and Power-down Commands CONTROL BITS C3 C2 C C DATA BITS 3 2 D03 D02 D0 D00 X X 0 X X DESC. FUNCTION Power- Up Shutdown Power-Up individual buffers indicated by data in through 8. A one indicates the output is active. A zero does not affect the s present state. Shutdown individual buffers indicated by data in through 8. A one indicates the output is high-impedance. A zero does not affect the s present state. 0 X X Shutdown 2 Shutdown individual buffers indicated by data in through 8. A one indicates the is shutdown and the output is connected to GND through a kω resistor. A zero does not affect the s present state. 0 0 X X Shutdown 3 Shutdown individual buffers indicated by data in through 8. A one indicates the is shutdown and the output is connected to GND through a 00kΩ resistor. A zero does not affect the s present state. X = Don t Care nected to ground through a kω or 00kΩ (default) resistor for each. The third shutdown (shutdown ) command leaves the s outputs high impedance. Table 2 lists the three shutdown modes of operation as well as the power-up command. Serial-Data Output (DOUT) The DOUT () follows with a 6 clock cycle delay. The DOUT is capable of driving 20pF load with a 50ns (max) delay from the falling edge of. DOUT is primarily used for daisy-chaining multiple devices. Optionally, DOUT can be used to monitor the serial interface for valid communications by connecting DOUT to a microprocessor input. 0

11 Output s with Serial Interface DOUT* SK SO SI* I/O MICROWIRE PORT *THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE, BUT MAY BE USED FOR TRANSMISSION VERIFICATION PURPOSES. Figure 2. Connections for MICROWIRE MAX5307 DOUT* MISO* MOSI SCK I/O +5V SS SPI/QSPI PORT CPOL = 0, CPHA = 0 *THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5307, BUT MAY BE USED FOR TRANSMISSION VERIFICATION PURPOSES. Figure 3. Connections for SPI/QSPI Hardware Clear (CLR) The MAX5307 has an active low CLR input. Drive CLR low to clear all internal registers, shutdown all s, and terminate all outputs to GND through 00kΩ resistors. CLR is asynchronous and can be applied at any time. If CLR is toggled low during loading of a serial word, that word will terminate and must be reloaded. Reference Input The external reference input has a typical input impedance of 200kΩ. The input voltage range is from 800mV to V DD. V DD can be used as the reference for the. The outputs are then ratiometric to V DD. Output Buffer The rail-to-rail buffer amplifier is stable with any combination of resistive loads greater than 2kΩ and capacitive loads less than 500pF. With a capacitive load of 200pF the output buffers have a slew rate of V/µs. For a /4 FS to 3/4 FS output transition, the amplifier output typically settles to /2 LSB in less than 0µs when loaded with 2kΩ in parallel with 200pF. Power-On Reset The have a POR circuit to set the s output to zero when V DD is first applied. This ensures that unwanted output voltages will not occur immediately following a system startup, such as after a loss of power. Upon initial power-up the POR circuit ensures that all registers are cleared, the s are powered-down, and their outputs are terminated to GND through a 00kΩ resistor. Application Information Daisy-Chaining Devices Any number of can be daisy-chained by connecting the DOUT pin of one device to the pin of the following device in the chain (Figure 5). To write to the chain, drive low until all n x 6 clock cycles (where n is the number of devices in the chain) and associated data have been applied to the first device. When is driven high, each device in the chain acts on the 6 bits in its input register. To adjust a single device in the chain, a No-Operation (NOP) command must be loaded for all other devices. Figure 6 shows an alternate method of connecting several s or MAX5307s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input () is required for each IC. Unipolar Output The are normally configured for unipolar output. Table 3 lists the unipolar output voltages vs. digital codes. Bipolar Output The outputs can be configured for bipolar operation using Figure 7 s circuit. V OUT = V REF [(2D / )] where D is the decimal value of the s binary input code. Table 4 shows digital codes (offset binary) and corresponding output voltages for the Figure 7 circuit.

12 Output s with Serial Interface Power-Supply Considerations On power-up, all input and registers are cleared and DOUT is in low. X X D4 DOUT X D5* D4* D3* D2* D* t PWH t DS t S D5 t DH t CL t CH D3 t SDL t SDH Bypass V DD to GND with a 4.7µF capacitor in parallel with a 0.µF capacitor. Use short lead lengths and place the bypass capacitors as close to the supply pins as possible. D2 D D0 D0* t H X X X CLR t CLRPWL *PREVIOUS DATA L t LPWL t S ±0.5LSB V OUT_ Figure 4. Timing Diagram Table 3. Unipolar Code Table CONTENTS MSB LSB ANALOG OUTPUT V REF ( ) V REF ( ) VREF V REF ( ) = V REF ( ) V REF ( ) V Table 4. Bipolar Code Table CONTENTS MSB LSB ANALOG OUTPUT +V 2047 REF ( ) V REF ( ) V 0 -V REF ( ) V 2047 REF ( ) V REF ( ) = -V REF

13 Output s with Serial Interface DOUT DOUT DOUT Figure 5. Daisy-Chaining s TO OTHER SERIAL DEVICES 2 3 TO OTHER SERIAL DEVICES MAX5307 MAX5307 MAX5307 Figure 6. Multiple s or MAX5307s Sharing a Common Line V REF REF R R2 Chip Information TRANSISTOR COUNT: 9,000 PROCESS TECHNOLOGY: BiCMOS MAX5307 OUT +5V -5V V OUT R2 = R Figure 7. Bipolar Output Circuit 3

14 Output s with Serial Interface (MAX5307) CLR () DOUT L V DD SHIFT S S S S 2-BIT 2-BIT 8 Simplified Block Diagram OUTPUT BUFFER OUTPUT BUFFER OUT OUT8 GND 4

15 Output s with Serial Interface Package Information TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY I Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.