+3V/+5V, 12-Bit, Serial, Multiplying DACs

Transcription

1 19-126; Rev 1; 9/2 +3/+5, 12-Bit, Serial, Multiplying DACs General Description The are 12-bit, current-output, 4-quadrant multiplying digital-to-analog converters (DACs). These devices are capable of providing unipolar or bipolar outputs when operating from either a single +5 () or +3 () power supply. An internal power-on-reset circuit clears all DAC registers on power-up, setting the DAC output voltage to. The SPI /QSPI and MICROWIRE -compatible 3- wire serial interface saves board space and reduces power dissipation compared with parallel-interface devices. The feature double-buffered interface logic with a 12-bit input register and a 12-bit DAC register. Data in the DAC register sets the DAC output voltage. Data is loaded into the input register through the serial interface. The LOAD input trafers data from the input register to the DAC register, updating the DAC output voltage. The are available in an 8-pin DIP package or a space-saving 1-pin µmax package. The µmax package provides an asynchronous clear (CLR) input that clears all DAC registers when pulled to, setting the output voltage to. Applicatio Automatic Calibration Gain Adjustment Traducer Drivers Process-Control I/O Boards Digitally Controlled Filters Motion-Controlled Systems µp-controlled Systems Programmable Amplifiers/Attenuators Functional Diagram Features Single-Supply Operation: +4.5 to () +2.7 to +3.6 () 12.5MHz 3-Wire Serial Interface SPI/QSPI and MICROWIRE Compatible Power-On Reset Clears DAC Output to Zero Asynchronous Clear Input Clears DAC Output to Zero oltage Mode or Bipolar Mode Operation with a Single Power Supply Schmitt-Trigger Digital Inputs for Direct Optocoupler Interface.4µA Supply Current 1-Pin µmax Package Ordering Information PART TEMP RANGE PIN- PACKAGE 8 Plastic DIP 8 Plastic DIP 1 µmax LINEARITY () ACPA BCPA ACUB C to +7 C C to +7 C C to +7 C /2 /2 BCUB C to +7 C 1 µmax AEPA -4 C to +85 C 8 Plastic DIP /2 BEPA -4 C to +85 C 8 Plastic DIP AEUB -4 C to +85 C 1 µmax /2 BEUB -4 C to +85 C 1 µmax Ordering Information continued at end of data sheet. Pin Configuratio 12-BIT D/A CONERTER R FB A* TOP IEW CLR* LOAD 12-BIT DAC REGISTER POWER-ON RESET A SCLK CLR SCLK 12-BIT SHIFT REGISTER SCLK LOAD 4 5 DIN LOAD 5 6 DIN *µmax PACKAGE ONLY DIN DIP µmax SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS to...6, to...2 Digital Inputs (SCLK, DIN, LOAD, CLR) to to 6 to to ( +.3) A to D...±.3 Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate 9.9mW/ C above +7 C)...727mW µmax (derate 5.6mW/ C above +7 C)...444mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Operating Temperature Ranges MAX55 C... C to +7 C MAX55 E...-4 C to +85 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C ( = +4.5 to +5.25, = 5, = A =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 1) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Gain Tempco ( Gain/ Temp) SYMBOL N INL DNL CONDITIONS Guaranteed monotonic over temperature A Using internal feedback A resistor (R FB ) B ±2 Using internal feedback resistor (R FB ) (Note 2) MIN TYP MAX 12 /2 B A /2 B ±.2 UNITS Bits ppm/ C Power-Supply Rejection PSR = +5%, -1% 2 ppm/% DYNAMIC PERFORMANCE (Note 3) Current Settling Time t S T A = +25 C, to 1/2, load is 1Ω 13pF, DAC register alternately loaded with 1s and s.8 1 µs Digital-to-Analog Glitch =, load is 1Ω 13pF, DAC register alternately loaded with 1s and s.65 2 n-s AC Feedthrough at = 5 P-P at 1kHz, DAC register loaded with all s.3 1 m P-P Total Harmonic Distortion THD = 6 RMS at 1kHz, DAC register loaded with all 1s -85 db Output Noise-oltage Deity 1Hz to 1kHz, measured between and n/ Hz 2

3 ELECTRICAL CHARACTERISTICS (continued) ( = +4.5 to +5.25, = 5, = A =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 1) PARAMETER ERENCE INPUT Input Resistance Input Resistance Tempco Reference -3dB Bandwidth ANALOG PUT Leakage Current Capacitance DIGITAL INPUTS SYMBOL R BW C DAC register loaded with all s CONDITIONS Measured between and =.31 P-P, R L = 5Ω, code = full-scale Code = zero scale (Note 2) Code = full scale (Note 2) T A = +25 C T A = T MIN to T MAX MIN TYP MAX ±.15 ±5 ± UNITS kω ppm/ C khz na pf Input High oltage IH 2.4 Input Low oltage IL.8 Input Hysteresis HYST LOAD, CLR, DIN, and SCLK, = m Input Leakage Current I IN CLR CLR = CLR = 18 1 µa SCLK, LOAD, DIN Inputs at or Input Capacitance C IN Inputs at or (Note 2) 8 pf SWITCHING CHARACTERISTICS SCLK Pulse Width High t CH 25 SCLK Pulse Width Low t CL 25 DIN Data to SCLK Setup t DS 15 DIN Data to SCLK Hold t DH 15 LOAD Pulse Width t LD 2 SCLK to LOAD t SL LOAD High to SCLK t LC 15 CLR Pulse Width t CLR 2 POWER SUPPLY Supply oltage Supply Current I DD All digital inputs at IL or IH, CLR = All digital inputs at or, CLR =.4 5 µa ma 3

4 ELECTRICAL CHARACTERISTICS ( = +2.7 to +3.6, = 2.5, = A =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 Bits Integral Nonlinearity INL A /2 B Differential Nonlinearity Gain Error Gain Tempco ( Gain/ Temp) DNL Guaranteed monotonic over temperature Using internal feedback resistor (R FB ) Using internal feedback resistor (R FB ) (Note 2) A /2 B A B ±2 ±.3 ppm/ C Power-Supply Rejection PSR = +2%, -1% 1 ppm/% DYNAMIC PERFORMANCE (Note 3) Current Settling Time t S T A = +25 C, to 1/2, load is 1Ω 13pF, DAC register alternately loaded with 1s and s.12 1 µs Digital-to-Analog Glitch =, load is 1Ω 13pF, DAC register alternately loaded with 1s and s.6 2 n-s AC Feedthrough at = 3 P-P at 1kHz, DAC register loaded with all s.2.6 m P-P Total Harmonic Distortion THD = 6 RMS at 1kHz, DAC register loaded with all 1s -85 db Output Noise-oltage Deity 1Hz to 1kHz, measured between and n/ Hz ERENCE INPUT Input Resistance R Measured between and kω Input Resistance Tempco 7.5 ppm/ C Reference -3dB Bandwidth BW =.31 P-P, R L = 5Ω, code = full-scale 725 khz ANALOG PUT Leakage Current DAC register loaded with all s T A = +25 C T A = T MIN to T MAX ±.13 ±5 ±25 na Capacitance C Code = zero code (Note 2) 14 2 Code = full scale (Note 2) 2 3 pf 4

5 ELECTRICAL CHARACTERISTICS (continued) ( = +2.7 to +3.6, = 2.5, = A =, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 1) PARAMETER DIGITAL INPUTS Input High oltage Input Low oltage Input Hysteresis Input Leakage Current Input Capacitance SWITCHING CHARACTERISTICS SYMBOL IH IL HYST I IN C IN CLR CONDITIONS LOAD, CLR, DIN, and SCLK, = 3 SCLK, LOAD, DIN Inputs at or (Note 2) CLR = CLR = Inputs at or MIN TYP MAX UNITS m µa pf SCLK Pulse Width High t CH 4 SCLK Pulse Width Low t CL 4 DIN Data to SCLK Setup t DS 15 DIN Data to SCLK Hold t DH 15 LOAD Pulse Width t LD 3 SCLK to LOAD t SL LOAD High to SCLK t LC 15 CLR Pulse Width t CLR 3 POWER SUPPLY Supply oltage Supply Current I DD All digital inputs at IL or IH, CLR =.1.5 All digital inputs at or, CLR =.7 5 µa ma Note 1: A and CLR are for µmax only. Note 2: Guaranteed by design. Not subject to production testing. Note 3: Parametric limits are provided for design guidance, and are not production tested. 5

6 Typical Operating Characteristics (T A = +25 C, unless otherwise noted.) THD + N (db) TOTAL HARMONIC DISTORTION vs. FREQUENCY PUT AMPLIFIER = MAX4166 1st 5 HARMONICS =.42 P-P, R L = 5Ω INPUT CODE = ALL 1s FREQUENCY (MHz) /552 toc3 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. LOGIC INPUT OLTAGE IN AT DIN, SCLK, AND LOAD CLR = = 3.3 = 2.7 = LOGIC INPUT OLTAGE, IN () /552 toc4 INL () INL vs. ERENCE OLTAGE = ERENCE OLTAGE () TOC1A DNL () DNL vs. ERENCE OLTAGE = ERENCE OLTAGE () GAIN (db) TOC2A INL () MULTIPLYING FREQUENCY RESPONSE OR =.31 P-P, R L = 5Ω INPUT CODE = ALL 1s PUT AMPLIFIER = MAX FREQUENCY (MHz) INL vs. ERENCE OLTAGE = ERENCE OLTAGE () /552 toc2 ERENCE AC FEEDTHROUGH (db) /MAX5452 TOC4A DNL () DNL vs. ERENCE OLTAGE = ERENCE OLTAGE () ERENCE AC FEEDTHROUGH vs. FREQUENCY OR =.31 P-P, R L = 5Ω INPUT CODE = ALL s PUT AMPLIFIER = MAX FREQUENCY (MHz) MAX4551/552 TOC1 TOC3A 6

7 Pin Description DIP PIN µmax NAME A LOAD 5 6 DIN 6 7 SCLK DAC Current Output Analog Ground Supply oltage Serial-Data Input FUNCTION Digital Ground. Also Analog Ground for DIP package. Active-Low Load DAC Input. Driving this asynchronous input low trafers the contents of the input register to the DAC register. Serial-Clock Input. The serial input data is clocked in on SCLK s rising edge. 8 CLR Clear DAC Input. Clears the DAC register. Tie to or float if not used. Reference Input Feedback Resistor R R R R 2R 2R 2R 2R 2R 2R R FB * A R FB * = R D11 (MSB) D1 D9 D1 DO () Figure 1. Simplified Circuit 7

8 DIN SCLK LOAD CLR t DS BIT 11 MSB t DH 1 2 t CH t CL BIT 1 BIT 1 LOAD SERIAL DATA INTO INPUT REGISTER 11 t SL BIT t LD t CLR t LC Figure 2. Write-Cycle Timing Diagram Detailed Description The digital-to-analog converter (DAC) circuits coist of a laser-trimmed, thin-film R-2R resistor array with NMOS current switches (Figure 1). Binary-weighted currents are switched to either or A, depending on the status of each input data bit. Although the currents at and A depend on the digital input code, the sum of the two output currents is always equal to the input current at. The output current (I ) can be converted into a voltage by adding an external output amplifier (Figure 3). The input accepts a wide range of signals, including fixed and time-varying voltage or current inputs. If a current source is used at the reference input, use a low-tempco, external feedback resistor in place of the internal feedback resistor (R FB ) to minimize gain variation with temperature. The internal feedback resistor (R FB ) is compeated with an NMOS switch that matches the NMOS switches used in the R-2R array, resulting in excellent supply rejection and gain-temperature coefficient. The pin output capacitance (C ) is code dependent. C is typically 14pF at hex and 2pF at FFFhex. Serial Interface The serial interface is compatible with the SPI/QSPI and MICROWIRE serial-interface standards. These devices accept serial clocks up to 12.5MHz (5% duty cycle). If the SCLK input is not Table 1. Unipolar Binary-Code Table for Circuit of Figure 3 DIGITAL INPUT MSB ANALOG PUT = DIN SCLK R1 1Ω +5 (+3) R2 5Ω C1 15pF LOAD A 3 ( ) ARE FOR Figure 3. Unipolar Operation 8

9 R1 1Ω ( ) ARE FOR +5 (+3) R4 2kΩ R2 5Ω A SCLK LOAD DIN C1 33pF R3 1kΩ R5 2kΩ Figure 4. Bipolar Operation Table 2. Offset Binary-Code Table for Circuit of Figure 4 DIGITAL INPUT MSB ANALOG PUT symmetrical, then the clock signal used must meet the t CH and t CL requirements given in the Electrical Characteristics. Figure 2 shows the timing diagram. The most significant bit (MSB) is always loaded first on SCLK s rising edge. When all data is shifted into the input register, the DAC register is loaded by driving the LOAD signal low. The DAC register is traparent when LOAD is low and latched when LOAD is high. The digital inputs are compatible with CMOS logic levels. The s inputs are also compatible with TTL logic Unipolar Operation Figure 3 shows the s basic application. This circuit is used for unipolar operation or 2- quadrant multiplication. The code table for this mode is given in Table 1. Note that the output s polarity is the opposite of the reference voltage polarity. In many applicatio the gain accuracy is sufficient and gain adjustment is not necessary. In these cases, resistors R1 and R2 in Figure 3 can be omitted. If the gain is trimmed and the DAC is operated over a wide temperature range, use low-tempco (<3ppm/ C) resistors for R1 and R2. Capacitor C1 provides phase compeation and reduces overshoot and ringing when fast amplifiers are used at the DAC s output. Bipolar Operation Figure 4 shows the operating in bipolar (or 4-quadrant multiplying) mode. Matched resistors R3, R4, and R5 must be of the same material (preferably metal film or wire-wound) for good temperaturetracking characteristics (<15ppm/ C) and should match to.1% for 12-bit performance. The output code is offset binary, as listed in Table 2. To adjust the circuit, load the DAC with a code of 1 and trim R1 for a output. With R1 and R2 omitted, an alternative zero trim is needed to adjust the ratio of R3 and R4 for out. Trim full scale by loading the DAC with all s or 1s and adjusting the amplitude or varying R5 until the desired positive or negative output is obtained. In applicatio where gain trim is not required, omit resistors R1 and R2. If gain trim is desired and the DAC is operated over a wide temperature range, then low-tempco (<3ppm/ C) resistors should be used. 9

10 Applicatio Information Output Amplifier For best linearity, terminate and at exactly. In most applicatio, is connected to an inverting op amp s summing junction. The amplifier s input offset voltage can degrade the DAC s linearity by causing to be terminated to a nonzero voltage. The resulting error is: Error oltage = OS (1 + R FB / R O ) where OS = is the op amp s offset and R O is the DAC s output resistance, which is code dependent. The maximum error voltage (R O = ) is 2 OS ; the minimum error voltage (R O = ) is OS. To minimize this error, use a low-offset amplifier such as the MAX4166 (unipolar output) or the MAX427 (bipolar output). Otherwise, the amplifier offset must be trimmed to zero. A good guide rule is that OS should be no more than 1/1. The output amplifier s input bias current (I B ) can also limit performance, since I B x R FB generates an offset error. Choose an op amp with an I B much less than (e.g., one-tenth) the DAC s 1 output current (typically 111nA when = 5, and 55.5nA when = 2.5). Offset and linearity can also be impaired if the output amplifier s noninverting input is grounded through a bias-current compeation resistor. This resistor adds to the offset at this pin and thus should not be used. For best performance, connect the noninverting input directly to ground. In static or DC applicatio, the output amplifier s characteristics are not critical. In higher speed applicatio in which either the reference input is an AC signal or the DAC output must quickly settle to a new programmed value, the output op amp s AC parameters must be coidered. A compeation capacitor, C1, may be required when the DAC is used with a high-speed output amplifier. The purpose of the capacitor is to cancel the pole formed by the DAC output capacitance, C, and the internal feedback resistor, R FB. Its value depends on the type of op amp used but typically ranges from 14pF to 3pF. Too small a value causes output ringing, while excess capacitance overdamps the output. C1 s size can be minimized and the output voltage settling time improved by keeping the circuit-board trace short and stray capacitance at as low as possible. ERENCE OLTAGE DIN Single-Supply Operation Reference oltage The are true 4-quadrant DACs, making them ideal for multiplying applicatio. The reference input accepts both AC and DC signals within a voltage range of ±6. The R-2R ladder is implemented with thin-film resistors, enabling the use of unipolar or bipolar reference voltages with only a single power supply for the DAC. The voltage at the input sets the DAC s full-scale output voltage. If the reference is too noisy, it should be bypassed to (A on the 1-pin µmax package) with a.1µf ceramic capacitor located as close to the pin as possible. oltage Mode () The can be conveniently used in voltage mode, single-supply operation with biased at any voltage between and. must not be allowed to go.3 lower than or.3 higher than. Otherwise, internal diodes turn on, causing a high current flow that could damage the device. Figure 5 shows the connected as a voltage output DAC. In this mode of operation, the pin is connected to the reference-voltage source, and the pin is connected to the PCB ground plane. The DAC output now appears at the pin, which has a cotant resistance equal to the reference input resistance (11kΩ typ). This output should be buffered with an op amp when a lower output impedance is required. The pin is not used in this mode. The reference input () impedance is code dependent, and the circuit s respoe time depends on the reference source s behavior with changing load conditio. +5 SCLK LOAD Figure 5. Single-Supply, oltage Mode Operation 1

11 +5 (+3) D TO MAX616 ADJ 16MΩ A MAX4167 An advantage of voltage mode operation is that a negative reference is not required for a positive output. Note that the reference input () must always be positive and is limited to no more than 2 when is 5. The unipolar and bipolar circuits in Figures 3 and 4 can be converted to voltage mode. Current Mode Figure 6 shows the in a current output configuration in which the output amplifier is powered from a single supply, and A is biased to With applied to the input, the output can be programmed from 1.23 (zero code) to 2.46 (full scale). With 2.45 applied to, the output can be programmed from 1.23 (zero code) to.1 (full scale). The MAX4166 op amp that drives A maintai the 1.23 bias as A s impedance changes with the DAC s digital code, from high impedance (zero code) to 7kΩ minimum (full scale). Using an AC Reference In applicatio where reference voltage has AC signal components, the have multiplying capability within the reference input range of ±6. If the DAC and the output amplifier are operated with a single C1 ( ) ARE FOR MAX4167 Figure 6. Single-Supply, Current Mode Operation +5 (+3) AC ERENCE INPUT ( ) ARE FOR 1kΩ 1kΩ MAX4166 supply voltage, then an AC reference input can be offset with the circuit shown in Figure 7 to prevent the DAC output voltage from exceeding the output amplifier s negative output rail. The reference input s typical -3dB bandwidth is greater than 7kHz, as shown in the Typical Operating Characteristics graphs. Offsetting A The provide separate A and inputs in the µmax package. With this package, A can be biased above to provide an arbitrary nonzero output voltage for a input code (Figure 8). Layout, Grounding, and Bypassing Bypass with a.1µf capacitor, located as close to and as possible. The ground pi (A and ) should be connected in a star configuration to the highest quality ground available, which should be located as close to the as possible. Since and the output amplifier s noninverting input are seitive to offset voltage, nodes that are to be grounded should be connected directly to a singlepoint ground through a separate, low-resistance (less than.2ω) connection. The current at and A varies with input code, creating a code-dependent error if these terminals are connected to ground (or virtual ground) through a resistive path. Parasitic coupling of the signal from to is an error source in dynamic applicatio. This coupling is normally a function of board layout and pin-to-pin package capacitance. Minimize digital feedthrough with guard traces between digital inputs,, and pi. Figure 7. Single-Supply AC Reference Input Circuit 11

12 IN BIAS A Figure 8. A Bias Current The have high-impedance digital inputs. To minimize noise pickup, tie them to either or when they are not in use. As a good practice, connect active inputs to or through highvalue resistors (1MΩ) to prevent static charge accumulation if the pi are left floating, such as when a circuit card is left unconnected. The CLR input on the µmax device has an internal pullup resistor with a typical value of 125kΩ. If the CLR input is not used, tie it to to minimize supply current. _Ordering Information (continued) PART ACPA BCPA TEMP RANGE C to +7 C C to +7 C ACUB C to +7 C 1 µmax BCUB C to +7 C 1 µmax AEPA -4 C to +85 C 8 Plastic DIP BEPA -4 C to +85 C 8 Plastic DIP AEUB -4 C to +85 C 1 µmax BEUB -4 C to +85 C 1 µmax Chip Information TRANSISTOR COUNT: 887 SUBSTRATE CONNECTED TO PIN- PACKAGE 8 Plastic DIP 8 Plastic DIP LINEARITY () /2 /2 /2 /2 Package Information For the latest package outline information, go to Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 12 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.