PART MAX7427EUA MAX7426CPA MAX7427CPA TOP VIEW. Maxim Integrated Products 1

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1 19-171; Rev ; 4/ 5th-Order, Lowpass, Elliptic, General Description The 5th-order, lowpass, elliptic, switched-capacitor filters (SCFs) operate from a single +5 (MAX7426) or +3 (MAX7427) supply. The devices draw only.8ma of supply current and allow corner frequencies from 1Hz to 12kHz, making them ideal for low-power post-dac filtering and anti-aliasing applications. They can be put into a low-power mode, reducing supply current to.2µa. Two clocking options are available: self-clocking (through the use of an external capacitor) or external clocking for tighter cutoff-frequency control. An offset-adjust pin allows for adjustment of the DC output level. The deliver 37 of stopband rejection and a sharp rolloff with a transition ratio of Their fixed response limits the design task to selecting a clock frequency. ADC Anti-Aliasing Post-DAC Filtering Applications CT2 Base Stations Speech Processing Selector Guide PART TRANSITION RATIO OPERATING OLTAGE () MAX7426 r = MAX7427 r = Features 5th-Order, Elliptic Lowpass Filters Low Noise and Distortion: -8 THD + Noise Clock-Tunable Corner Frequency (1Hz to 12kHz) Single-Supply Operation +5 (MAX7426) +3 (MAX7427) Low Power.8mA (Operating Mode).2µA (Shutdown Mode) Available in 8-Pin µmax/pdip Packages Low Output Offset: ±4m PART MAX7426CUA MAX7426CPA MAX7426EUA Ordering Information TEMP. RANGE C to +7 C C to +7 C -4 C to +85 C PIN-PACKAGE 8 µmax 8 Plastic DIP 8 µmax MAX7426EPA -4 C to +85 C 8 Plastic DIP MAX7427CUA C to +7 C 8 µmax MAX7427CPA MAX7427EUA C to +7 C -4 C to +85 C 8 Plastic DIP 8 µmax MAX7427EPA -4 C to +85 C 8 Plastic DIP SUPPLY Typical Operating Circuit Pin Configuration TOP IEW.1µF DD SHDN COM 1 8 CLK INPUT CLOCK IN CLK MAX7426 MAX7427 OUT COM OUTPUT IN GND DD MAX7426 MAX SHDN OS OUT GND OS.1µF µmax/pdip Maxim Integrated Products 1 For free samples and the latest literature, visit or phone For small orders, phone

2 ABSOLUTE MAXIMUM RATINGS DD to GND to +6 IN, OUT, COM, OS, CLK, SHDN to ( DD +.3) OUT Short-Circuit Duration...1s Continuous Power Dissipation (T A = +7 C) 8-Pin µmax (derate 4.1mW/ C above +7 C)...33mW 8-Pin PDIP (derate 6.9mW/ C above +7 C)...552mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS MAX7426 Operating Temperature Ranges MAX742 _C_A... C to +7 C MAX742 _E_A...-4 C to +85 C Storage Temperature Range C to +16 C Lead Temperature (soldering, 1s)...+3 C ( DD = +5, filter output measured at OUT, 1kΩ 5pF load to GND at OUT, SHDN = DD, OS = COM,.1µF from COM to GND, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER FILTER Corner-Frequency Range Clock-to-Corner Ratio Clock-to-Corner Tempco Output oltage Range Output Offset oltage DC Insertion Gain with Output Offset Removed SYMBOL f C f CLK /f C OFFSET (Note 1) CONDITIONS IN = COM = DD / 2 COM = DD / 2 (Note 2) MIN TYP MAX.1 to 9 1: DD -.25 ±4 ± UNITS khz ppm/ C m Total Harmonic Distortion plus Noise THD+N f IN = 2Hz, IN = 4p-p, measurement bandwidth = 22kHz -81 Offset oltage Gain A OS OS to OUT +1 / COM oltage Range COM Input, COM externally driven Output, COM internally driven DD -.5 DD DD DD -.2 DD DD Input oltage Range at OS Input Resistance at COM Clock Feedthrough Resistive Output Load Drive OS R COM R L Measured with respect to COM T A = +25 C ± kω mp-p kω Maximum Capacitive Load at OUT C L 5 5 pf Input Leakage Current at COM Input Leakage Current at OS CLOCK Internal Oscillator Frequency f OSC SHDN = GND, COM = to DD OS = to DD C OSC = 1pF (Note 3) ±.2 ±1 ±.2 ± µa µa khz Clock Output Current (internal oscillator mode) I CLK ±8 ±12.5 µa Clock Input High Clock Input Low IH IL

3 ELECTRICAL CHARACTERISTICS MAX7426 (continued) ( DD = +5, filter output measured at OUT, 1kΩ 5pF load to GND at OUT, SHDN = DD, OS = COM,.1µF from COM to GND, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER POWER REQUIREMENTS SYMBOL SHDN = GND Measured at DC ELECTRICAL CHARACTERISTICS MAX7427 CONDITIONS MIN TYP MAX Supply oltage DD Supply Current I DD Operating mode, no load.8 1. Shutdown Current Power-Supply Rejection Ratio SHUTDOWN SHDN Input High SHDN Input Low I SHDN PSRR SDH SDL ( DD = +3, filter output measured at OUT pin, 1kΩ 5pF load to GND at OUT, SHDN = DD, OS = COM,.1µF from COM to GND, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SHDN Input Leakage Current SHDN = to DD ±.2 ±1 µa FILTER CHARACTERISTICS Corner-Frequency Range Clock-to-Corner Ratio Clock-to-Corner Tempco Output oltage Range Output Offset oltage DC Insertion Gain with Output Offset Removed f C f CLK /f C OFFSET (Note 1) IN = COM = DD / 2 COM = DD / 2 (Note 2) 7.1 to : DD -.25 ±4 ± UNITS ma µa khz ppm/ C m Total Harmonic Distortion plus Noise THD+N f IN = 2Hz, IN = 2.5p-p, measurement bandwidth = 22kHz -79 Offset oltage Gain A OS OS to OUT +1 / COM oltage Range Input oltage Range at OS Input Resistance at COM Clock Feedthrough Resistance Output Load Drive Maximum Capacitive Load at OUT COM OS R COM R L C L Measured with respect to COM T A = +25 C DD DD DD ± Input Leakage Current at COM SHDN = GND, COM = to DD ±.2 ±1 µa Input Leakage Current at OS OS = to DD ±.2 ±1 µa kω mp-p kω pf 3

4 ELECTRICAL CHARACTERISTICS MAX7427 (continued) ( DD = +3, filter output measured at OUT pin, 1kΩ 5pF load to GND at OUT, SHDN = DD, OS = COM,.1µF from COM to GND, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER CLOCK Internal Oscillator Frequency Clock Output Current (internal oscillator mode) Clock Input High Clock Input Low POWER REQUIREMENTS Supply oltage Supply Current Shutdown Current Power-Supply Rejection Ratio SHUTDOWN SHDN Input High SYMBOL f OSC I CLK IH IL DD I DD I SHDN PSRR SDH CONDITIONS C OSC = 1pF (Note 3) CLK = or 3 Operating mode, no load SHDN = GND Measured at DC MIN TYP MAX SHDN Input Low SDL.5 SHDN Input Leakage Current SHDN = to DD ±.2 ±1 µa ±7.5 ± UNITS khz µa ma µa ELLIPTIC FILTER CHARACTERISTICS (r = 1.25) ( DD = +5 for MAX7426, DD = +3 for MAX7427, filter output measured at OUT, 1kΩ 5pF load to GND at OUT, SHDN = DD, COM = OS = DD / 2, f CLK = 1kHz, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS f IN =.38f C f IN =.68f C Insertion Gain with DC Gain Error Removed (Note 4) f IN =.87f C f IN =.97f C f IN = f C f IN = 1.25f C f IN = 1.43f C f IN = 3.25f C Note 1: The maximum f C is defined as the clock frequency f CLK = 1 f C at which the peak SINAD drops to 68 with a sinusoidal input at.2f C. Note 2: DC insertion gain is defined as OUT / IN. Note 3: f OSC (khz) / C OSC (C OSC in pf). Note 4: The input frequencies, f IN, are selected at the peaks and troughs of the ideal elliptic frequency responses. 4

5 GAIN () FREQUENCY RESPONSE INPUT FREQUENCY (khz) f C = 1kHz r = 1.25 MAX7426/27-2 Typical Operating Characteristics ( DD = +5 for MAX7426, DD = +3 for MAX7427, f CLK = 1kHz, SHDN = DD, COM = OS = DD / 2, T A = +25 C, unless otherwise noted.) GAIN () PASSBAND FREQUENCY RESPONSE f C = 1kHz r = INPUT FREQUENCY (khz) MAX7426/27-4 PHASE SHIFT (DEGREES) PHASE RESPONSE INPUT FREQUENCY (khz) f C = 1kHz r = 1.25 MAX7426/27-6 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY OLTAGE SUPPLY OLTAGE () MAX7426/27-7 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE DD = +5 DD = TEMPERATURE ( C) MAX7426/27-8 5

6 Typical Operating Characteristics (continued) ( DD = +5 for MAX7426, DD = +3 for MAX7427, f CLK = 1kHz, SHDN = DD, COM = OS = DD / 2, T A = +25 C, unless otherwise noted.) THD + NOISE () MAX7426 TOTAL HARMONIC DISTORTION PLUS NOISE vs. INPUT SIGNAL AMPLITUDE B A SEE TABLE AMPLITUDE (p-p) MAX7426/27-1 THD + NOISE () MAX7427 TOTAL HARMONIC DISTORTION PLUS NOISE vs. INPUT SIGNAL AMPLITUDE SEE TABLE AMPLITUDE (p-p) B A MAX7426/27-12 Table 1. THD + Noise Test Conditions LABEL f IN (Hz) f C (khz) A 2 1 B 1k 5 f CLK (khz) 1 5 MEASUREMENT BANDWIDTH (khz)

7 Switched-Capacitor OSCILLATOR FREQUENCY (khz) INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY OLTAGE C OSC = 1pF SUPPLY OLTAGE () Typical Operating Characteristics (continued) ( DD = +5 for MAX7426, DD = +3 for MAX7427, f CLK = 1kHz, SHDN = DD, COM = OS = DD / 2, T A = +25 C, unless otherwise noted.) OSCILLATOR PERIOD (µs) INTERNAL OSCILLATOR PERIOD vs. SMALL CAPACITANCE (IN pf) DD = +5 DD = CAPACITANCE (pf) MAX7426/27-13 MAX7426/27-15 OSCILLATOR PERIOD (ms) OSCILLATOR FREQUENCY (khz) INTERNAL OSCILLATOR PERIOD vs. LARGE CAPACITANCE (IN nf) CAPACITANCE (nf) INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE DD = +5 C OSC = 1pF DD = +3 DD = +5 DD = TEMPERATURE ( C) MAX7426/27-14 MAX7426/27-16 DC OFFSET OLTAGE (m) DC OFFSET OLTAGE vs. TEMPERATURE DD = +3 DD = +5 MAX7426/27-17 DC OFFSET OLTAGE (m) DC OFFSET OLTAGE vs. SUPPLY OLTAGE MAX7426/ TEMPERATURE ( C) SUPPLY OLTAGE () 7

8 PIN NAME Detailed Description The family of 5th-order, elliptic, lowpass filters provides sharp rolloff with good stopband rejection. All parts operate with a 1:1 clock-tocorner frequency ratio. Most SCFs are designed with biquadratic sections. Each section implements two pole-zero pairs, and the sections can be cascaded to produce higher-order filters. The advantage to this approach is ease of design. However, this type of design is highly sensitive to component variations if any section s Q is high. The use an alternative approach, which is to emulate a passive network using switched-capacitor integrators with summing and scaling. The passive network may be synthesized using CAD programs or may be found in many filter books. Figure 1 shows a basic 5th-order ladder elliptic filter structure. A switched-capacitor filter that emulates a passive ladder filter retains many of the same advantages. The component sensitivity of a passive ladder filter is low when compared to a cascaded biquadratic design, because each component affects the entire filter shape rather than a single pole-zero pair. In other words, a R S C2 L2 C4 L4 FUNCTION 1 COM Common Input Pin. Biased internally at midsupply. Bypass externally to GND with a.1µf capacitor. To override internal biasing, drive with an external supply. 2 IN Filter Input 3 GND Ground 4 DD Positive Supply Input, +5 for MAX7426 or +3 for MAX7427 Pin Description 5 OUT Filter Output 6 OS Offset Adjust Input. To adjust output offset, bias OS with a resistive voltage-divider between an external supply and ground. Connect OS to COM if no offset adjustment is needed. 7 SHDN Shutdown Input. Drive low to enable shutdown mode; drive high or connect to DD for normal operation. 8 CLK Clock Input. Connect an external capacitor (C OSC ) from CLK to GND to set the internal oscillator frequency. To override the internal oscillator, connect to an external clock. mismatched component in a biquadratic design has a concentrated error on its respective poles, while the same mismatch in a ladder filter design spreads its error over all poles. Elliptic Characteristics Lowpass elliptic filters such as the provide the steepest possible rolloff with frequency of the four most common filter types (Butterworth, Bessel, Chebyshev, and elliptic). The high Q value of the poles near the passband edge combined with the stopband zeros allow for the sharp attenuation characteristic of elliptic filters, making these devices ideal for anti-aliasing and post-dac filtering in single-supply systems (see the Anti-Aliasing and Post-DAC Filtering section). In the frequency domain (Figure 2), the first transmission zero causes the filter s amplitude to drop to a minimum level. Beyond this zero, the response rises as the frequency increases until the next transmission zero. The stopband begins at the stopband frequency, f S. At frequencies above f S, the filter s gain does not exceed the gain at f S. The corner frequency, f C, is defined as the point where the filter output attenuation falls just below the passband ripple. The transition ratio (r) is defined as the ratio of the stopband frequency to the corner frequency: r = f S / f C The have a transition ratio of 1.25 and typically 37 of stopband rejection. + - IN C1 Figure 1. 5th-Order Ladder Elliptic Filter Network C3 C5 R L Clock Signal External Clock These SCFs are designed for use with external clocks that have a 4% to 6% duty cycle. When using an external clock, drive the CLK pin with a CMOS gate 8

9 GAIN () PASSBAND Figure 2. Elliptic Filter Response f C f C powered from to DD. arying the rate of the external clock adjusts the corner frequency of the filter: fc f S RIPPLE f TRANSITION RATIO = S fc f S f = CLK 1 STOPBAND FREQUENCY.1µF INPUT CLOCK SUPPLY IN CLK Estimate the input impedance of the filter by using the following formula: Z IN = DD MAX7426 MAX7427 GND Figure 3. Offset Adjustment Circuit SHDN OUT COM OS.1µF.1µF 1 f CLK CIN OUTPUT 5k 5k 5k Internal Clock When using the internal oscillator, the capacitance (C OSC ) on CLK determines the oscillator frequency: f OSC(kHz) = C OSC(pF) Since C OSC is in the low picofarads, minimize the stray capacitance at CLK so that it does not affect the internal oscillator frequency. arying the rate of the internal oscillator adjusts the filter s corner frequency by a 1:1 clock-to-corner frequency ratio. For example, an internal oscillator frequency of 1kHz produces a nominal corner frequency of 1kHz. Input Impedance vs. Clock Frequencies The s input impedance is effectively that of a switched-capacitor resistor (see the following equation), and is inversely proportional to frequency. The input impedance values determined by the equation represent the average input impedance, since the input current is not continuous. As a rule, use a driver with an output resistance less than 1% of the filter s input impedance. where f CLK = clock frequency and C IN = 1pF. Low-Power Shutdown Mode The have a shutdown mode that is activated by driving SHDN low. In shutdown mode, the filter supply current reduces to.2µa, and the output of the filter becomes high impedance. For normal operation, drive SHDN high or connect to DD. Applications Information Offset (OS) and Common-Mode (COM) Input Adjustment COM sets the common-mode input voltage and is biased at midsupply with an internal resistor-divider. If the application does not require offset adjustment, connect OS to COM. For applications where offset adjustment is required, apply an external bias voltage through a resistor-divider network to OS, as shown in Figure 3. For applications that require DC level shifting, adjust OS with respect to COM. (Note: Do not leave OS unconnected.) The output voltage is represented by these equations: OUT = ( IN COM) + OS DD COM = ( typical) 2 where ( IN - COM ) is lowpass filtered by the SCF and OS is added at the output stage. See the Electrical 9

10 + - INPUT CLOCK IN CLK DD Characteristics table for the input voltage range of COM and OS. Changing the voltage on COM or OS significantly from midsupply reduces the dynamic range. Power Supplies The MAX7426 operates from a single +5 supply, and the MAX7427 operates from a single +3 supply. Bypass DD to GND with a.1µf capacitor. If dual supplies are required, connect COM to the system ground and GND to the negative supply. Figure 4 shows an example of dual-supply operation. Singlesupply and dual-supply performance are equivalent. + MAX7426 MAX7427 GND *CONNECT SHDN TO - FOR LOW-POWER SHUTDOWN MODE. Figure 4. Dual-Supply Operation - * SHDN OUT COM OS OUTPUT.1µF.1µF For either single-supply or dual-supply operation, drive CLK and SHDN from GND (- in dual-supply operation) to DD. Use the MAX7427 for ±2.5, and use the MAX7426 for ±1.5. For ±5 dual-supply applications, refer to the MAX291/MAX292/MAX295/MAX296 and MAX293/MAX294/MAX297 data sheets. Input Signal Amplitude Range The optimal input signal range is determined by observing the voltage level at which the signal-to-noise plus distortion (SINAD) ratio is maximized for a given corner frequency. The Typical Operating Characteristics show the THD + Noise response as the input signal s peak-topeak amplitude is varied. Anti-Aliasing and Post-DAC Filtering When using the for anti-aliasing or post-dac filtering, synchronize the DAC (or ADC) and the filter clocks. If the clocks are not synchronized, beat frequencies may alias into the desired passband. Harmonic Distortion Harmonic distortion arises from nonlinearities within the filter. These nonlinearities generate harmonics when a pure sine wave is applied to the filter input. Table 2 lists typical harmonic distortion values with a 1kΩ load at T A = +25 C. TRANSISTOR COUNT: 1457 PROCESS: BiCMOS Chip Information Table 2. Typical Harmonic Distortion FILTER f CLK (khz) f IN (Hz) IN TYPICAL HARMONIC DISTORTION () (p-p) 2nd 3rd 4th 5th MAX k MAX k

11 Package Information 8LUMAXD.EPS 11

12 Package Information (continued) PDIPN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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