High-Speed, Low-Power, 3V/5V, Rail-to-Rail Single-Supply Comparators

Transcription

1 19-9; Rev 3; 6/97 High-Speed, Low-Power, 3V/5V, General Description The are single/dual/quad high-speed comparators optimized for systems powered from a 3V or 5V supply. These devices combine high speed, low power, and rail-to-rail inputs. Propagation delay is 8ns, while supply current is only 35µA per comparator. The input common-mode range of the / MAX94/MAX944 extends beyond both power-supply rails. The outputs pull to within.4v of either supply rail without external pull-up circuitry, making these devices ideal for interface with both CMOS and TTL logic. All input and output pins can tolerate a continuous shortcircuit fault condition to either rail. Internal hysteresis ensures clean output switching, even with slow-moving input signals. The features latch enable and device shutdown. The single and dual MAX94 are offered in a tiny µmax package. Both the single and dual MAX94 are available in 8-pin DIP and SO packages. The quad MAX944 comes in 14-pin DIP and narrow SO packages. Applications 3V/5V Systems Battery-Powered Systems Threshold Detectors/Discriminators Line Receivers Zero-Crossing Detectors Sampling Circuits Features Available in µmax Package Optimized for 3V and 5V Applications (operation down to.7v) Fast, 8ns Propagation Delay (5mV overdrive) Rail-to-Rail Input Voltage Range Low Power: 1mW Power Dissipation per Comparator (3V) 35µA Supply Current Low, 1mV Offset Voltage Internal Hysteresis for Clean Switching Outputs Swing mv of Power Rails CMOS/TTL-Compatible Outputs Output Latch ( only) Shutdown Function ( only) Ordering Information PART CPA CSA C/D EPA ESA EUA MJA TEMP. RANGE C to +7 C C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C -4 C to +85 C -55 C to +15 C PIN-PACKAGE 8 Plastic DIP 8 SO Dice* 8 Plastic DIP 8 SO 8 µmax 8 CERDIP Ordering Information continued at end of data sheet. * Dice are specified at T A = +5 C, DC parameters only. Pin Configurations TOP VIEW MAX94 OUTA 1 14 OUTD N.C. OUT LATCH A B IND- IND+ INC+ INC- INA- INA+ INB+ INB A B MAX944 D C IN+ IN- SHDN OUTB INB- INB+ OUTA INA- INA+ DIP/SO/µMAX DIP/SO/µMAX OUTB 7 8 OUTC DIP/SO Maxim Integrated Products 1 For free samples & the latest literature: or phone For small orders, phone ext

2 ABSOLUTE MAXIMUM RATINGS Power-Supply Ranges Supply Voltage to...+7v Differential Input Voltage...-.3V to ( +.3V) Common-Mode Input Voltage...-.3V to ( +.3V) L A T C H Input ( only)...-.3v to ( +.3V) S H D N Control Input ( only)...-.3v to ( +.3V) Continuous Power Dissipation (T A = +7 C) 8-Pin Plastic DIP (derate 9.9mW/ C above +7 C)...77mW 8-Pin SO (derate 5.88mW/ C above +7 C)...471mW 8-Pin µmax (derate 4.1mW/ C above +7 C)...33mW 8-Pin CERDIP (derate 8.mW/ C above +7 C)...64mW 14-Pin Plastic DIP (derate 1.mW/ C above +7 C)..8mW 14-Pin SO (derate 8.33mW/ C above +7 C)...667mW 14-Pin CERDIP (derate 9.9mW/ C above +7 C)...77mW Operating Temperature Ranges MAX94_C... C to +7 C MAX94_E...-4 C to +85 C MAX94_MJ _ C to +15 C Storage Temperature Range C to +16 C Lead Temperature (soldering, 1sec)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( =.7V to 6.V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C. See Note 14.) PARAMETER Positive Supply Voltage Input Voltage Range Input-Referred Trip Points Input Offset Voltage Input Bias Current Input Offset Current Common-Mode Rejection Ratio Power-Supply Rejection Ratio Output High Voltage Output Low Voltage Output Leakage Current SYMBOL V CMR V TRIP V OS I B I OS CMRR PSRR V OH V OL I LEAK (Note 1) V CM = V or V CM = (Note ) V CM = V or V CM = (Note 3) V IN = V OS, V CM = V or V CM = (Note 4) V IN = V OS, V CM = V or (Note 5).7V 6.V, V CM = V I SOURCE = 4µA I SOURCE = 4mA I SINK = 4µA I SINK = 4mA (Note 6) CONDITIONS T A = +5 C T A = T MIN to T MAX T A = +5 C T A = T MIN to T MAX MAX94_C, MAX94_EP_, MAX94_ES_, MAX94_MJ_ EUA/MAX94EUA MAX94_C, MAX94_EP_, MAX94_ES_, MAX94_MJ_ EUA/MAX94EUA MAX94_C, MAX94_EP_, MAX94_ES_, MAX94_MJ_ EUA/MAX94EUA MAX94_C, MAX94_EP_, MAX94_ES_, MAX94_MJ_ EUA/MAX94EUA MAX94_C MAX94_E/M MAX94_C, MAX94_EP_, MAX94_ES_, MAX94_MJ_ EUA/MAX94EUA MAX94_C, MAX94_EP_, MAX94_ES_, MAX94_MJ_ EUA/MAX94EUA MIN TYP MAX UNITS V V mv mv mv mv na na µv/v µv/v V V µa

3 ELECTRICAL CHARACTERISTICS (continued) ( =.7V to 6.V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C. See Note 14.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current per Comparator Power Dissipation per Comparator Propagation Delay I CC = 3V = 5V PD (Note 7) t PD+, t PD- (Note 8) MAX94/MAX944 MAX94/MAX only, shutdown mode ( = 3V) 1 6 MAX94/MAX944 MAX94_C MAX94_E/M Differential Propagation Delay dt PD (Note 9) 1 ns Propagation Delay Skew (Note 1) 1 ns Logic Input Voltage High V IH (Note 11) V V + V Logic Input Voltage Low V IL (Note 11) V + V V Logic Input Current I IL, I IH V LOGIC = V or (Note 11) 1 µa Data-to-Latch Setup Time t S (Note 1) ns Latch-to-Data Hold Time t H (Note 1) 3 ns Latch Pulse Width t LPW only 5 ns Latch Propagation Delay t LPD only 7 ns Shutdown Time (Note 13) 3 µs Shutdown Disable Time (Note 13) 1 µs µa mw ns Note 1: Inferred from the CMRR test. Note also that either or both inputs can be driven to the absolute maximum limit (.3V beyond either supply rail) without damage or false output inversion. Note : The input-referred trip points are the extremities of the differential input voltage required to make the comparator output change state. The difference between the upper and lower trip points is equal to the width of the input-referred hysteresis zone. See Figure 1. Note 3: V OS is defined as the center of the input-referred hysteresis zone. See Figure 1. Note 4: The polarity of I B reverses direction as V CM approaches either supply rail. See Typical Operating Characteristics for more detail. Note 5: Specified over the full common-mode range (V CMR ). Note 6: Applies to the only when in shutdown mode. Specification is for current flowing into or out of the output pin for V OUT driven to any voltage from to. Note 7: Typical power dissipation specified with = 3V; maximum with = 6V. Note 8: Parameter is guaranteed by design and specified with V OD = 5mV and C LOAD = 15pF in parallel with 4µA of sink or source current. V OS is added to the overdrive voltage for low values of overdrive. See Figure. Note 9: Specified between any two channels in the MAX94/MAX944. Note 1: Specified as the difference between t PD+ and t PD- for any one comparator. Note 11: Applies to the only for both S H D N and L A T C H pins. Note 1: Applies to the only. Comparator is active with L A T C H pin driven high and is latched with L A T C H pin driven low. See Figure. Note 13: Applicable to the only. Comparator is active with S H D N pin driven high and is in shutdown with S H D N pin driven low. Shutdown disable time is the delay when S H D N is driven high to the time the output is valid. Note 14: The EUA and MAX94EUA are 1% production tested at T A = +5 C. Specifications over temperature are guaranteed by design. 3

4 Typical Operating Characteristics ( = 3.V, T A = +5 C, unless otherwise noted.) PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) PROPAGATION DELAY vs. INPUT OVERDRIVE R S = 1Ω C LOAD = 15pF t PD INPUT OVERDRIVE (mv) t PD+ PROPAGATION DELAY vs. TEMPERATURE 7 R S = 1Ω C LOAD = 15pF V OD = 5mV TEMPERATURE ( C) -1-4 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) PROPAGATION DELAY vs. SOURCE IMPEDANCE C LOAD = 15pF V OD = 5mV k 1k 1k SOURCE IMPEDANCE (Ω) PROPAGATION DELAY vs. SUPPLY VOLTAGE t PD- SUPPLY VOLTAGE (V) t PD+ t PD- t PD+ R S = 1Ω 4 C LOAD = 15pF V OD = 5mV PROPAGATION DELAY (ns) VOH (V) R S = 1Ω V OD = 5mV PROPAGATION DELAY vs. CAPACITIVE LOAD t PD- t PD CAPACITIVE LOAD (pf) OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT T A = +5 C T A = -55 C T A = +15 C SOURCE CURRENT (µa) OUTPUT LOW VOLTAGE vs. SINK CURRENT TOTAL SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = +15 C MAX94 TOTAL SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = +15 C -9 VOL (V).3..1 T A = -55 C T A = +5 C SUPPLY CURRENT (µa) T A = +5 C T A = -55 C SUPPLY CURRENT (µa) T A = +5 C T A = -55 C 1 T A = +15 C SINK CURRENT (µa) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 4

5 Typical Operating Characteristics (continued) ( = 3.V, T A = +5 C, unless otherwise noted.) SUPPLY CURRENT (ma) TRIP POINTS / VOS (µv) MAX944 TOTAL SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = +15 C T A = +5 C T A = -55 C SUPPLY VOLTAGE (V) VOLTAGE TRIP POINTS / INPUT OFFSET VOLTAGE vs. TEMPERATURE V OS V TRIP- V TRIP+ V CM =.V TEMPERATURE ( C) INPUT VOLTAGE RANGE (V) INPUT BIAS / OFFSET CURRENT (na) INPUT VOLTAGE RANGE vs. TEMPERATURE V CM + V CM- = 3.V TEMPERATURE ( C) INPUT BIAS CURRENT / INPUT OFFSET CURRENT vs. TEMPERATURE I B + I B- I OS TEMPERATURE ( C) SHORT-CIRCUIT OUTPUT CURRENT (ma) IB+, IB- (na) SHORT-CIRCUIT OUTPUT CURRENT vs. TEMPERATURE OUTPUT SHORTED TO (SINKING) OUTPUT SHORTED TO (SOURCING) TEMPERATURE ( C) INPUT BIAS CURRENT (I B +, I B -) vs. V CM T A = -55 C T A = +5 C T A = +15 C V IN + = V IN - NEGATIVE VALUES REPRESENT CURRENT FLOWING INTO THE DEVICE = 6V COMMON-MODE VOLTAGE (V) SHUTDOWN SUPPLY CURRENT (µa) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE = 6.V =.7V TEMPERATURE ( C) -17 V OS 1MHz RESPONSE 5ns/div INPUT 5mV/div OUTPUT 1V/div 5

6 Typical Operating Characteristics (continued) ( = 3.V, T A = +5 C, unless otherwise noted.) V OD V OS ns/div PROPAGATION DELAY (t PD+ ) t PD+ INPUT STEP = 1mV V OD = +5mV NAME INPUT 5mV/div OUTPUT 1V/div V OS V OD ns/div PROPAGATION DELAY (t PD- ) t PD- FUNCTION 1 1 OUTA Comparator A output INA- Comparator A inverting input 3 3 INA+ Comparator A noninverting input Positive supply ( to must be 7V) 5 5 INB+ Comparator B noninverting input 6 6 INB- Comparator B inverting input 7 7 OUTB Comparator B output 8 OUTC Comparator C output 9 INC- Comparator C inverting input 1 INC+ Comparator C noninverting input Ground 1 IND+ Comparator D noninverting input 13 IND- Comparator D inverting input 14 OUTD Comparator D output IN+ Noninverting input 3 IN- Inverting input INPUT STEP = 1mV V OD = -5mV INPUT 5mV/div Pin Description PIN MAX94 MAX944 4 S H D N Shutdown: is active when S H D N is driven high; is in shutdown when S H D N is driven low. OUTPUT 1V/div 5 L A T C H The output is latched when L A T C H is low. The latch is transparent when L A T C H is high. 7 OUT Comparator output 8 N.C. No connect not internally connected 6

7 V TRIP+ V HYST V TRIP- COMPARATOR OUTPUT V IN+ V TRIP+ + V V TRIP- OS = V IN- = V Detailed Description The single-supply comparators feature internal hysteresis, high speed, and low power. Their outputs are guaranteed to pull within.4v of either supply rail without external pull-up or pulldown circuitry. Rail-to-rail input voltage range and lowvoltage single-supply operation make these devices ideal for portable equipment. The /MAX94/ MAX944 interface directly to CMOS and TTL logic. Timing Most high-speed comparators oscillate in the linear region because of noise or undesired parasitic feedback. This tends to occur when the voltage on one input is at or equal to the voltage on the other input. To counter the parasitic effects and noise, the / MAX94/MAX944 have internal hysteresis. The hysteresis in a comparator creates two trip points: one for the rising input voltage and one for the falling input voltage (Figure 1). The difference between the trip points is the hysteresis. When the comparator s input voltages are equal, the hysteresis effectively causes one comparator input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. Standard comparators require hysteresis to be added with external resistors. The s fixed internal hysteresis V OH Figure 1. Input and Output Waveform, Noninverting Input Varied V OL eliminates these resistors and the equations needed to determine appropriate values. Figure 1 illustrates the case where IN- is fixed and IN+ is varied. If the inputs were reversed, the figure would look the same, except the output would be inverted. The includes an internal latch that allows storage of comparison results. The L A T C H pin has a high input impedance. If L A T C H is high, the latch is transparent (i.e., the comparator operates as though the latch is not present). The comparator's output state is stored when L A T C H is pulled low. All timing constraints must be met when using the latch function (Figure ). Shutdown Mode ( Only) The shuts down when S H D N is low. When shut down, the supply current drops to less than 6µA, and the three-state output becomes high impedance. The S H D N pin has a high input impedance. Connect S H D N to for normal operation. Exit shutdown with L A T C H high; otherwise, the output will be indeterminate. Input Stage Circuitry The include internal protection circuitry that prevents damage to the precision input stage from large differential input voltages. This protection circuitry consists of four back-to-back diodes between IN+ and IN- as well as two.5kω resistors (Figure 3). The diodes limit the differential voltage applied to the internal circuitry of the comparators to be no more than 4V F, where V F is the forward voltage drop of the diode (about.7v at +5 C). For a large differential input voltage (exceeding 4V F ), this protection circuitry increases the input bias current at IN+ (source) and IN- (sink). Input Current = (IN+ - IN-) - 4V F x.5kω Input current with large differential input voltages should not be confused with input bias current (IB). As long as the differential input voltage is less than 4V F, this input current is equal to IB. The protection circuitry also allows for the input common-mode range of the to extend beyond both power-supply rails. The output is in the correct logic state if one or both inputs are within the common-mode range. 7

8 DIFFERENTIAL INPUT VOLTAGE LATCH OUT V V V OH V OL V OS Figure. Timing Diagram with Latch Operator Output Stage Circuitry The contain a current-driven output stage as shown in Figure 4. During an output transition, ISOURCE or ISINK is pushed or pulled to the output pin. The output source or sink current is high during the transition, creating a rapid slew rate. Once the output voltage reaches V OH or VOL, the source or sink current decreases to a small value, capable of maintaining the VOH or VOL static condition. This significant decrease in current conserves power after an output transition has occurred. One consequence of a current-driven output stage is a linear dependence between the slew rate and the load capacitance. A heavy capacitive load will slow down a voltage output transition. This can be useful in noisesensitive applications where fast edges may cause interference. t S t H t PD t LPW t LPD Applications Information Circuit Layout and Bypassing The high gain bandwidth of the /MAX94/ MAX944 requires design precautions to realize the comparators full high-speed capability. The recommended precautions are: 1) Use a printed circuit board with a good, unbroken, low-inductance ground plane. ) Place a decoupling capacitor (a.1µf ceramic capacitor is a good choice) as close to as possible. 3) Pay close attention to the decoupling capacitor s bandwidth, keeping leads short. 4) On the inputs and outputs, keep lead lengths short to avoid unwanted parasitic feedback around the comparators. 5) Solder the device directly to the printed circuit board instead of using a socket. 8

9 .5k IN+ IN.5k Figure 3. Input Stage Circuitry TO INTERNAL CIRCUITRY TO INTERNAL CIRCUITRY MAX94 MAX944 V CC I SOURCE I SINK V Figure 4. Output Stage Circuitry MAX94 MAX944 OUTPUT V DD = 3.3V = 3V SERIAL DIGITAL INPUT SDI VREFC 8-BIT DAC V DD 1k MAX51 DACOUTC V SS COAX LINE k k 3V V CLEAN DIGITAL SIGNAL ANALOG IN Figure V Digitally Controlled Threshold Detector Figure 6. Line Transceiver Application 9

10 _Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX94CPA C to +7 C 8 Plastic DIP MAX94CSA C to +7 C 8 SO MAX94C/D C to +7 C Dice* MAX94EPA -4 C to +85 C 8 Plastic DIP MAX94ESA -4 C to +85 C 8 SO MAX94EUA -4 C to +85 C 8 µmax MAX94MJA -55 C to +15 C 8 CERDIP MAX944CPD C to +7 C 14 Plastic DIP MAX944CSD C to +7 C 14 SO MAX944EPD -4 C to +85 C 14 Plastic DIP MAX944ESD -4 C to +85 C 14 SO MAX944MJD -55 C to +15 C 14 CERDIP * Dice are specified at T A = +5 C, DC parameters only. Chip Topographies IN+ IN- SHDN.58" (1.47mm) OUT.56" (1.4mm) LATCH MAX94 INB- INB+ OUTB.6" (1.57mm) OUTA INA- INA+.64" (1.63mm) TRANSISTOR COUNT: 134(), 19(MAX94) SUBSTRATE CONNECTED TO 1

11 Package Information 8LUMAXD.EPS 11

12 Package Information (continued) PDIPN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 1 Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.