PART* MAX5354EUA MAX5354EPA TOP VIEW OUT. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

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1 ; Rev 1; 2/97 1-Bit Voltage-Output DACs General Description The combine a low-power, voltageoutput, 1-bit digital-to-analog converter (DAC) and a precision output amplifier in an 8-pin µmax or DIP package. The operates from a single +5V supply, and the operates from a single +3.3V supply. Both devices draw less than 28µA of supply current. The output amplifier s inverting input is available to the user, allowing specific gain configuratio, remote seing, and high output current capability. This makes the ideal for a wide range of applicatio, including industrial process control. Other features include a software shutdown and power-on reset. The serial interface is compatible with SPI /QSPI and Microwire. The DAC has a double-buffered input, organized as an input register followed by a DAC register. A 16-bit serial word loads data into the input register. The DAC register can be updated independently or simultaneously with the input register. All logic inputs are TTL/CMOS-logic compatible and buffered with Schmitt triggers to allow direct interfacing to optocouplers. Applicatio Digital Offset and Gain Adjustment Industrial Process Controls Microprocessor-Controlled Systems Portable Test Itruments Remote Industrial Controls Functional Diagram Features 1-Bit DAC with Configurable Output Amplifier +5V Single-Supply Operation () +3.3V Single-Supply Operation () Low Supply Current:.28mA Normal Operation 2µA Shutdown Mode Available Power-On Reset Clears DAC Output to Zero SPI/QSPI and Microwire Compatible Schmitt-Trigger Digital Inputs for Direct Optocoupler Interface +3.3V Directly Interfaces with +5V Logic Ordering Information PART* CPA CUA EPA EUA TEMP. RANGE C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C PIN-PACKAGE 8 Plastic DIP 8 µmax 8 Plastic DIP 8 µmax MJA -55 C to +125 C 8 CERDIP** Ordering Information continued at end of data sheet. *Contact factory for availability of 8-pin SO package. **Contact factory for availability and processing to MIL-STD-883. Pin Configuration FB TOP VIEW CONTROL DAC REGISTER INPUT REGISTER DAC BIT SHIFT REGISTER 4 DIP/µMAX 5 FB SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. Maxim Integrated Products 1 For free samples & the latest literature: or phone

2 1-Bit Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS to...-.3v to +6V,, FB to...-.3v to ( +.3V) Digital Inputs to...-.3v to +6V Continuous Current into Any Pin...±2mA Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate 9.9mW/ C above +7 C)...727mW µmax (derate 4.1mW/ C above +7 C)...33mW CERDIP (derate 8.mW/ C above +7 C)...64mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI: Operating Temperature Ranges C_A/C_A... C to +7 C E_A/E_A...-4 C to +85 C MJA/MJA C to +125 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1sec)...+3 C ( = +5V ±1%, = V, = 2.5V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C. Output buffer connected in unity-gain configuration (Figure 8).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE ANALOG SECTION Resolution N 1 Bits Integral Nonlinearity C/E ±1 INL (Note 1) M ±2 LSB Differential Nonlinearity DNL Guaranteed monotonic ±1. LSB Offset Error V OS ±.3 ±8 mv Offset-Error Tempco TCV OS 6 ppm/ C Gain Error (Note 1) GE -.3 ±2 LSB Gain-Error Tempco 1 ppm/ C Power-Supply Rejection Ratio PSRR 4.5V 5.5V 8 µv/v ERENCE INPUT Reference Input Range V V Reference Input Resistance R Code dependent, minimum at code 155 hex 18 3 kω MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth V =.67Vp-p 65 khz Reference Feedthrough Input code = all s, V = 3.6Vp-p at 1kHz -84 db Signal-to-Noise Plus Distortion Ratio SINAD V = 1Vp-p at 25kHz, code = full scale 77 db DIGITAL INPUTS Input High Voltage V IH 2.4 V Input Low Voltage V IL.8 V Input Leakage Current I IN V IN = V or.1 ±.5 µa Input Capacitance C IN 8 pf 2

3 1-Bit Voltage-Output DACs ELECTRICAL CHARACTERISTI: (continued) ( = +5V ±1%, = V, = 2.5V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C. Output buffer connected in unity-gain configuration (Figure 8).) Current into FB Start-Up Time Supply Voltage Supply Current PARAMETER DIGITAL DYNAMIC INPUTS PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing Digital Feedthrough POWER SUPPLIES Supply Current in Shutdown Reference Current in Shutdown SYMBOL SR I DD TIMING CHARACTERISTI (Figure 6) Clock Period Pulse Width High Pulse Width Low Fall to Rise Setup Time Rise to Rise Hold Time Setup Time Hold Time Rise to Fall Delay Rise to Rise Hold Time Pulse Width High t CP t CH t CL t S t H t DS t DH t t 1 t W To ±1/2LSB, V STEP = 2.5V Rail-to-rail (Note 2) =, = 1kHz (Note 3) CONDITIONS MIN TYP MAX.6 1 to.1 ± UNITS (Note 3) 4 2 µa ±.5 V/µs µs V µa µs nv-s V ma µa Note 1: Guaranteed from code 3 to code 123 in unity-gain configuration. Note 2: Accuracy is better than 1LSB for V = 8mV to - 1mV, guaranteed by a power-supply rejection test at the end points. Note 3: R L =, digital inputs at or. 3

4 1-Bit Voltage-Output DACs ELECTRICAL CHARACTERISTI: ( = +3.15V to +3.6V, = 1.25V, = V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C. Output buffer connected in unity-gain configuration (Figure 8).) Resolution Integral Nonlinearity (Note 4) Differential Nonlinearity Offset Error PARAMETER Offset-Error Tempco Gain-Error Tempco SYMBOL STATIC PERFORMANCE ANALOG SECTION N INL DNL TCV OS C/E M CONDITIONS Guaranteed monotonic Gain Error (Note 4) GE -.3 ±2 Power-Supply Rejection Ratio PSRR 8 ERENCE INPUT Reference Input Range V Reference Input Resistance R Code dependent, minimum at code 155 hex MULTIPLYING-MODE PERFORMANCE ( = +3.3V) Reference -3dB Bandwidth V =.67Vp-p Reference Feedthrough Input code = all s, V = 1.9Vp-p at 1kHz Signal-to-Noise Plus Distortion Ratio SINAD V = 1Vp-p at 25kHz, code = full scale DIGITAL INPUTS Input High Voltage V IH Input Low Voltage V IL Input Leakage Current I IN V IN = V or Input Capacitance C IN DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing Current into FB Start-Up Time Digital Feedthrough POWER SUPPLIES Supply Voltage Supply Current Supply Current in Shutdown Reference Current in Shutdown V OS SR I DD To ±1/2LSB, V STEP = 1.25V Rail-to-rail (Note 5) =, = 1kHz (Note 6) (Note 6) MIN TYP MAX ± ±1 ±2 ±.3 ±8.6.1 ± to.1 ± ±.5 UNITS Bits LSB LSB mv ppm/ C LSB ppm/ C µv/v V kω khz db db V V µa pf V/µs µs V µa µs nv-s V ma µa µa 4

5 1-Bit Voltage-Output DACs ELECTRICAL CHARACTERISTI: (continued) ( = +3.15V to +3.6V, = 1.25V, = V, R L = 5kΩ, C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C. Output buffer connected in unity-gain configuration (Figure 8).) Clock Period Pulse Width High Fall to Rise Setup Time Setup Time PARAMETER Pulse Width Low Rise to Rise Hold Time SYMBOL TIMING CHARACTERISTI (Figure 6) Hold Time Rise to Fall Delay Rise to Rise Hold Time Pulse Width High t CP t CH t CL t S t H t DS t DH t t 1 t W CONDITIONS MIN TYP MAX UNITS Note 4: Guaranteed from code 6 to code 123 in unity-gain configuration. Note 5: Accuracy is better than 1LSB for V = 8mV to - 15mV, guaranteed by a power-supply rejection test at the end points. Note 6: R L =, digital inputs at or. 5

6 1-Bit Voltage-Output DACs Typical Operating Characteristics ( only, = +5V, R L = 5kΩ, C L = 1pF, T A = +25 C, unless otherwise noted.) INL (LSB) INTEGRAL NONLINEARITY vs. ERENCE VOLTAGE ERENCE VOLTAGE (V) RELATIVE PUT (db) ERENCE VOLTAGE INPUT FREQUENCY RESPONSE 5k 1M 1.5M 2M 2.5M 3M FREQUENCY (Hz) -2 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. TEMPERATURE 4 38 R L = TEMPERATURE ( C) -3 POWER-DOWN SUPPLY CURRENT (µa) POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE -4 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. SUPPLY VOLTAGE -5 THD + NOISE (db) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY V = 2.5V DC + 1 Vp-p SINE CODE = FULL SCALE TEMPERATURE ( C) SUPPLY VOLTAGE (V) FREQUENCY (khz) -2 PUT FFT PLOT V = +3.6Vp-p CODE = FULL SCALE f IN = 1kHz PUT VOLTAGE vs. LOAD -8-2 ERENCE FEEDTHROUGH AT 1kHz ERENCE INPUT SIGNAL -9a/9b SIGNAL AMPLITUDE (db) PUT VOLTAGE (V) SIGNAL AMPLITUDE (db) PUT FEEDTHROUGH FREQUENCY (khz) k 1k 1k 1k 1M LOAD (Ω) FREQUENCY (khz) 6

7 1-Bit Voltage-Output DACs Typical Operating Characteristics (continued) ( only, = +5V, R L = 5kΩ, C L = 1pF, T A = +25 C, unless otherwise noted.) 5V/div, AC COUPLED 1mV/div MAJOR-CARRY TRANSITION 1µs/div (continued) -1a, 2V/div, AC COUPLED 1mV/div CODE = 512 DIGITAL FEEDTHROUGH (f = 1kHz) = 5V 2µs/div -11a DYNAMIC RESPONSE 1V/div -12a 1µs/div GAIN = +2, SWITCHING FROM CODE TO 15 7

8 1-Bit Voltage-Output DACs Typical Operating Characteristics (continued) ( only, = +3.3V, R L = 5kΩ, C L = 1pF, T A = +25 C, unless otherwise noted.) INL (LSB) POWER-DOWN SUPPLY CURRENT (µa) INTEGRAL NONLINEARITY vs. ERENCE VOLTAGE ERENCE VOLTAGE (V) POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) RELATIVE PUT (db) SUPPLY CURRENT (µa) ERENCE VOLTAGE INPUT FREQUENCY RESPONSE -2 1k 5k 1M 1.5M 2M 2.5M FREQUENCY (Hz) SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) SUPPLY CURRENT (µa) THD + NOISE (db) R L = SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY V = 1V DC +.5Vp-p SINE CODE = FULL SCALE FREQUENCY (khz) SIGNAL AMPLITUDE (db) PUT FFT PLOT V = 1.9Vp-p CODE = FULL SCALE f IN = 1kHz -16 FULL-SCALE PUT (V) FULL-SCALE PUT vs. LOAD -17 SIGNAL AMPLITUDE (db) ERENCE FEEDTHROUGH AT 1kHz ERENCE INPUT SIGNAL PUT FEEDTHROUGH FREQUENCY (khz) k 1k 1k 1M 1M LOAD (Ω) FREQUENCY (khz) 8

9 1-Bit Voltage-Output DACs Pin Description PIN NAME FB Serial-Data Input DAC Output Amplifier Feedback Reference Voltage Input Ground FUNCTION DAC Output Voltage Chip-Select Input. Active low. Serial-Clock Input Positive Power Supply Detailed Description The contain a voltage-output digital-to-analog converter (DAC) that is easily addressed using a simple 3-wire serial interface. Each IC includes a 16-bit shift register, and has a double-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition to the voltage output, the amplifier s negative input is available to the user. The DAC is an inverted R-2R ladder network that converts a digital input (1 data bits plus three sub-bits) into an equivalent analog output voltage in proportion to the applied reference voltage. Figure 1 shows a simplified circuit diagram of the DAC. Reference Inputs The reference input accepts positive DC and AC signals. The voltage at the reference input sets the fullscale output voltage for the DAC. The reference input voltage range is V to (VDD - 1.4V). The output voltage (V) is represented by a digitally programmable voltage source, as expressed in the following equation: V = (V x NB / 124) x Gain where NB is the numeric value of the DAC s binary input code ( to 123), V is the reference voltage, and Gain is the externally set voltage gain. The impedance at the reference input is code dependent, ranging from a low value of 18kΩ when the DAC has an input code of 155 hex, to a high value exceeding several giga ohms (leakage currents) with an input code of hex. Because the input impedance at the reference pin is code dependent, load regulation of the reference source is important. A 2R 2R 2R 2R 2R SHOWN FOR ALL 1s ON DAC R R R Figure 1. Simplified DAC Circuit Diagram In shutdown mode, the s input enters a high-impedance state with a typical input leakage current of.1µa. The reference input capacitance is also code dependent and typically ranges from 15pF (with an input code of all s) to 5pF (at full scale). The MAX V reference is recommended for use with the. Output Amplifier The s DAC output is internally buffered by a precision amplifier with a typical slew rate of.6v/µs. Access to the output amplifier s inverting input provides the user greater flexibility in output gain setting/signal conditioning (see the Applicatio Information section). With a full-scale traition at the output, the typical settling time to ±1/2LSB is 1µs when loaded with 5kΩ in parallel with 1pF (loads less than 2kΩ degrade performance). The amplifier s output dynamic respoes and settling performances are shown in the Typical Operating Characteristics. MSB Shutdown Mode The feature a software-programmable shutdown that reduces supply current to a typical value of 4µA. Writing 111X XXXX XXXX XXXX as the inputcontrol word puts the device in shutdown mode (Table 1). FB 9

10 1-Bit Voltage-Output DACs In shutdown mode, the amplifier s output and the reference input enter a high-impedance state. The serial interface remai active. Data in the input register is retained in shutdown, allowing the to recall the output state prior to entering shutdown. Exit shutdown mode by either recalling the previous configuration or updating the DAC with new data. When powering up the device or bringing it out of shutdown, allow 2µs for the outputs to stabilize. Serial-Interface Configuratio The s 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI /QSPI (Figure 3). The serial input word coists of three control bits followed by 1+3 data bits (MSB first), as shown in Figure 4. The 3-bit control code determines the s respoe outlined in Table 1. The s digital inputs are double buffered. Depending on the command issued through the serial interface, the input register can be loaded without affecting the DAC register, the DAC register can be loaded directly, or the DAC register can be updated from the input register (Table 1). The +3.3V can also directly interface with +5V logic. Serial-Interface Description The require 16 bits of serial data. Table 1 lists the serial-interface programming commands. For certain commands, the 1+3 data bits are don t cares. Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word ( must remain low until 16 bits are traferred). The serial data is composed of three control bits (C2, C1, C), followed by the 1+3 data bits D9...D, S2, S1, S (Figure 4). Set the sub-bits (S2, S1, S) to zero. The 3-bit control code determines: the register to be updated, the configuration when exiting shutdown. Figure 5 shows the serial-interface timing requirements. The chip-select pin () must be low to enable the DAC s serial interface. When is high, the interface control circuitry is disabled. must go low at least ts before the rising serial clock () edge to properly clock in the first bit. When is low, data is clocked into the internal shift register via the serial-data input pin () on s rising edge. The maximum guaranteed clock frequency is 1MHz. Data is latched into the input/dac register on s rising edge. Figure 2. Connectio for Microwire Figure 3. Connectio for SPI/QSPI SK SO I/O MOSI SCK I/O MICROWIRE PORT +5V SS SPI/QSPI PORT CPOL =, CPHA = MSB...LSB Control Bits C2 C1 C 3 Control Bits Figure 4. Serial-Data Format 16 Bits of Serial Data Data Bits MSB...LSB Sub-Bits D9...D, S2, S1, S 1+3 Data Bits 1

11 1-Bit Voltage-Output DACs Table 1. Serial-Interface Programming Commands 16-BIT 16-BIT SERIAL SERIAL WORD WORD C2 C1 C X X 1 X X = Don t care D9...D MSB LSB 1 bits of data 1 bits of data XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX S2...S XXX XXX XXX Shutdown No operation (NOP) FUNCTION Load input register; DAC register immediately updated (also exit shutdown). Load input register; DAC register unchanged. Update DAC register from input register (also exit shutdown; recall previous state) COMMAND EXECUTED C2 C1 C D9 D8 D7 D6 D5 D4 D3 D2 D1 D S2 S1 S Figure 5. Serial-Interface Timing Diagram t W t O t S t CL t CH t CP t H t 1 t DS tdh Figure 6. Detailed Serial-Interface Timing Diagram 11

12 1-Bit Voltage-Output DACs TO OTHER SERIAL DEVICES Figure 7. Multiple s Sharing Common and Lines Figure 7 shows a method of connecting several s. In this configuration, the clock and the data bus are common to all devices, and separate chip-select lines are used for each IC. Applicatio Information Unipolar Output For a unipolar output, the output voltage and the reference input have the same polarity. Figure 8 shows the unipolar output circuit, which is also the typical operating circuit. Table 2 lists the unipolar output codes. Figure 9 illustrates a rail-to-rail output configuration. This circuit shows the with the output amplifier configured for a closed-loop gain of +2, to provide a V to 5V full-scale range when a 2.5V reference is used. When the is used with a 1.25V reference, this circuit provides a V to 2.5V full-scale range. Bipolar Output The output can be configured for bipolar operation using Figure 1 s circuit, according to the following equation: V = V [(2NB / 124) - 1] where NB is the numeric value of the DAC s binary input code. Table 3 shows digital codes (offset binary) and corresponding output voltage for Figure 1 s circuit. Table 2. Unipolar Code Table DAC CONTENTS MSB LSB () 1 1 () 1 () () 1 () ANALOG PUT 123 +V V V +V = V V 124 () V NOTE: ( ) are for sub-bits. Using an AC Reference In applicatio where the reference has AC-signal components, the have multiplying capability within the reference input range specificatio. Figure 11 shows a technique for applying a sinewave signal to the reference input where the AC signal is offset before being applied to. The reference voltage must never be more negative than. 12

13 1-Bit Voltage-Output DACs Table 3. Bipolar Code Table DAC CONTENTS MSB LSB () 1 1 () NOTE: ( ) are for sub-bits. ANALOG PUT 1 () V () 1 () () 511 +V V V V V = - V 512 The s total harmonic distortion plus noise (THD+N) is typically less than -77dB (full-scale code), and the s THD+N is typically less than -72dB (full-scale code), given a 1Vp-p signal swing and input frequencies up to 25kHz. The typical -3dB frequency is 65kHz for both devices, as shown in the Typical Operating Characteristics graphs. Digitally Programmable Current Source The circuit of Figure 12 places an NPN traistor (2N394 or similar) within the op-amp feedback loop to implement a digitally programmable, unidirectional current source. The output current is calculated with the following equation: I = (V/R) x (NB/124) where NB is the numeric value of the DAC s binary input code and R is the see resistor shown in Figure V/3.3V +5V/+3.3V FB FB 1k DAC DAC 1k Figure 8. Unipolar Output Circuit Figure 9. Unipolar Rail-to-Rail Output Circuit 13

14 1-Bit Voltage-Output DACs DAC R1 +5V/+3.3V R2 V+ FB V- R1 = R2 = 1kΩ ±.1% V +5V/ +3.3V AC ERENCE INPUT 5mVp-p 26k 1k +5V/+3.3V DAC MAX495 Figure 1. Bipolar Output Circuit Figure 11. AC Reference Input Circuit +5V/+3.3V DAC V L I 2N394 Grounding and Layout Coideratio Digital or AC traient signals on can create noise at the analog output. Tie to the highest-quality ground available. Good printed circuit board ground layout minimizes crosstalk between the DAC output, reference input, and digital input. Reduce crosstalk by keeping analog lines away from digital lines. Wire-wrapped boards are not recommended. FB R Figure 12. Digitally Programmable Current Source Power-Supply Coideratio On power-up, the input and DAC registers are cleared (set to zero code). For rated performance, must be at least 1.4V below VDD. Bypass VDD with a 4.7µF capacitor in parallel with a.1µf capacitor to. Use short lead lengths and place the bypass capacitors as close to the supply pi as possible. 14

15 1-Bit Voltage-Output DACs _Ordering Information (continued) PART* CPA CUA EPA EUA TEMP. RANGE C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C PIN-PACKAGE 8 Plastic DIP 8 µmax 8 Plastic DIP 8 µmax MJA -55 C to +125 C 8 CERDIP** *Contact factory for availability of 8-pin SO package. **Contact factory for availability and processing to MIL-STD-883. Chip Information TRANSISTOR COUNT: 1677 Package Information PDIPN.EPS CDIPS.EPS 15

16 1-Bit Voltage-Output DACs Package Information (continued) 8LUMAXD.EPS Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 16 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 (48) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.