PART MAX534BCPE. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

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1 9-5; Rev ; 8/96 +5V, Low-Power, 8-Bit Quad AC General escription The serial-input, voltage-output, 8-bit quad digital-to-analog converter (AC) operates from a single +4.5V to +5.5V supply. Internal precision buffers swing rail to rail, and the reference input range includes both ground and the positive rail. The features a 2.5µA shutdown mode. The serial interface is double buffered: a 2-bit input shift register is followed by four 8-bit buffer registers and four 8-bit AC registers. The 2-bit serial word coists of eight data bits and four control bits (for AC selection and special programming commands). Both the input and AC registers can be updated independently or simultaneously with a single software command. Two additional asynchronous control pi, LAC and CLR, provide simultaneous updating or clearing of the input and AC registers. The interface is compatible with SPI, QSPI (CPOL = CPHA = or CPOL = CPHA = ), and Microwire. A buffered data output allows daisy chaining of serial devices. In addition to 6-pin IP and CERIP packages, the is available in a 6-pin QSOP that occupies the same area as an 8-pin SO. For operation guaranteed to 2.7V, see the 533 data sheet. Applicatio igital Gain and Offset Adjustments Programmable Attenuators Programmable Current Sources Portable Itruments Pin Configuration TOP VIEW OUTB OUTA 2 REF 3 UPO 4 PE 5 LAC 6 CLR 7 6 OUTC 5 OUT 4 AGN 3 V 2 GN IN Features +4.5V to +5.5V Single-Supply Operation Ultra-Low Supply Current:.8mA while Operating 2.5µA in Shutdown Mode Ultra-Small 6-Pin QSOP Package Ground to V Reference Input Range Output Buffer Amplifiers Swing Rail to Rail MHz Serial Interface Compatible with SPI, QSPI (CPOL = CPHA = or CPOL = CPHA = ), and Microwire ouble-buffered Registers for Synchronous Updating Serial ata Output for aisy Chaining Power-On Reset Clears Serial Interface and Sets All Registers to Zero Software Shutdown Software-Programmable Logic Output (µc I/O Extender) Asynchronous Hardware Clear Resets All Internal Registers to Zero Ordering Information PART ACPE BCPE ACEE TEMP. RANGE C to +7 C C to +7 C C to +7 C PIN-PACKAGE 6 Plastic IP 6 Plastic IP 6 QSOP BCEE C to +7 C 6 QSOP BC/ C to +7 C ice* AEPE -4 C to +85 C 6 Plastic IP BEPE -4 C to +85 C 6 Plastic IP AEEE -4 C to +85 C 6 QSOP BEEE -4 C to +85 C 6 QSOP AMJE -55 C to +25 C 6 CERIP** BMJE -55 C to +25 C 6 CERIP** INL (LSB) ± ±2 ± ±2 ±2 ± ±2 ± ±2 ± ±2 *ice are tested at T A = +25 C. **Contact factory for availability and processing to MIL-ST-883. OUT 8 9 Functional iagram appears at end of data sheet. IP/QSOP SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. Maxim Integrated Products For free samples & the latest literature: or phone

2 +5V, Low-Power, 8-Bit Quad AC ABSOLUTE IMUM RATINGS V to GN...-.3V, +6V V to AGN...-.3V, +6V igital Input Voltage to GN...-.3V, +6V igital Output Voltage to GN...-.3V, (V +.3V) AGN to GN...±.3V REF...-.3V, (V +.3V) OUT_...-.3V, V Maximum Current into Any Pin...5mA Continuous Power issipation (T A = +7 C) Plastic IP (derate.53mw/ C above +7 C)...842mW QSOP (derate 8.3mW/ C above +7 C)...667mW CERIP (derate.mw/ C above +7 C)...8mW Operating Temperature Ranges _ C_ E... C to +7 C _ E_ E...-4 C to +85 C _ MJE C to +25 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI (V = +4.5V to +5.5V, V REF = 4.96V, AGN = GN = V, R L = kω, C L = pf, T A = T to T, unless otherwise noted. Typical values are at V = +5V and T A = +25 C.) PARAMETER SYMBOL CONITIONS TYP UNITS STATIC ACCURACY Resolution Integral Nonlinearity (Note ) ifferential Nonlinearity (Note ) Zero-Code Error Zero-Code-Error Supply Rejection INL NL ZCE A B Guaranteed monotonic (all codes) Code = hex Code = hex, V = 4.5V to 5.5V 8 ± ±2 ±. ±2 Bits LSB LSB mv LSB Zero-Code Temperature Coefficient Code = hex ± µv/ C Full-Scale Error Code = FF hex ±3 mv Full-Scale Error Supply Rejection Code = FF hex, V = 4.5V to 5.5V LSB Full-Scale Temperature Coefficient Code = FF hex ± µv/ C REFERENCE INPUTS Input Voltage Range V V Input Resistance kω Input Capacitance pf Channel-to-Channel Isolation (Note 2) -6 db AC Feedthrough (Note 3) -6 db AC OUTPUTS Output Voltage Range R L = open V REF V Load Regulation Code = FF hex, measured with I L = ma to.6ma.56 LSB/mA 2

3 +5V, Low-Power, 8-Bit Quad AC ELECTRICAL CHARACTERISTI (continued) (V = +4.5V to +5.5V, V REF = 4.96V, AGN = GN = V, R L = kω, C L = pf, T A = T to T, unless otherwise noted. Typical values are at V = +5V and T A = +25 C.) PARAMETER SYMBOL CONITIONS TYP UNITS IGITAL INPUTS Input High Voltage V IH.7V V Input Low Voltage V IL.3V V Input Current I IN V IN = V or V ±. µa Input Capacitance C IN (Note 4) pf IGITAL OUTPUTS Output High Voltage V OH I SOURCE =.2mA V -.5 V Output Low Voltage V OL I SINK =.6mA.4 V YNAMIC PERFORMANCE Voltage-Output Slew Rate COE = FF hex.6 V/µs Output Settling Time To /2LSB, from code to code FF hex (Note 5) 8 µs igital Feedthrough and Crosstalk VREF = V, code to code FF hex (Note 6) 5 nv-s igital-to-analog Glitch Impulse Code 8 hex to code 7F hex 5 nv-s Signal-to-Noise Plus istortion Ratio SINA V REF = 4Vp-p at khz, code = FF hex 8 V REF = 4Vp-p at khz 7 db Multiplying Bandwidth V REF =.5Vp-p, 3dB bandwidth 38 khz Wideband Amplifier Noise 6 µv RMS POWER SUPPLIES Power-Supply Voltage V V Supply Current I C/E M ma Shutdown Current 2.5 µa TIG CHARACTERISTI (V = +4.5V to +5.5V, V REF = 4.96V, AGN = GN = V, C OUT = pf, T A = T to T, unless otherwise noted. Typical values are at V = +5V and T A = +25 C.) PARAMETER SYMBOL CONITIONS TYP V Rise to Fall Setup Time (Note 4) LAC Pulse Width Low Rise to LAC Fall Setup Time (Note 7) CLR Pulse Width Low Pulse Width High t V t LAC t CLL t CLW t W C/E M C/E M C/E M C/E M C/E M UNITS µs 3

4 +5V, Low-Power, 8-Bit Quad AC TIG CHARACTERISTI (continued) (V = +4.5V to +5.5V, V REF = 4.96V, AGN = GN = V, C OUT = pf, T A = T to T, unless otherwise noted. Typical values are at V = +5V and T A = +25 C.) PARAMETER SYMBOL CONITIONS TYP UNITS SERIAL-INTERFACE TIG Clock Frequency (Note 8) f CLK C/E M 8.3 MHz Pulse Width High t CH C/E 4 M 5 Pulse Width Low t CL C/E 4 M 5 Fall to Rise Setup C/E 4 t S Time M 5 Rise to Rise Hold Time t H IN to Rise to Setup Time t S C/E 4 M 5 IN to Rise to Hold Time t H Rise to OUT Valid C/E 2 t Propagation elay (Note 9) O M 23 Fall to OUT Valid C/E 2 t Propagation elay (Note ) O2 M 25 Rise to Fall elay t C/E 4 M 5 Rise to Rise Setup C/E 4 t Time M 5 Note : INL and NL are measured with R L referenced to ground. Nonlinearity is measured from the first code that is greater than or equal to the maximum offset specification to code FF hex (full scale). See AC Linearity and Voltage Offset section. Note 2: V REF = 4Vp-p, khz. Channel-to-channel isolation is measured by setting one AC s code to FF hex and setting all other AC s codes to hex. Note 3: V REF = 4Vp-p, khz. AC code = hex. Note 4: Guaranteed by design, not production tested. Note 5: Output settling time is measured from the 5% point of the rising edge of to /2LSB of V OUT s final value. Note 6: igital crosstalk is defined as the glitch energy at any AC output in respoe to a full-scale step change on any other AC. Note 7: If LAC is activated prior to s rising edge, it must stay low for t LAC or longer after goes high. Note 8: When OUT is not used. If OUT is used, f CLK max is 4MHz, due to the to OUT propagation delay. Note 9: Serial data clocked out at s rising edge (measured from 5% of the clock edge to 2% or 8% of V ). Note : Serial data clocked out at s falling edge (measured from 5% of the clock edge to 2% or 8% of V ). 4

5 +5V, Low-Power, 8-Bit Quad AC Typical Operating Characteristics (V = +5V, T A = +25 C, unless otherwise noted.) AC ZERO-COE OUTPUT VOLTAGE (V) AC ZERO-COE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT V REF = 5V AC COE = HEX LOA TO V AC OUTPUT SINK CURRENT (ma) -TOC AC FULL-SCALE OUTPUT VOLTAGE (V) AC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT V REF = 5V AC COE = FF HEX LOA TO GN AC OUTPUT SOURCE COE (ma) -TOC2 SUPPLY CURRENT (µa) V REF = 4.5V SUPPLY CURRENT vs. TEMPERATURE AC COE = FF HEX AC COE = HEX TEMPERATURE ( C) -TOC3 SHUTOWN SUPPLY CURRENT (µa) SHUTOWN SUPPLY CURRENT vs. TEMPERATURE -TOC4 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. REFERENCE VOLTAGE ALL AC COES = FF HEX ALL AC COES = HEX -TOC TEMPERATURE ( C) REFERENCE VOLTAGE (V) 5

6 +5V, Low-Power, 8-Bit Quad AC Pin escription PIN NAME OUTB OUTA REF UPO PE LAC CLR OUT IN GN V AGN OUT OUTC AC B Voltage Output AC A Voltage Output Reference-Voltage Input FUNCTION Software-Programmable Logic Output Power-own Enable. Must be high to allow software shutdown mode. Load AC Input (active low). riving this asynchronous input low (level seitive) trafers the contents of each input latch to its respective AC latch. Clear AC Input (active low). riving CLR low asynchronously clears the input and AC registers, and sets all AC outputs to zero. Serial ata Output. Sinks and sources current. ata at OUT can be clocked out on the rising or falling edge of (Table ). Chip-Select Input (active low). ata is shifted in and out when is low. Programming commands are executed when retur high. Serial Clock Input. ata is clocked in on the rising edge and clocked out on the falling (default) or rising edge (A = A =, see Table ). Serial ata Input. ata is clocked in on the rising edge of. igital Ground Power Supply, +4.5V to +5.5V Analog Ground AC Voltage Output AC C Voltage Output 6

7 +5V, Low-Power, 8-Bit Quad AC INSTRUCTION EXECUTE IN A A C C A A C C MSB LSB MSB LSB ACA AC OUT MOE A A C C A A A C C A ATA FROM PREVIOUS ATA INPUT ATA FROM PREVIOUS ATA INPUT OUT MOE (EFAULT) A A C C A A A C C A Figure. 3-Wire Interface Timing t W t t S t CL t CH t CP t H t t S t H IN t 2 t OUT t CLL t LAC LAC Figure 2. etailed Serial-Interface Timing iagram 7

8 +5V, Low-Power, 8-Bit Quad AC etailed escription Serial Interface At power-on, the serial interface and all digital-toanalog converters (ACs) are cleared and set to code zero. The serial data output (OUT) is set to traition on s falling edge. The communicates with microprocessors through a synchronous, full-duplex, 3-wire interface (Figure ). ata is sent MSB first and can be tramitted in one 4-bit and one 8-bit (byte) packet or in one 2-bit word. If a 6-bit word is used, the first four bits are ignored. A 4-wire interface adds a line for LAC and allows asynchronous updating. The serial clock () synchronizes the data trafer. ata is tramitted and received simultaneously. Figure 2 shows the detailed serial-interface timing. Please note that the clock should be low if it is stopped between updates. OUT does not go into a highimpedance state if the clock idles or is high. Serial data is clocked into the data registers in MSB-first format, with the address and configuration information preceding the actual AC data. ata is clocked in on s rising edge while is low. ata at OUT is clocked out 2 clock cycles later, either at s falling edge (default or mode ) or rising edge (mode ). Chip select () must be low to enable the AC. If is high, the interface is disabled and OUT remai unchanged. must go low at least 4 before the first rising edge of the clock pulse to properly clock in the first bit. With low, data is clocked into the s internal shift register on the rising edge of the external serial clock. Always clock in the full 2 bits because each time goes high the bits currently in the input shift register are interpreted as a command. can be driven at rates up to MHz. Serial Input ata Format and Control Codes The 2-bit serial input format shown in Figure 3 comprises two AC address bits (A, A), two control bits (C, C), and eight bits of data (7...). The 4-bit address/control code configures the AC as shown in Table. A Address Load Input Register, AC Registers Unchanged (Single Update Operation) (LAC = H) When performing a single update operation, A and A select the respective input register. At the rising edge of, the selected input register is loaded with the current shift-register data. All AC outputs remain unchanged. This preloads individual data in the input register without changing the AC outputs. A A A Address (LAC = H) C C C C Bit ata Load Input and AC Registers 6 This command directly loads the selected AC register at s rising edge. A and A set the AC address. Current shift-register data is placed in the selected input and AC registers. For example, to load all four AC registers simultaneously with individual settings (AC A = V, AC B = 2V, AC C = 3V, and AC = 4V), four commands are required. First, perform three single input register update operatio for ACs A, B, and C (C = ). The final command loads input register and updates all four AC registers from their respective input registers Bit ata 2 2 Software LAC Command OUT THIS IS THE FIRST BIT SHIFTE IN MSB LSB A A C C IN CONTROL AN ARESS BITS 8-BIT AC ATA A A C C 7 6 x x x x x x x x (LAC = ) When this command is initiated, all AC registers are updated with the contents of their respective input registers at s rising edge. With the exception of using to execute, this performs the same function as the asynchronous LAC Figure 3. Serial Input Format 8

9 +5V, Low-Power, 8-Bit Quad AC Table. Serial-Interface Programming Commands A A 2-BIT SERIAL WOR C C X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8-bit AC data 8-bit AC data 8-bit AC data 8-bit AC data 8-bit AC data 8-bit AC data 8-bit AC data 8-bit AC data X X X X X X X X 8-bit AC data X X X X X X X X LAC X X X X X X X X X X X FUNCTION Load input register A; all AC outputs unchanged. Load input register B; all AC outputs unchanged. Load input register C; all AC outputs unchanged. Load input register ; all AC outputs unchanged. Load input register A; all AC outputs updated Load input register B; all AC outputs updated Load input register C; all AC outputs updated Load input register ; all AC outputs updated. Software LAC commands. Update all ACs from their respective input registers. Also bring the part out of shutdown mode. Load all ACs with shift-register data. Also bring the part out of shutdown mode. Software shutdown (provided PE is high) UPO goes low. UPO goes high. No operation (NOP); shift data in shift registers. Set OUT phase rising (mode ). OUT clocked out on rising edge of. All ACs updated from their respective input registers. Set OUT phase falling (mode ). OUT clocked out on falling edge of. All ACs updated from their respective registers (default). (LAC = X) Load All ACs with Shift-Register ata A A C C Bit ata When this command is initiated, all four AC registers are updated with shift-register data. This command allows all ACs to be set to any analog value within the reference range. It can be used to substitute CLR if code hex is programmed, which clears all ACs. (LAC = X, PE = H) Software Shutdown A A C C x x x x x x x x This command shuts down all output buffer amplifiers, reducing supply current to µa max. (LAC = X) User-Programmable Output (UPO) A A C C UPO Output x x x x x x x x Low x x x x x x x x High This command initiates the user-programmable logic output for controlling another device across an isolated interface. Example devices are gain control of an amplifier and a polarity output for a motor speed control. A A (LAC = X) C C No Operation (NOP) x x x x x x x x The NOP command (no operation) allows data to be shifted through the shift register without affecting the input or AC registers. This is useful in daisy chaining (also see the aisy Chaining evices section). 9

10 +5V, Low-Power, 8-Bit Quad AC For this command, the data bits are on't Cares. As an example, three s are daisy chained (A, B, and C), and devices A and C need to be updated. The 36-bit-wide command would coist of one 2-bit word for device C, followed by an NOP itruction for device B and a third 2-bit word with data for device A. At s rising edge, device B will not change state. A A C Set OUT Phase Rising (Mode ) C 7 6 x x x x x x x x Serial ata Output OUT is the internal shift register s output. OUT can be programmed to clock out data on s falling edge (mode ) or rising edge (mode ). In mode, output data lags input data by 2.5 clock cycles, maintaining compatibility with Microwire and SPI. In mode, output data lags input data by 2 clock cycles. On power-up, OUT defaults to mode timing. OUT never three-states; it always actively drives either high or low and remai unchanged when is high. (LAC = x) The mode command resets the serial-output OUT to traition at s rising edge. Once this command is issued, OUT s phase is latched and will not change except on power-up or if the specific command to set the phase to falling edge is issued. This command also loads all AC registers with the contents of their respective input registers, and is identical to the LAC command. Set OUT Phase Falling (Mode, efault) A A C C x x x x x x x x IN SK SO I/ MICROWIRE PORT (LAC = x) This command resets OUT to traition at s falling edge. The same command also updates all AC registers with the contents of their respective input registers, identical to the LAC command. Figure 4. Connectio for Microwire LAC Operation (Hardware) LAC is typically used in 4-wire interfaces (Figure 7). This command is level seitive, and allows asynchronous hardware control of the AC outputs. With LAC low the AC registers are traparent, and any time an input register is updated, the AC output immediately follows. IN MOSI SCK SPI/QSPI PORT Clear ACs with CLR Strobing the CLR pin low causes an asynchronous clear of input and AC registers and sets all AC outputs to zero. Similar to the LAC pin, CLR can be invoked at any time, typically when the device is not selected ( = H). When the AC data is all zeros, this function is equivalent to the Update all ACs from Shift Registers command. Figure 5. Connectio for SPI/QSPI I/

11 +5V, Low-Power, 8-Bit Quad AC Interfacing to the Microprocessor The is Microwire and SPI /QSPI compatible (Figures 4 and 5). For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = ). The SPI/QSPI CPOL = CPHA = configuration can also be used if the OUT output is ignored. The can interface with Intel s 8C5X/8C3X family in mode if the clock polarity is inverted. More universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. igital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. The clock idle state is low. aisy-chaining evices Any number of s can be daisy-chained by connecting OUT of one device to IN of the following device in the chain. The NOP itruction (Table ) allows data to be passed from IN to OUT without changing the input or AC registers of the passing device. A 3-wire interface updates daisy-chained or individual s simultaneously by bringing high (Figure 6). Analog Section AC Operation The uses a matrix decoding architecture for the ACs, which saves power in the overall system. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 8 shows a simplified diagram of the four ACs. Reference Input The voltage at REF sets the full-scale output voltage for all four ACs. The 46kΩ typical input impedance at REF is code independent. The output voltage for any AC can be represented by a digitally programmable voltage source as follows: VOUT = (NB x VREF) / 256 where NB is the numerical value of the AC s binary input code. IN IN OUT IN OUT IN OUT EVICE A EVICE B EVICE C TO OTHER SERIAL EVICES IN IN Figure 6. aisy-chained or individual s are simultaneously updated by bringing high. Only three wires are required.

12 +5V, Low-Power, 8-Bit Quad AC IN LAC 2 3 TO OTHER SERIAL EVICES LAC LAC LAC IN IN IN Figure 7. Multiple s sharing one IN line. Simultaneously update by strobing LAC, or specifically update by enabling an individual. 7 REF R R R5 R6 Output Buffer Amplifiers All voltage outputs are internally buffered by precision unity-gain followers that slew at about.6v/µs. The outputs can swing from GN to V. With a V to +4V (or +4V to V) output traition, the amplifier outputs will typically settle to /2LSB in 8µs when loaded with kω in parallel with pf. 6 5 MSB ECOER The buffer amplifiers are stable with any combination of resistive ( kω) or capacitive loads. 4 R255 LSB ECOER 3 2 AC A Figure 8. AC Simplified Circuit iagram 2

13 +5V, Low-Power, 8-Bit Quad AC Applicatio Information AC Linearity and Voltage Offset The output buffer can have a negative input offset voltage that would normally drive the output negative, but since there is no negative supply the output stays at V (Figure 9). When linearity is determined using the endpoint method, it is measured between zero code (all inputs ) and full-scale code (all inputs ) after offset and gain error are calibrated out. However, in singlesupply operation the next code after zero may not change the output, so the lowest code that produces a positive output is the lower endpoint. Power Sequencing The voltage applied to REF should not exceed V at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and V to eure compliance with the absolute maximum ratings. o not apply signals to the digital inputs before the device is fully powered up. Power-Supply Bypassing and Ground Management Connect AGN and GN together at the IC. This ground should then return to the highest-quality ground available. Bypass V with a.µf capacitor, located as close to V and GN as possible. Careful PC board layout minimizes crosstalk among AC outputs and digital inputs. Figure shows suggested circuit board layout to minimize crosstalk. Unipolar-Output, Two-Quadrant Multiplication In unipolar operation, the output voltages and the reference input are the same polarity. Figure shows the unipolar configuration, and Table 2 shows the unipolar code. OUTC OUT AGN SYSTEM GN OUTB OUTA REF Figure. Suggested PC Board Layout for Minimizing Crosstalk (Bottom View) REFERENCE INPUT +3V 3 3 REFAB V AC A 2 OUTA OUTPUT VOLTAGE V NEGATIVE OFFSET AC COE SERIAL INTERFACE NOT SHOWN AC B AC C 6 OUTB OUTC AC 5 OUT AGN GN 4 2 Figure 9. Effect of Negative Offset (Single Supply) Figure. Unipolar Output Circuit 3

14 +5V, Low-Power, 8-Bit Quad AC Table 2. Unipolar Code Table AC CONTENTS MSB LSB ANALOG OUTPUT +V 255 REF () 256 +V 29 REF () V REF +V REF () = V REF () 256 +V REF () 256 V Note: LSB = (V REF ) (2-8 ) = +V REF () 256 Functional iagram OUT CLR LAC UPO PE V REF GN AGN ECOE CONTROL INPUT REGISTER A AC REGISTER A AC A OUTA 2-BIT SHIFT REGISTER INPUT REGISTER B AC REGISTER B AC B OUTB INPUT REGISTER C AC REGISTER C AC C OUTC SR CONTROL INPUT REGISTER AC REGISTER AC OUT IN 4

15 +5V, Low-Power, 8-Bit Quad AC Chip Information TRANSISTOR COUNT: 682 Package Information e B A A S E N H A2 IM A A A2 B C E e H h L N S α INCHES MILLIMETERS SEE VARIATIONS BSC.635 BSC SEE VARIATIONS SEE VARIATIONS h x 45 E α IM S S S S PINS INCHES QSOP QUARTER SMALL-OUTLINE PACKAGE MILLIMETERS A C L 5

16 +5V, Low-Power, 8-Bit Quad AC Package Information A L Q e B B L E E -5 C IM A B B C E E e L L Q S S INCHES MILLIMETERS S S CERIP CERAMIC UAL-IN-LINE PACKAGE (.3 in.) IM PINS INCHES MILLIMETERS A A L A2 A e B B A3 Plastic IP PLASTIC UAL-IN-LINE PACKAGE (.3 in.) Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 6 Maxim Integrated Products, 2 San Gabriel rive, Sunnyvale, CA 9486 (48) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. E E - 5 C ea eb PKG. P P P P P N IM A A A2 A3 B B C E E e ea eb L IM PINS INCHES INCHES MILLIMETERS MILLIMETERS A