Low-Charge Injection, 16-Channel, High-Voltage Analog Switches MAX14800 MAX14803

Transcription

1 ; Rev 1; 9/09 Low-Charge Injection, 16-Channel, General Description The provide high-voltage switching on 16 channels for ultrasonic imaging and printer applications. The devices utilize HVCMOS process technology to provide 16 high-voltage lowcharge-injection SPST switches, controlled by a digital interface. Data is clocked into an internal 16-bit shift register and retained by a programmable latch with enable and clear inputs. A power-on reset function ensures that all switches are open on power-up. The operate with a wide range of high-voltage supplies including: / = +100V/ -100V, +200V/0V, or +40V/-160V. The digital interface operates from a separate +2.7V to +5.5V V DD supply. Digital inputs DIN,,, and operate on the V DD supply voltage. The MAX14801/ provide integrated 35kΩ bleed resistors on each switch terminal to discharge capacitive loads. The MAX14802/ provide integrated clamping diodes for overvoltage protection against positive overshoot. The are available in the 48-pin TQFP package. All devices are specified for the commercial 0 C to +70 C temperature range. Ultrasound Imaging Printers Applications Features Integrated Overvoltage Protection (MAX14802/ ) 20MHz Serial Interface (5V) HVCMOS Technology for High Performance Individually Programmable Higholtage Analog Switches Very Low 5µA (typ) Quiescent Current DC-to-20MHz Lowoltage Analog Signal Frequency Range 2.7V to 5.5V Logic Supply Voltage Low-Charge Injection, Low-Capacitance R L Switches -77dB (typ) Off-Isolation at 5MHz (R L = 50Ω) Daisy-Chainable Serial Interface Flexible Higholtage Supplies ( - = 250V) Pin Configuration appears at end of data sheet. Ordering Information/Selector Guide PART SWITCH CHANNELS BED RESISTOR OVP SECOND SOURCE PIN-PACKAGE TEMP RANGE MAX14800CCM+* 16 No No HV TQFP 0 C to +70 C MAX14801CCM+* 16 Yes No HV TQFP 0 C to +70 C MAX14802CCM+ 16 No Yes 48 TQFP 0 C to +70 C CCM+ 16 Yes Yes 48 TQFP 0 C to +70 C +Denotes a lead(pb)-free/rohs-compliant package. *Future product contact factory for availability. Parts with extended temperature range (-40 C to +85 C) are available upon request. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to.) V DD Logic-Supply Voltage V to +7V - Supply Voltage...260V Positive-Supply Voltage V to +220V Negative-Supply Voltage V to -220V Logic Inputs (,,, DIN, ) V to +7V COM_, NO_ (MAX14800/MAX14801)...(-0.3V + ) to ( + 220V) COM_, NO_ (MAX14802/)...(-0.3V + ) to the minimum of [( + 220V) or ( + 0.3V)] Peak Analog Signal Current Per Channel...3A Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ECTRICAL CHARACTERISTICS Continuous Power Dissipation (T A = +70 C) 48-Pin TQFP (derate 22.7mW/ C above +70 C) mW Junction-to-Ambient Thermal Resistance (θ JA ) (Note 1) 48-Pin TQFP...44 C/W Junction-to-Case Thermal Resistance (θ JC ) (Note 1) 48-Pin TQFP...10 C/W Operating Temperature Range (commercial)...0 C to +70 C Operating Temperature Range (Extended) C to +85 C Storage Temperature Range C to +150 C Junction Temperature C Lead Temperature (soldering, 10s) C (V DD = +2.7V to +5.5V, = +40V to + 250V, = -40V to -160V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES V DD Supply Voltage V DD V Supply Voltage Supply Voltage V V DD Supply Quiescent Current I DDQ 5 µa V V DD Supply Dynamic Current Supply Quiescent Current I DD V DD = +5V, = +5V, f = 5MHz 0.5 ma I PPQ All switches remain on or off, I COM_ = 5mA 0 10 µa Supply Dynamic Current (All Channel Switching Simultaneously) = +40V, = -160V, f COM_ = 50kHz 4 I PP = +100V, = -100V, f COM_ = 50kHz = +160V, = -40V, f COM_ = 50kHz 8 ma Supply Quiescent Current I NNQ All switches remain on or off, I COM_ = 5mA 0 10 µa Supply Dynamic Current (All Channel Switching Simultaneously) ANALOG SWITCH = +40V, = -160V, f COM_ = 50kHz 5 I NN = +100V, = -100V, f COM_ = 50kHz = +160V, = -40V, f COM_ = 50kHz 3 ma COM_, NO_ Analog Signal Range V COM_, V NO_ (Note 3) m i n of ( V N N + 200V) or ( - 10V) V 2

3 ECTRICAL CHARACTERISTICS (continued) (V DD = +2.7V to +5.5V, = +40V to + 250V, = -40V to -160V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Small-Signal Switch On-Resistance Small-Signal Switch On-Resistance Matching Large-Signal Switch On-Resistance R ONS = +40V, = -160V, I COM_ = 5mA V COM_ = 0 I COM_ = 200mA = +100V, = -100V, I COM_ = 5mA V COM_ = 0 I COM_ = 200mA = +160V, = -40V, I COM_ = 5mA V COM_ = 0 I COM_ = 200mA ΔR ONS = +100V, = -100V, V COM_ = 0, I COM_ = 5mA Ω 5 % R ONL V COM_ = - 10V, I COM_ = 1A 15 Ω Shunt Resistance R INT NO_ or COM_ to (MAX14801/), switch off Switch-Off Leakage kω I COM_(OFF), I NO_(OFF) V COM_, V NO_ = +100V or unconnected 0 2 µa Switch-Off DC Offset R L = 100kΩ mv Switch-Output Peak Current (Note 4) Switch-Output COM_ Isolation Diode Current (Note 4) SWITCH DYNAMIC CHARACTERISTICS 100ns pulse width, 0.1% duty cycle 3 A 300ns pulse width, 2% duty cycle (MAX14802/) Turn-On Time t ON V NO_ = +100V, R L = 10kΩ, = -100V Turn-Off Time t OFF V NO_ = +100V, R L = 10kΩ, = -100V Output Switching Frequency 500 ma µs µs f SW Duty cycle = 50% 50 khz Maximum V COM_, V NO_ Slew Rate dv/dt (Note 4) 20 V/ns f = 5MHz, R L = 1kΩ, C L = 15pF -50 Off-Isolation V ISO f = 5MHz, R L = 50Ω -77 Crosstalk V CT f = 5MHz, R L = 50Ω -80 db COM_, NO_ Off- Capacitance (Note 4) COM_ On-Capacitance (Note 4) Outputoltage Spike (Note 4) Small-Signal Analog Bandwidth C COM_(OFF), C NO_(OFF) V COM_ = 0, V NO_ = 0, f = 1MHz pf C COM_(ON) V COM_ = 0, f = 1MHz pf V SPK R L = 50Ω mv f BW = +100V, = -100V, C L = 200pF 20 MHz db 3

4 ECTRICAL CHARACTERISTICS (continued) (V DD = +2.7V to +5.5V, = +40V to + 250V, = -40V to -160V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Charge Injection LOGIC VELS Q = +40V, = -160V, V COM_ = = +100V, = -100V, V COM_ = = +160V, = -40V, V COM_ = Logic-Input Low Voltage V IL 0.75 V Logic-Input High Voltage V IH V DD Logic-Output Low Voltage V OL I SINK = 1mA 0.4 V Logic-Output High Voltage V OH I SOURCE = 0.75mA Logic-Input Capacitance (Note 4) V DD C IN 10 pf Logic-Input Leakage I IN µa pc V V TIMING CHARACTERISTICS (V DD = +2.7V to +5.5V, = +40V to + 200V, = -40V to -160V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC TIMING (Figure 1) V DD = +5V ±10% 20 Frequency f V DD = +3V ±10% 10 MHz V DD = +5V ±10% 10 DIN to Setup Time t DS V DD = +3V ±10% 16 V DD = +5V ±10% 3 DIN to Hold Time t DH V DD = +3V ±10% 3 V DD = +5V ±10% 36 to Setup Time t CS V DD = +3V ±10% 65 V DD = +5V ±10% 14 Low-Pulse Width t WL V DD = +3V ±10% 22 V DD = +5V ±10% 20 High-Pulse Width t WC V DD = +3V ±10% 40 V DD = +5V ±10% 50 Rise and Fall Times t R, t F V DD = +3V ±10% 50 V DD = +5V ±10% 6 42 to Delay t DO V DD = +3V ±10% ns ns ns ns ns ns ns Note 2: All devices are 100% tested at T A = +70 C. Limits over the operating temperature range are guaranteed by design and characterization. Note 3: The analog signal input V COM_ and V NO_ must satisfy (V COM_, V NO_ ), or remain unconnected during power-up and power-down. Note 4: Guaranteed by characterization; not production tested. 4

5 I SOL +100V -100V +100V -100V V OUT = 10V P-P AT 5MHz NO_ +100V COM_ COM_ R L 100kΩ V DD 5V V DD 5V SWITCH OFF AKAGE V OUT NO_ DC OFFSET ON/OFF R L 100kΩ V OUT - 10V -100V V OUT = 10V P-P AT 5MHz NO_ COM_ t ON/t OFF TEST CIRCUIT Test Circuits V DD 5V V OUT R L NO_ COM_ V DD 5V V OUT COM_ I ID NO_ V DD 5V 50Ω NO_ COM_ NO_ COM_ V DD 5V 50Ω V ISO = 20LOG VOUT V IN OFF ISOLATION ISOLATION DIODE CURRENT V CT = 20LOG VOUT V IN CROSSTALK V OUT SPK V OUT V COM_ 100pF NO_ COM_ SPK 50Ω V OUT R L 1kΩ NO_ COM_ V DD V DD V DD 5V Q = 1000pF x V OUT CHARGE INJECTION OUTPUTOLTAGE SPIKE 5

6 Typical Operating Characteristics (V DD = +3V, = +100V, = -100V, T A = +25 C, unless otherwise noted.) ON-RESISTANCE (Ω) OFF-ISOLATION (db) ON-RESISTANCE vs. ANALOG SIGNAL VOLTAGE = +40V, = -160V = +160V, = -40V = +100V, = -100V V COM_ (V) OFF-ISOLATION vs. FREQUENCY T A = +70 C T A = +25 C T A = 0 C FREQUENCY (MHz) MAX14800 toc01 MAX14800 toc04 ON-RESISTANCE (Ω) AKAGE CURRENT (na) ON-RESISTANCE vs. ANALOG SIGNAL VOLTAGE = +100V, = -100V T A = +70 C T A = +25 C 20 T A = 0 C V COM_ (V) AKAGE CURRENT vs. TEMPERATURE I COM_(ON) (V COM_ = +90V) I COM_(ON) (V COM_ = -90V) I COM_(ON) (V COM_ = 0V) I COM_(OFF) (V COM_ = +90V) I COM_(OFF) (V COM_ = -90V) I COM_(OFF) (V COM_ = 0V) TEMPERATURE ( C) MAX14800 toc02 MAX14800 toc05 TURN-ON/TURN-OFF TIME (μs) IDDQ SUPPLY CURRENT (μa) TURN-ON/TURN-OFF TIME vs. ANALOG SIGNAL VOLTAGE t OFF t ON V NO_ (V) LOGIC SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = +70 C T A = 0 C T A = +25 C V DD SUPPLY VOLTAGE (V) MAX14800 toc03 MAX14800 toc06 SUPPLY CURRENT (μa) HIGHOLTAGE SUPPLY CURRENT vs. TEMPERATURE = +100V = -100V I PP I NN MAX14800 toc07 IDD SUPPLY CURRENT (μa) LOGIC SUPPLY CURRENT vs. SERIAL-CLOCK FREQUENCY T A = +70 C T A = +25 C T A = 0 C MAX14800 toc08 SUPPLY CURRENT (ma) HIGHOLTAGE SUPPLY CURRENT vs. SWITCHING FREQUENCY ALL SWITCHES SWITCHING T A = +25 C I PP MAX14800 toc09 I NN TEMPERATURE ( C) SERIAL-CLOCK FREQUENCY (MHz) SWITCHING FREQUENCY (khz) 6

7 PIN NAME FUNCTION 1, 2, 14, 16, 24, 35, 36 N.C. No Connection. Not internally connected. 3 COM4 Analog Switch 4 Common Terminal 4 NO4 Analog Switch 4 Normally Open Terminal 5 NO3 Analog Switch 3 Normally Open Terminal 6 COM3 Analog Switch 3 Common Terminal 7 NO2 Analog Switch 2 Normally Open Terminal 8 COM2 Analog Switch 2 Common Terminal 9 COM1 Analog Switch 1 Common Terminal 10 NO1 Analog Switch 1 Normally Open Terminal 11 NO0 Analog Switch 0 Normally Open Terminal 12 COM0 Analog Switch 0 Common Terminal Pin Description 13 Negative Higholtage Supply. Bypass to with a 0.1µF or greater ceramic capacitor. 15 Positive Higholtage Supply. Bypass to with a 0.1µF or greater ceramic capacitor. 17 Ground 18 V DD Digital Supply Voltage. Bypass V DD to with a 0.1µF or greater ceramic capacitor. 19 DIN Serial-Data Input 20 Serial-Clock Input 21 Active-Low, Latch-Enable Input 22 Latch Clear Input 23 Serial-Data Output 25 COM15 Analog Switch 15 Common Terminal 26 NO15 Analog Switch 15 Normally Open Terminal 27 NO14 Analog Switch 14 Normally Open Terminal 28 COM14 Analog Switch 14 Common Terminal 29 COM13 Analog Switch 13 Common Terminal 30 NO13 Analog Switch 13 Normally Open Terminal 31 COM12 Analog Switch 12 Common Terminal 32 NO12 Analog Switch 12 Normally Open Terminal 33 NO11 Analog Switch 11 Normally Open Terminal 34 COM11 Analog Switch 11 Common Terminal 37 COM10 Analog Switch 10 Common Terminal 7

8 PIN NAME FUNCTION 38 NO10 Analog Switch 10 Normally Open Terminal 39 COM9 Analog Switch 9 Common Terminal 40 NO9 Analog Switch 9 Normally Open Terminal 41 COM8 Analog Switch 8 Common Terminal 42 NO8 Analog Switch 8 Normally Open Terminal 43 NO7 Analog Switch 7 Normally Open Terminal 44 COM7 Analog Switch 7 Common Terminal 45 NO6 Analog Switch 6 Normally Open Terminal 46 COM6 Analog Switch 6 Common Terminal 47 NO5 Analog Switch 5 Normally Open Terminal 48 COM5 Analog Switch 5 Common Terminal Pin Description (continued) DIN D N+1 50% D N 50% D N-1 50% 50% t WL t CS 50% 50% t DS t DH t DO 50% t OFF t ON SWITCH OFF ON 90% 10% 50% 50% t WC Figure 1. Serial Interface Timing 8

9 Detailed Description The provide high-voltage switching on 16 channels for ultrasound imaging and printer applications. The devices utilize HVCMOS process technology to provide 16 high-voltage lowcharge-injection SPST switches, controlled by a digital interface. Data is clocked into an internal 16-bit shift register and retained by a programmable latch with enable and clear inputs. A power-on-reset function ensures that all switches are open on power-up. The operate with a wide range of high-voltage supplies including: / = +100V/ -100V, +200V/0V, or +40V/-160V. The digital interface operates from a separate +2.7V to +5.5V V DD supply. Digital inputs DIN,,, and operate on the V DD supply voltage. The MAX14801/ provide integrated 35kΩ bleed resistors on each switch terminal to discharge capacitive loads. The MAX14802/ feature clamping diodes (at the COM_). These clamping diodes provide overvoltage protection against positive overshoot. Analog Switch The allow a peak-to-peak analog signal range from to the minimum of either + 200V or ( - 10V). Analog switch inputs must be unconnected, or satisfy (V COM_, V NO_ ) during power-up and power-down. Higholtage Supplies The allow a wide range of highvoltage supplies. The devices operate with from -160V to 0 and from +40V to + 250V. When is connected to (single-supply applications), the devices operate with up to +200V. The and high-voltage supplies are not required to be symmetrical, but the voltage difference ( - ) must not exceed 250V. Bleed Resistors (MAX14801/) The MAX14801/ feature integrated 35kΩ bleed resistors to discharge capacitive loads such as piezoelectric transducers. Each analog switch terminal is connected to with a bleed resistor. Overvoltage Protection (MAX14802/) The MAX14802/ feature clamping diodes (at the COM_). These clamping diodes provide overvoltage protection against positive overshoot. Serial Interface The are controlled by a serial interface with a 16-bit serial shift register and transparent latch. Each of the sixteen data bits controls a single analog switch (see Table 1). Data on DIN is clocked with the most significant bit (MSB) first into the shift register on the rising edge of. Data is clocked out of the shift register onto on the rising edge of. reflects the status of DIN, delayed by 16 clock cycles (see Figures 1 and 2). Latch Enable () Drive logic-low to change the contents of the latch and update the state of the high-voltage switches (Figure 2). Drive logic-high to freeze the contents of the latch and prevent changes to the switch states. To reduce noise due to clock feedthrough, drive logichigh while data is clocked into the shift register. After the data shift register is loaded with valid data, pulse logic-low to load the contents of the shift register into the latch. Latch Clear () The feature a latch clear input. Drive logic-high to reset the contents of the latch to zero and open all switches. does not affect the contents of the data shift register. Pulse logic-low to reload the contents of the shift register into the latch. Power-On Reset The feature a power-on-reset circuit to ensure all switches are open at power-on. The internal 16-bit serial shift register and latch are set to zero on power-up. 9

10 DIN D15 D15 MSB D14 D14 D13 D13 DATA FROM PREVIOUS DATA BYTE POWER-UP DEFAULT: D15 D0 = 0 D1 D0 LSB D1 D0 D15 Figure 2. Latch Enable Interface Timing Table 1. Serial Interface Programming (Notes 5 10) D0 (LSB) DATA BITS CONTROL BITS FUNCTION D1 D2 D3 D4 D5 D6 D7 SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF 10

11 Table 1. Serial Interface Programming (Notes 5 10) (continued) DATA BITS D8 D9 D10 D11 D12 D13 D14 D15 (MSB) CONTROL BITS FUNCTION SW8 SW9 SW10 SW11 SW12 SW13 SW14 SW15 X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF X = Don t care. Note 5: The 16 switches operate independently. Note 6: Serial data is clocked in on the rising edge of. Note 7: The switches go to a state retaining their present condition on the rising edge of. When is low, the shift register data flows through the latch. Note 8: is high when switch 15 is on. Note 9: Shift register clocking has no effect on the switch states if is high. Note 10: The input overrides all other inputs. 11

12 Applications Information For medical ultrasound applications, see Figures 4, 5, and 6. Logic Levels The digital interface inputs, DIN,, and operate on the V DD supply voltage. Daisy-Chaining Multiple Devices Digital output is provided to allow the connection of multiple devices by daisychaining (Figure 3). Connect each to the DIN of the subsequent device in the chain. Connect,, DIN1 DIN and inputs of all devices, and drive logic-low to update all devices simultaneously. Drive high to open all the switches simultaneously. Additional shift registers can be included anywhere in series with the data chain. Supply Sequencing and Bypassing The do not require special sequencing of the V DD,, and supply voltages; however, analog switch inputs must be unconnected, or satisfy (V COM_, V NO_ ) during power-up and power-down. Bypass V DD,, and to with a 0.1µF ceramic capacitor as close as possible to the device. Application Diagrams U10 U11 U1n DIN DIN U20 U21 U2n DIN2 DIN DIN DIN Figure 3. Interfacing Multiple Devices by Daisy-Chaining 12

13 HIGHOLTAGE TRANSMIT 1 PER CHANNEL LOWOLTAGE RECEIVE 64 TO 128 CHANNELS SECTION 2 TO 4 S RELAY 1 RELAY/CH/ CAB 1 PER CHANNEL ±100V MAX ±1 TO 2A MAX ±1V MAX 10mA TYP MAINFRAME A B C S HV ANALOG SWITCHES 2 TO 4 PER CHANNEL TRANSDUCERS 2 TO 4 PER CHANNEL HIGH- VOLTAGE ISOLATION D Figure 4. Medical Ultrasound Application in Probe 13

14 HV TRANSMIT 1 PER CHANNEL LV RECEIVE 64 TO 128 CHANNELS HV ANALOG SWITCHES SECTION 2 TO 4 S CAB 2 TO 4 PER CHANNEL 2 TO 4 PER CHANNEL ±100V MAX ±1 TO 2A MAX ±1V MAX 10mA TYP HIGH- VOLTAGE ISOLATION MAINFRAME RELAYS 2 TO 4 RELAYS/CH/ A B S TRANSDUCERS 2 TO 4 PER CHANNEL C D Figure 5. Medical Ultrasound Application in Mainframe 14

15 HIGHOLTAGE TRANSMIT 2 TO 4 PER CHANNEL LOWOLTAGE RECEIVE 64 TO 128 CHANNELS MAINFRAME SECTION 2 TO 4 S RELAYS 2 TO 4 RELAYS/CH/ A CAB 2 TO 4 PER CHANNEL ±100V MAX ±1 TO 2A MAX ±1V MAX 10mA TYP B S TRANSDUCERS 2 TO 4 PER CHANNEL C D HIGHOLTAGE ISOLATION AND CHANNEL SECT 2 TO 4 PER CHANNEL Figure 6. Medical Ultrasound Application Multiple Transmit and Isolation per Receiver Channel 15

16 DIN 16-BIT SHIFT REGISTER V DD LATCH LATCH MAX14802 VEL SHIFTER VEL SHIFTER Functional Diagram ** * * * * ** COM0 NO0 COM15 NO15 *BED RESISTORS AVAILAB ON THE ONLY. **OVERVOLTAGE PROTECTION DIODES ARE AVAILAB ON THE MAX14802 AND ONLY. 16

17 TOP VIEW COM10 37 NO10 38 COM9 39 NO9 40 COM8 41 NO8 42 NO7 43 COM7 44 NO6 45 COM6 46 NO5 47 N.C. N.C. COM11 NO11 NO12 COM12 NO13 COM13 COM14 NO N.C. DIN V DD N.C. N.C. COM N.C. N.C. COM4 NO4 NO3 COM3 NO2 COM2 COM1 NO1 NO0 COM0 NO15 COM15 Pin Configuration TQFP 7mm x 7mm PROCESS: BiCMOS Chip Information Package Information For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFP C

18 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 0 4/09 Initial release. 1 9/09 Corrected two specifications in the Absolute Maximum Ratings section. Changed the minimum of the peak-to-peak analog signal range to either + 200V or ( 10V). 2, 9 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.