Multiplexers/Switches

Transcription

1 EVALUATION KIT AVAILABLE / General Description The / are low-voltage, single-supply CMOS analog switches configured as a 4-channel multiplexer/demultiplexer () and a double-pole/double-throw (DPDT) switch (). The / have an inhibit input to simultaneously open all switches. These devices operate from a single supply of +2V to +2V. They are optimized for operation with a +2V supply. The on-resistance is Ω with a +2V supply. Each switch can handle Rail-to-Rail analog signals. Off-leakage current measures only 2nA at +25 C. All digital inputs have.8v to 2.V logic thresholds to ensure TTL/CMOSlogic compatibility when using a +2V supply. Applications Audio and Video Signal Routing Data-Acquisition Systems Communications Circuits DSL Modems Features +3V Logic-Compatible Inputs (V IH = 2.V, V IL =.8V) +2V to +2V Supply Operation Ω On-Resistance with +2V Supply Guaranteed Ω On-Resistance Match at +2V Guaranteed 2nA Maximum Off-Leakage at +2V TTL/CMOS-Logic Compatible Tiny -Pin TDFN (3mm x 3mm) and -Pin µmax Packages Ordering Information PART *EP = Exposed pad. TEMP RANGE PIN- PACKAGE TOP MARK EUB -4 C to +85 C μmax ETB -4 C to +85 C TDFN-EP* (3mm x 3mm) AAL EUB -4 C to +85 C μmax ETB -4 C to +85 C TDFN-EP* (3mm x 3mm) AAM Pin Configurations/Functional Diagrams/Truth Tables TOP VIEW NO2 NO3 NO LOGIC NO NOA A NCA LOGIC B NOB NCB ADD ON SWITCH X X NONE -NO -NO -NO2 -NO3 ON SWITCH X NONE A-NCA, B-NCB A-NOA, B-NOB µmax/tdfn µmax/tdfn 9-294; Rev 2; 4/4

2 / Absolute Maximum Ratings (All Voltages Referenced to, Unless Otherwise Noted.)...-.3V to +3V Voltage at Any Pin (Note )...-.3V to ( +.3V) Continuous Current into Any Terminal...±2mA Peak Current NO_, NC_ or _ (pulsed at ms, % duty cycle)...±4ma ESD per Method >2V Continuous Power Dissipation (T A = +7 C) -Pin µmax (derate 5.6mW/ C above +7 C)...444mW -Pin TDFN (derate 24.4mW/ C above +7 C)...95mW Operating Temperature Range MAX452_E C to +85 C Storage Temperature Range C to +5 C Junction Temperature...+5 C Lead Temperature (soldering, s)...+3 C Note : Voltages exceeding or on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum current rating. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics Single +2V Supply ( = 2V ±5%, = V, V IH = 2.V, V IL =.8V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS TEMP MIN TYP MAX UNITS ANALOG SWITCH Analog Signal Range V, V NO_ -4 C to +85 C V -NO/NC On-Resistance -NO/NC On-Resistance Match Between Channels R ON R ON =.4V, I = ma, V = V =.4V, I = ma, V = V (Note 4) +25 C C to +85 C +25 C 2-4 C to +85 C 5 Ω Ω -NO/NC On- Resistance Flatness R FLAT =.4V, I = ma, V =.5V, 6.V, V (Note 5) +25 C 5 2 Ω NO/NC Off-Leakage I NO(OFF) = 2.6V, V NO =.V, V, I NC(OFF) V = V,.V (Note 6) Off-Leakage I (OFF) V NO = V, V; V = V, = 2.6V, V (Note 6) ON-Leakage I (ON) V = V, = 2.6V, V (Note 6) DIGITAL I/O (, ADD_) +25 C C to +85 C C C to +85 C C C to +85 C C C to +85 C C C to +85 C Logic-Input Threshold High V IH -4 C to +85 C.5 2. V Logic-Input Threshold Low V IL -4 C to +85 C.8.5 V Input Current High I IH _ = V = 2.V +25 C - + µa Input Current Low I IL _ = V =.8V +25 C - + µa na na na Maxim Integrated 2

3 / Electrical Characteristics (continued) ( = 2V ±5%, = V, V IH = 2.V, V IL =.8V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS TEMP MIN TYP MAX UNITS SWITCH DYNAMIC CHARACTERISTICS Inhibit Turn-On Time t ON V NO_ = V, R L = 3Ω, C L =, Figure Inhibit Turn-Off Time t OFF V NO_ = V, R L = 3Ω, C L =, Figure Address Transition Time t TRANS V NO_ = V, R L = 3Ω, C L =, Figure 2 Break-Before-Make Time t BBM V NO = V, R L = 3Ω, C L =, Figure C C to +85 C C C to +85 C C C to +85 C C 2 ns Charge Injection Q C = nf, Figure 4 (Note 7) +25 C.8 pc NO/NC Off-Capacitance C NO(OFF) V NO_ = V, ƒ = MHz, Figure C 4 pf Off-Capacitance C (OFF) V NO_ = V, ƒ = MHz, Figure 5 On-Capacitance C (ON) V NO_ = V, ƒ = MHz, Figure C C C C 2 Off-Isolation V ISO R L = 5Ω, ƒ = MHz, Figure C 92 db Channel-to-Channel Crosstalk () On-Channel -3dB Bandwidth Total Harmonic Distortion POWER SUPPLY V CT R L = 5Ω, ƒ = MHz, Figure C 96 db BW Figure C 2 MHz THD R L = 6Ω, V = 2.5V P-P, 2Hz to 2kHz BW +25 C.2 % Power-Supply Range -4 C to +85 C V Power-Supply Current I+ = 2.6V, _ = V = or V +25 C C to +85 C - + Note 2: The TDFN package is production tested at T A = +25 C. Limits over temperature are guaranteed by design. Note 3: The algebraic convention used in this data sheet is where the most negative value is a minimum column. Note 4: R ON = R ON(MAX) - R ON(MIN). Note 5: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Note 6: Leakage parameters are % tested at maximum-rated hot operating temperature and guaranteed by design at T A = +25 C Note 7: Guaranteed by design, not production tested. ns ns ns pf pf μa Maxim Integrated 3

4 / Typical Operating Characteristics ( = 2V, V =, T A = +25 C, unless otherwise noted.) ON-RESISTANCE (Ω) ON-RESISTANCE vs. V toc ON-RESISTANCE (Ω) ON-RESISTANCE vs. V T A = +85 C T A = -4C T A = +7 C T A = C T A = +25 C toc2 OFF-LEAKAGE CURRENT (na).. OFF-LEAKAGE CURRENT vs. TEMPERATURE I _OFF I NO_OFF toc V (V) V (V) TEMPERATURE ( C) ON-LEAKAGE CURRENT (na).. ON-LEAKAGE CURRENT vs. TEMPERATURE TOTAL HARMONIC DISTORTION (%) TEMPERATURE ( C) TOTAL HARMONIC DISTORTION vs. FREQUENCY toc7. 6Ω IN AND OUT... k k k FREQUENCY (Hz) toc4 CHARGE INJECTION (pc) CHARGE INJECTION vs. V V (V) GAIN (db) toc5 SUPPLY CURRENT (na) ON LOSS ON-PHASE. FREQUENCY RESPONSE OFF-ISOLATION SUPPLY CURRENT vs. TEMPERATURE V = _ = OR TEMPERATURE ( C) FREQUENCY (MHz) CROSSTALK toc PHASE (DEGREES) toc6 Maxim Integrated 4

5 / Typical Operating Characteristics (continued) ( = 2V, V =, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (A),.. SUPPLY CURRENT vs. LOGIC-LEVEL VOLTAGE toc9 LOGIC THRESHOLD (V) INPUT LOGIC THRESHOLD vs. SUPPLY VOLTAGE toc _, V (V) SUPPLY VOLTAGE (V) Pin Description PIN NAME NO2 Analog Switch Normally Open Input 2 NOA Analog Switch A Normally Open Input 2 NO3 Analog Switch Normally Open Input 3 2 A Analog Switch A Common 3 NO Analog Switch Normally Open Input 3 NCA Analog Switch A Normally Closed Input FUNCTION Inhibit. Drive low or connect to for normal operation. Drive high or connect to to turn all switches off. Ground. Connect to digital ground (analog signals have no ground reference, but are limited to and ). 6 Logic-Level Address Input (see Truth Tables) 6 ADD Logic-Level Address Input (see Truth Tables) 7 Logic-Level Address Input (see Truth Tables) 7 NCB Analog Switch B Normally Closed Input 8 NO Analog Switch Normally Open Input 8 NOB Analog Switch B Normally Open Input 9 Analog Switch Common 9 B Analog Switch A Common Positive Analog and Digital Supply Voltage. Bypass with a.µf capacitor to. EP EP Exposed PAD The bottom of the IC (TDFN package only) contains an exposed pad that must be connected externally to. Maxim Integrated 5

6 / Detailed Description The / are low-voltage, single-supply CMOS analog switches that operate from a single supply of +2V to +2V. Operation with a +2V supply optimizes the performance by reducing their on-resistance to Ω. The is configured as a 4-channel multiplexer/demultiplexer and the is a doublepole/double-throw (DPDT) switch. These devices have an inhibit input () to simultaneously open all signal paths. Each switch can handle rail-to-rail analog signals. The off-leakage current is typically only.na at +25 C and na (max) over temperature. All digital inputs have.8v to 2.V logic-level thresholds, ensuring TTL/CMOS-logic compatibility when using a single +2V supply. Applications Information Power-Supply Considerations The /s construction is typical of most CMOS analog switches. The supply input,, is used to power the internal CMOS switches and set the limits of the analog voltage on any switch. Reverse ESD protection diodes are internally connected between each analog signal pin and both and. If any analog signal exceeds or goes below, one of these diodes conducts. During normal operation, these reversebiased ESD diodes leak, forming the only current drawn from or. Virtually all the analog leakage current comes from the ESD diodes. Although the ESD diodes on a given signal pin are identical, and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means that leakage varies as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of either the same or opposite polarity. There is no connection between the analog signal paths and. and power the internal logic and logiclevel translators, and set both the input and output logic limits. The logic-level translators convert the logic levels into switched and signals to drive the gates of the analog signals. This drive signal is the only connection between the logic supplies (and signals) and the analog supplies. Test Circuits/Timing Diagrams NO NO NO3 V V V NO 5% 9% V 5W 3W V 9% t ON t OFF ADD NO_ V V 5% V 5W NC 3W V NO_ V 9% 9% t ON t OFF Figure. Inhibit Switching Times Maxim Integrated 6

7 / Test Circuits/Timing Diagrams (continued) 5Ω NO NO NO2 NO3 V V NO 5% 9% 9% 3Ω V t TRANS t TRANS ADD NO V 5% 5Ω NC V NC 9% 9% 3Ω V t TRANS t TRANS Figure 2. Address Transition Time Maxim Integrated 7

8 / Test Circuits/Timing Diagrams (continued) 5Ω NO N3 3W 5% t R < 2ns t F < 2ns V V 8% 5Ω ADD NO_, NC_ V t BBM 3W Figure 3. Break-Before-Make Interval NO_ V NO = V V V V 5Ω _ CL = pf IS THE MEASURED VOLTAGE DUE TO CHARGE- TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF. Q = x C L. Figure 4. Charge Injection Maxim Integrated 8

9 / Test Circuits/Timing Diagrams (continued) CHANNEL SELECT NO_ NO MHz CAPACITANCE ANALYZER Figure 5. NO/ Capacitance nf NETWORK ANALYZER CHANNEL SELECT NO_ VIN 5W 5W _ VOUT MEAS. REF. 5Ω 5Ω OFF-ISOLATION = 2log x V IN MEASUREMENTS ARE STANDARDIZED AGAINST SHORT AT SOCKET TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN AND "OFF" NO TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN AND "ON" NO TERMINAL ON EACH SWITCH. CROSSTALK () IS MEASURED FROM ONE CHANNEL (A, B) TO OTHER CHANNEL SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. ON-LOSS = 2log x V IN CROSSTALK = 2log x V IN Figure 6. Off-Isolation, On-Loss, and Crosstalk Chip Information TRANSISTOR COUNT: 29 PROCESS: CMOS Maxim Integrated 9

10 / Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. LAND PATTERN NO. µmax U Refer to Application Note TDFN T Maxim Integrated

11 / Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 6/7 Pages changed, 5, 6,, 2 2 4/4 Removed automotive reference in Applications section For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim Integrated s website at Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 24 Maxim Integrated Products, Inc.