20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP

Transcription

1 9-2626; Rev ; /2 2, 3MHz Bandwidth, Dual SPDT Analog General Description The low-voltage, low on-resistance (R ON ), dual single-pole/double throw (SPDT) analog switch operates from a single +.8V to +5.5V supply. The features 2 R ON (max) with.2 flatness and.4 matching between channels. The switch offers break-before-make switching () with t ON <8 and t OFF <4 at +2.7V. The digital logic inputs are +.8V logic compatible with a +2.7V to +3.6V supply. The switch is packaged in a chip-scale package (UCSP ), significantly reducing the required PC board area. The chip occupies only a 2.mm.5mm area and has a 4 3 bump array with a bump pitch of.5mm. The is also available in a -pin µmax package. Applicatio Cell Phones Battery-Operated Equipment Audio/Video-Signal Routing Low-Voltage Data-Acquisition Systems Sample-and-Hold Circuits PDAs UCSP is a trademark of Maxim Integrated Products, Inc. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Features -3dB Bandwidth: >3MHz Low 5pF On-Channel Capacitance Single-Supply Operation from +.8V to +5.5V 2 R ON (max) Switch.4 (max) R ON Match (+3.V Supply).2 (max) R ON Flatness (+3.V Supply) Rail-to-Rail Signal Handling High Off-Isolation: -55dB (MHz) Low Crosstalk: -8dB (MHz) Low Distortion:.3% +.8V CMOS-Logic Compatible <.5nA Leakage Current at +25 C PART Ordering Information TEMP RANGE PIN/BUMP- PACKAGE TOP MARK EUB -4 C to +85 C µmax EBC-T* -4 C to +85 C 2 UCSP-2 ABJ Note: UCSP package requires special solder temperature profile described in the Absolute Maximum Ratings section. *UCSP reliability is integrally linked to the user s assembly methods, circuit board material, and environment. See the UCSP reliability notice in the UCSP Reliability section of this data sheet for more information. Pin Configuratio/Functional Diagrams/Truth Table TOP VIEW (BUMP SIDE DOWN) NC IN C C2 B A A2 NC2 IN2 IN_ NO_ OFF NC_ ON NO NO2 2 9 COM2 COM C3 A3 COM2 ON OFF SWITCHES SHOWN FOR LOGIC "" INPUT COM IN IN2 NC2 NO C4 B4 A4 NO2 NC 5 6 UCSP µmax Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (All Voltages Referenced to ), IN_...-.3V to +6.V COM_, NO_, NC_ (Note )...-.3V to ( +.3V) Continuous Current COM_, NO_, NC_...±mA Peak Current COM_, NO_, NC_ (pulsed at ms, % duty cycle)...±2ma Continuous Power Dissipation (T A = +7 C) -Pin µmax (derate 5.6mW/ C above +7 C)...444mW 2-Bump UCSP (derate.4mw/ C above +7 C)...99mW ESD Method kV Operating Temperature Range...-4 C to +85 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C Bump Temperature (soldering) (Note 2) Infrared (5s) C Vapor Phase (6s) C Note : Signals on COM_, NO_, or NC_ exceeding or are clamped by internal diodes. Limit forward-diode current to maximum current rating. Note 2: This device is cotructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry standard specification, JEDEC 2A, paragraph 7.6, table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Single +3V Supply ( = +2.7V to +3.6V, V IH = +.4V, V IL = +.5V, T A =, unless otherwise noted. Typical values are at = +3.V, T A = +25 C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX UNITS Analog Signal Range ANALOG SWITCH V COM_, V NO_, V NC_ On-Resistance (Note 5) R ON = 2.7V, I COM_ = ma; V NO_ or V NC_ =.5V On-Resistance Match Between Channels (Notes 5, 6) On-Resistance Flatness (Note 7) NO_, NC_ Off-Leakage Current COM_ On-Leakage Current DYNAMIC CHARACTERISTICS R ON R FLAT(ON) I NO_(OFF), I NC_(OFF) I COM_(ON) = 2.7V, I COM_ = ma; V NO_ or V NC_ =.5V = 2.7V, I COM_ = ma; V NO_ or V NC_ =.V,.5V, 2.V = 3.6V, V COM_ =.3V, 3.3V; V NO_ or V NC_ = 3.3V,.3V = 3.6V, V COM_ =.3V, 3.3V; V NO_ or V NC_ =.3V, 3.3V, or floating Turn-On Time t ON V NO_, V NC_ =.5V; R L = 3, C L = 35pF, Figure V +25 C C C C C C 4 8 na na 2

3 ELECTRICAL CHARACTERISTICS Single +3V Supply (continued) ( = +2.7V to +3.6V, V IH = +.4V, V IL = +.5V, T A =, unless otherwise noted. Typical values are at = +3.V, T A = +25 C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX UNITS Turn-Off Time t OFF V NO_, V NC_ =.5V; R L = 3, C L = 35pF, Figure Break-Before-Make Time Delay Charge Injection t BBM Q V NO_, V NC_ =.5V; R L = 3, C L = 35pF, Figure 2 V GEN = 2V, R GEN = ; C L =.nf, Figure 3 f = MHz; V NO_, V NC_ = V P-P ; R L = 5, C L = 5pF, Figure 4 Off-Isolation V ISO f = MHz; V NO_, V NC_ = V P-P ; R L = 5, C L = 5pF, Figure 4 f = MHz; V NO_, V NC_ = V P-P ; R L = 5, C L = 5pF, Figure 4 Crosstalk (Note 9) V CT f = MHz; V NO_, V NC_ = V P-P ; R L = 5, C L = 5pF, Figure 4 On-Channel -3dB Bandwidth BW Signal = dbm, R L = 5; C L = 5pF, Figure C C C 8 pc +25 C +25 C db db +25 C 3 MHz Total Harmonic Distortion THD V COM = 2V P-P, R L = C.3 % NO_, NC_ Off-Capacitance C NO_(OFF) C NC_(OFF) f = MHz, Figure C 9 pf Switch On-Capacitance C ON f = MHz, Figure C 2 pf DIGITAL I/O Input Logic High Voltage V IH.4 V Input Logic Low Voltage V IL.5 V Input Leakage Current I IN = +3.6V, V IN_ = V or 5.5V POWER SUPPLY Power-Supply Range Supply Current I+ = +5.5V, V IN_ = V or - + na V µa 3

4 ELECTRICAL CHARACTERISTICS Single +5V Supply ( = +4.2V to +5.5V, V IH = +2.V, V IL = +.8V, T A =, unless otherwise noted. Typical values are at = +5.V, T A = +25 C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX UNITS Analog Signal Range ANALOG SWITCH V COM_, V NO_, V NC_ On-Resistance (Note 5) R ON = 4.2V, I COM_ = ma; V NO_ or V NC_ = 3.5V On-Resistance Match Between Channels (Notes 5, 6) On-Resistance Flatness (Note 7) NO_, NC_ Off-Leakage Current COM_ On-Leakage Current DYNAMIC CHARACTERISTICS R ON R FLAT(ON) I NO_(OFF), I NC_(OFF) I COM_(ON) = 4.2V, I COM_ = ma; V NO_ or V NC_ = 3.5V = 4.2V, I COM_ = ma; V NO_ or V NC_ =.V, 2.V, 4.5V = 5.5V; V COM_ =.V, 4.5V; V NO_ or V NC_ = 4.5V,.V = 5.5V, V COM_ =.V, 4.5V; V NO_ or V NC_ =.V, 4.5V, or floating Turn-On Time t ON V NO_, V NC_ = 3.V; R L = 3, C L = 35pF, Figure Turn-Off Time t OFF V NO_, V NC_ = 3.V; R L = 3, C L = 35pF, Figure Break-Before-Make Time Delay DIGITAL I/O t BBM V NO_, V NC_ = 3.V; R L = 3, C L = 35pF, Figure 2 V +25 C C C C C C C C 8 Input Logic High Voltage V IH 2. V na na Input Logic Low Voltage V IL.8 V Input Leakage Current I IN = 5.5V, V IN _ = V or µa 4

5 ELECTRICAL CHARACTERISTICS Single +5V Supply (continued) ( = +4.2V to +5.5V, V IH = +2.V, V IL = +.8V, T A =, unless otherwise noted. Typical values are at = +5.V, T A = +25 C, unless otherwise noted.) (Notes 3, 4) POWER SUPPLY PARAMETER SYMBOL CONDITIONS TA MIN TYP MAX UNITS Power-Supply Range Supply Current I+ = 5.5V, V IN_ = V or V µa Note 3: UCSP parts are % tested at +25 C only, and guaranteed by design over the specified temperature range. µmax parts are % tested at and guaranteed by design over the specified temperature range. Note 4: The algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive value is a maximum. Note 5: Guaranteed by design for UCSP parts. Note 6: R ON = R ON(MAX) - R ON(MIN). Note 7: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Note 8: Guaranteed by design. Note 9: Between any two switches. (T A = +25 C, unless otherwise noted.) Typical Operating Characteristics 2 8 ON-RESISTANCE vs. V COM =.8V toc 5 4 = 3V ON-RESISTANCE vs. V COM T A = +85 C toc2 5 4 = 5V ON-RESISTANCE vs. V COM toc3 RON () 6 4 = 2.5V = 4.2V RON () 3 2 RON () 3 2 T A = +85 C 2 = 5V V COM (V) T A = -4 C T A = +25 C V COM (V) T A = -4 C T A = +25 C V COM (V) 5

6 (T A = +25 C, unless otherwise noted.) LEAKAGE CURRENT vs. TEMPERATURE 7 = 3V LEAKAGE CURRENT (pa) 5 COM ON-LEAKAGE 3 COM OFF-LEAKAGE toc4 LEAKAGE CURRENT (pa) Typical Operating Characteristics (continued) LEAKAGE CURRENT vs. TEMPERATURE = 5V COM OFF-LEAKAGE COM ON-LEAKAGE toc5 CHARGE INJECTION (pc) CHARGE INJECTION vs. V COM C L = nf = 3V C L = nf = 5V toc TEMPERATURE ( C) TEMPERATURE ( C) V COM (V) 6 5 SUPPLY CURRENT vs. TEMPERATURE toc7 8 SUPPLY CURRENT vs. LOGIC LEVEL toc8 SUPPLY CURRENT (na) = 5V = 3V SUPPLY CURRENT (µa) = 3V = 5V TEMPERATURE ( C) LOGIC LEVEL (V) LOGIC THRESHOLD vs. SUPPLY VOLTAGE 2..6 toc9 8 TURN-ON/OFF TIME vs. SUPPLY VOLTAGE toc LOGIC THRESHOLD (V).2.8 V TH+ V TH- ton/toff () 6 4 t ON.4 2 t OFF SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 6

7 (T A = +25 C, unless otherwise noted.) ton/toff () TURN-ON/OFF TIME vs. TEMPERATURE t ON, = 3.V t ON, = 5.V t OFF, = 3.V t OFF, = 5.V toc ON-LOSS (db) Typical Operating Characteristics (continued) = 3V/5V FREQUENCY RESPONSE ON-LOSS OFF-ISOLATION CROSSTALK toc2 THD (%). TOTAL HARMONIC DISTORTION vs. FREQUENCY = 3V R L = 6 toc TEMPERATURE ( C) -4.. FREQUENCY (MHz). k k k FREQUENCY (Hz) PIN UCSP µmax A 7 NC2 A2 8 IN2 A3 9 COM2 NAME FUNCTION Analog Switch 2 Normally Closed Digital Control Input for Analog Switch 2 Analog Switch 2 Common A4 NO2 Analog Switch 2 Normally Open B 6 Ground B4 Positive-Supply Voltage Input C 5 NC C2 4 IN C3 3 COM C4 2 NO Pin Description Analog Switch Normally Closed Digital Control Input for Analog Switch Analog Switch Common Analog Switch Normally Open Detailed Description The high-speed, low-voltage, 2 R ON, dual SPDT analog switch operates from a single +.8V to +5.5V supply. The switch features break-before-make switching operation and fast switching speeds (t ON = 8 (max), t OFF = 4 (max)). Applicatio Information Digital Control Inputs The logic inputs accept up to +5.5V regardless of supply voltage. For example, with a +3.3V supply, IN_ can be driven low to and high to +5.5V allowing for mixing of logic levels in a system. Driving the control logic inputs rail-to-rail minimizes power coumption. For a +3V supply voltage, the logic thresholds are.5v (low) and.4v (high); for a +5V supply voltage, the logic thresholds are.8v (low) and 2.V (high). Analog Signal Levels The on-resistance of the changes very little for analog input signals across the entire supply voltage range (see the Typical Operating Characteristics). The switches are bidirectional, so the NO_, NC_, and COM_ pi can be either inputs or outputs. 7

8 Power-Supply Sequencing and Overvoltage Protection Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the device. Proper power-supply sequencing is recommended for all CMOS devices. Always apply before applying analog signals, especially if the analog signal is not current-limited. UCSP Package Coideratio For general UCSP package information and PC layout coideratio, please refer to the Maxim Application Note (Wafer-Level Chip-Scale Package). UCSP Reliability The chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user s assembly methods, circuit board material, and usage environment. The user should closely review these areas when coidering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remai uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater coideration for a UCSP package. UCSPs are attached through direct solder contact to the user s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be coidered. Information on Maxim s qualification plan, test data, and recommendatio are detailed in the UCSP application note, which can be found on Maxim s website at TRANSISTOR COUNT: 235 PROCESS: BiCMOS Chip Information Test Circuits/Timing Diagrams LOGIC INPUT V N_ NO_ OR NC_ IN_ COM_ R L 3 C L 35pF LOGIC INPUT SWITCH OUTPUT V IH V IL V 5% t ON t OFF tr < 5 tf < 5.9 x V UT.9 x C L INCLUDES FIXTURE AND STRAY CAPACITANCE. = V N_ ( R L R L + R ON ) LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. Figure. Switching Time V N_ NC_ NO_ COM_ LOGIC INPUT V IH V IL 5% IN_ R L 3 C L 35pF LOGIC INPUT.9 x t BBM Figure 2. Break-Before-Make Interval C L INCLUDES FIXTURE AND STRAY CAPACITANCE. 8

9 V GEN R GEN NC_ OR NO_ IN_ COM_ Test Circuits/Timing Diagrams (continued) IN C L OFF OFF ON V IL TO V IH IN OFF ON Q = ( )(C L ) OFF IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 3. Charge Injection V OR IN_ +5V nf COM V IN NETWORK ANALYZER 5 5 OFF-ISOLATION = 2log V IN ON-LOSS = 2log V IN 5 NC NO* MEAS REF CROSSTALK = 2log V IN 5 5 MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. *FOR CROSSTALK THIS PIN IS NO2. NC2 AND COM2 ARE OPEN. Figure 4. On-Loss, Off-Isolation, and Crosstalk nf COM_ CAPACITANCE METER f = MHz NC_ or NO_ IN V IL OR V IH Figure 5. Channel Off/On-Capacitance 9

10 Package Information (The package drawing(s) in this data sheet may not reflect the most current specificatio. For the latest package outline information, go to 2L, UCSP 4x3.EPS

11 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specificatio. For the latest package outline information, go to e ÿ.5±..6±. TOP VIEW 4X S H BOTTOM VIEW DIM A A MIN -.2 MAX.43.6 MIN -.5 MAX..5 A D D2 E E2 H L L b e c S α INCHES MILLIMETERS REF.94 REF BSC.5 BSC REF.498 REF 6 6 LUMAX.EPS D2 E2 GAGE PLANE A2 A c D b A α E L L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, L umax/usop APPROVAL DOCUMENT CONTROL NO. REV. 2-6 I Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.