High Speed FET-Input INSTRUMENTATION AMPLIFIER

Transcription

1 High Speed FET-Input INSTRUMENTATION AMPLIFIER FEATURES FET INPUT: I B = 2pA max HIGH SPEED: T S = 4µs (G =,.%) LOW OFFSET VOLTAGE: µv max LOW OFFSET VOLTAGE DRIFT: µv/ C max HIGH COMMON-MODE REJECTION: 6dB min 8-PIN PLASTIC DIP, SOL-6 SOIC APPLICATIONS MEDICAL INSTRUMENTATION DATA ACQUISITION DESCRIPTION The is a high speed, FET-input instrumentation amplifier offering excellent performance. The uses a current-feedback topology providing extended bandwidth (2MHz at G = ) and fast settling time (4µs to.% at G = ). A single external resistor sets any gain from to over. Offset voltage and drift are laser trimmed for excellent DC accuracy. The s FET inputs reduce input bias current to under 2pA, simplifying input filtering and limiting circuitry. The is available in 8-pin plastic DIP, and SOL-6 surface-mount packages, specified for the 4 C to 8 C temperature range. V 7 (3) 2 (4) (2) 8 () 3 () A A 2 kω kω kω A 3 kω Feedback (2) 6 () () DIP Connected Internally G = kω DIP 4 V (7) (SOIC) International Airport Industrial Park Mailing Address: PO Box 4 Tucson, AZ 8734 Street Address: 673 S. Tucson Blvd. Tucson, AZ 876 Tel: (2) 746- Twx: Cable: BBRCORP Telex: FAX: (2) 889- Immediate Product Info: (8) Burr-Brown Corporation PDS-43D Printed in U.S.A. December, 99

2 SPECIFICATIONS ELECTRICAL T A = 2 C, V S = ±V, R L = 2kΩ, unless otherwise noted. BP, BU AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS INPUT Offset Voltage, RTI Initial T A = 2 C ± ± /G ± ± 2/G ±2 ± /G ± ± /G µv vs Temperature T A = T MIN to T MAX ±2 ± /G ± ± /G ±2 ± 2/G ± ± /G µv/ C vs Power Supply V S = ±6V to ±8V 2 /G 3 /G * * µv/v Impedance, Differential 2 6 * Ω pf Common-Mode 2 3 * Ω pf Input Common-Mode Range V DIFF = V ± ±2 * * V Common-Mode Rejection V CM = ±V, R S = kω G = * db G = 96 9 * db G = 6 * db G = 6 * db BIAS CURRENT ±2 ±2 * * pa OFFSET CURRENT ±. ± * * pa NOISE VOLTAGE, RTI G =, R S = Ω f = Hz 3 * nv/ Hz f = khz * nv/ Hz f = khz * nv/ Hz f B =.Hz to Hz * µvp-p Noise Current f = khz.8 * fa/ Hz GAIN Gain Equation (kω/ ) * V/V Range of Gain * * V/V Gain Error G =, R L = kω ±. ±.2 *. % G =, R L = kω ±. ±. * * % G =, R L = kω ±. ±. * ±.7 % G =, R L = kω ±.2 ± * ±2 % Gain vs Temperature G = ± ± * * ppm/ C kω Resistance () ±2 ± * * ppm/ C Nonlinearity G = ±. ±. * * % of FSR G = ±. ±. * ±. % of FSR G = ±. ±. * ±. % of FSR G = ±. ±.2 * ±.4 % of FSR OUTPUT Voltage I O = ma, T MIN to T MAX ± ±2.7 * * V Load Capacitance Stability * pf Short Circuit Current 3/2 * ma FREQUEY RESPONSE Bandwidth, 3dB G = 2 * MHz G = 2 * MHz G = 4 * khz G = * khz Slew Rate = ±V, G = 2 to 7 * V/µs Settling Time,.% G = 2 * µs G = 2 * µs G = 4 * µs G = 3 * µs Overload Recovery % Overdrive * µs POWER SUPPLY Voltage Range ±6 ± ±8 * * * V Current = V ±3.3 ±4. * * ma TEMPERATURE RANGE Specification 4 8 * * C Operating Plastic P, U 4 2 * * C θ JA Plastic P, U * C/W * Specification same as BP. NOTE: () Temperature coefficient of the kω term in the gain equation. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 2

3 DICE INFORMATION FPO PAD FUTION A, B 2 V IN 3 V IN 4 V PAD FUTION 6 7 Feedback 8 V 9A, 9B Pads A and B must be connected. Pads 9A and 9B must be connected. = No Connection. Substrate Bias: Internally connected to V power supply. MECHANICAL INFORMATION MILS (.") MILLIMETERS Die Size 29 x 9 ± 3.28 x 2.29 ±.3 Die Thickness 2 ±3. ±.8 Min. Pad Size 4 x 4. x. Backing Gold DIE TOPOGRAPHY PIN CONFIGURATIONS Top View V IN 2 V IN 3 V 4 Top View DIP 8 7 V 6 SOL-6 Surface Mount ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. V IN V IN V Feedback ORDERING INFORMATION MODEL PACKAGE TEMPERATURE RANGE AP 8-Pin Plastic DIP 4 C to 8 C BP 8-Pin Plastic DIP 4 C to 8 C AU SOL-6 Surface-Mount 4 C to 8 C BU SOL-6 Surface-Mount 4 C to 8 C V 6 7 PACKAGE INFORMATION 8 ABSOLUTE MAXIMUM RATINGS Supply Voltage... ±8V Input Voltage Range... (V).7V to (V) V Output Short-Circuit (to ground)... Continuous Operating Temperature... 4 C to 2 C Storage Temperature... 4 C to 2 C Junction Temperature... C Lead Temperature (soldering, s)... 3 C 9 PACKAGE DRAWING MODEL PACKAGE NUMBER () AP 8-Pin Plastic DIP 6 BP 8-Pin Plastic DIP 6 AU 6-Pin Surface Mount 2 BU 6-Pin Surface Mount 2 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. 3

4 TYPICAL PERFORMAE CURVES T A = 2 C, V S = ±V unless otherwise noted. k GAIN vs FREQUEY 2 COMMON-MODE REJECTION vs FREQUEY Gain (V/V) k G = k G = G = G =. k k k M M Common-Mode Rejection (db) 8 G = k 6 G = 4 G = 2 G = k k k M Common-Mode Voltage (V) INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE Limited by A Output Swing Limited by A 2 Output Swing V D/2 V D/2 V CM A 3 Output Swing Limit (Any Gain) A 3 Output Swing Limit Output Voltage (V) Limited by A 2 Output Swing Limited by A Output Swing Power Supply Rejection (db) POWER SUPPLY REJECTION vs FREQUEY k k k M G = k G = G = G = k INPUT-REFERRED NOISE VOLTAGE vs FREQUEY SETTLING TIME vs GAIN Input-erred Noise Voltage (nv/ Hz) G = G = G =, k Settling Time (µs).%.% k k Gain (V/V) 4

5 TYPICAL PERFORMAE CURVES (CONT) T A = 2 C, V S = ±V unless otherwise noted. 7 OFFSET VOLTAGE WARM-UP vs TIME 3 n INPUT BIAS CURRENT vs TEMPERATURE I b erred-to-input S Change (µv) 2 2 G G = 2 2 erred-to-input S Change (µv) Input Bias Current (A) n p p p.p I OS Time From Power Supply Turn-On (Minutes) 3.p Temperature ( C) Input Bias Current (A) m m µ µ.7v INPUT BIAS CURRENT vs DIFFERENTIAL INPUT VOLTAGE G = G = G = G = k p G = G = p G = k G =.7V p 2 2 Differential Overload Voltage (V) NOTE: One input grounded. Input Bias Current (A) m m µ µ p INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE.7V Common-Mode Voltage (V).7V p MAXIMUM OUTPUT VOLTAGE SWING vs FREQUEY OUTPUT CURRENT LIMIT vs TEMPERATURE Peak-to-Peak Amplitude (V) 2 2 Short-Circuit Current (ma) I CL I CL k k k M M Temperature ( C)

6 TYPICAL PERFORMAE CURVES (CONT) T A = 2 C, V S = ±V unless otherwise noted. Quiescent Current (ma) QUIESCENT CURRENT vs TEMPERATURE THD N (%)... G = k G = G = TOTAL HARMONIC DISTORTION NOISE vs FREQUEY = 3Vrms, R L = 2kΩ Measurement BW = 8kHz Single-Ended Drive G = Differential Drive G = Temperature ( C). 2 k k 2k LARGE SIGNAL RESPONSE, G = SMALL SIGNAL RESPONSE, G =.. 2 Time (µs) 2 Time (µs) LARGE SIGNAL RESPONSE, G = SMALL SIGNAL RESPONSE, G =.. 2 Time (µs) 2 Time (µs) 6

7 APPLICATION INFORMATION Figure shows the basic connections required for operation of the. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference () terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 2Ω in series with the pin will cause a typical device with 9dB CMR to degrade to approximately 8dB CMR (G = ). SETTING THE GAIN Gain of the is set by connecting a single external resistor, : G = kω () Commonly used gains and resistor values are shown in Figure. The kω term in equation comes from the sum of the two internal feedback resistors. These are on-chip metal film resistors which are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the. The stability and temperature drift of the external gain setting resistor,, also affects gain. s contribution to gain accuracy and drift can be directly inferred from the gain equation (). Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance, which will contribute additional gain error (possibly an unstable gain error) in gains of approximately or greater. DYNAMIC PERFORMAE The typical performance curve Gain vs Frequency shows that the achieves wide bandwidth over a wide range of gain. This is due to the current-feedback topology of the. Settling time also remains excellent over wide gains. V.µF Pin numbers are for DIP package. 7 2 A kω kω A 3 6 = G ( ) G = kω 8 Load 3 A 2 kω kω 4.µF DESIRED NEAREST % GAIN (Ω) (Ω) No Connection No Connection 2.k 49.9k 2.k 2.4k.6k.62k k 2.6k.2k.2k V Also drawn in simplified form: FIGURE. Basic Connections 7

8 The exhibits approximately 6dB rise in gain at 2MHz in unity gain. This is a result of its current-feedback topology and is not an indication of instability. Unlike an op amp with poor phase margin, the rise in response is a predictable 6dB/octave due to a response zero. A simple pole at 7kHz or lower will produce a flat passband response (see Input Filtering). The provides excellent rejection of high frequency common-mode signals. The typical performance curve, Common-Mode Rejection vs Frequency shows this behavior. If the inputs are not properly balanced, however, common-mode signals can be converted to differential signals. Run the and connections directly adjacent each other, from the source signal all the way to the input pins. If possible use a ground plane under both input traces. Avoid running other potentially noisy lines near the inputs. NOISE AND ACCURACY PERFORMAE The s FET input circuitry provides low input bias current and high speed. It achieves lower noise and higher accuracy with high impedance sources. With source impedances of 2kΩ to kω the INA4 may provide lower offset voltage and drift. For very low source impedance ( kω), the INA3 may provide improved accuracy and lower noise. INPUT BIAS CURRENT RETURN PATH The input impedance of the is extremely high approximately 2 Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is typically less than pa. High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current if the is to operate properly. Figure 3 shows various provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the common-mode range of the and the input amplifiers will saturate. If the differential source resistance is low, the bias current return path can be connected to one input (see the thermocouple example in Figure 3). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better high-frequency common-mode rejection. Crystal or Ceramic Transducer OFFSET TRIMMING The is laser trimmed for low offset voltage and drift. Most applications require no external offset adjustment. Figure 2 shows an optional circuit for trimming the output offset voltage. The voltage applied to terminal is summed at the output. Low impedance must be maintained at this node to assure good common-mode rejection. The op amp shown maintains low output impedance at high frequency. Trim circuits with higher source impedance should be buffered with an op amp follower circuit to assure low impedance on the pin. Thermocouple MΩ kω MΩ V µa /2 REF2 Center-tap provides bias current return. OPA77 ±mv Adjustment Range NOTE: () For wider trim range required in high gains, scale resistor values larger kω () Ω () Ω () FIGURE 2. Optional Trimming of Output Offset Voltage. V µa /2 REF2 FIGURE 3. Providing an Input Common-Mode Current Path. INPUT COMMON-MODE RANGE The linear common-mode range of the input op amps of the is approximately ±2V (or 3V from the power supplies). As the output voltage increases, however, the linear input range will be limited by the output voltage swing of the input amplifiers, A and A 2. The common-mode range is related to the output voltage of the complete amplifier see performance curve Input Common-Mode Range vs Output Voltage. 8

9 A combination of common-mode and differential input voltage can cause the output of A or A 2 to saturate. Figure 4 shows the output voltage swing of A and A 2 expressed in terms of a common-mode and differential input voltages. For applications where input common-mode range must be maximized, limit the output voltage swing by connecting the in a lower gain (see performance curve Input Common-Mode Voltage Range vs Output Voltage ). If necessary, add gain after the to increase the voltage swing. Input-overload often produces an output voltage that appears normal. For example, consider an input voltage of 4V on one input and V on the other input will obviously exceed the linear common-mode range of both input amplifiers. Since both input amplifiers are saturated to the nearly the same output voltage limit, the difference voltage measured by the output amplifier will be near zero. The output of the will be near V even though both inputs are overloaded. INPUT PROTECTION Inputs of the are protected for input voltages from.7v below the negative supply to V above the positive power supply voltages. If the input current is limited to less than ma, clamp diodes are not required; internal junctions will clamp the input voltage to safe levels. If the input source can supply more than ma, use external clamp diodes as shown in Figure. The source current can be limited with series resistors R and R 2 as shown. Resistor values greater than kω will contribute noise to the circuit. A diode formed with a 2N47A transistor as shown in Figure assures low leakage. Common signal diodes such as the N448 may have leakage currents far greater than the input bias current of the and are usually sensitive to light. INPUT FILTERING The s FET input allows use of an R/C input filter without creating large offsets due to input bias current. Figure 6 shows proper implementation of this input filter to preserve the s excellent high frequency commonmode rejection. Mismatch of the common-mode input capacitance (C and C 2 ), either from stray capacitance or R R 2 D D 3 V V FIGURE. Input Protection Voltage Clamp. D 2 D 4 Diodes: = 2N47A pa Leakage V CM G V D 2 V V D2 A kω kω G = kω A 3 = G V D V D2 V CM A 2 kω kω V CM G V D 2 V FIGURE 4. Voltage Swing of A and A 2. 9

10 mismatched values, causes a high frequency common-mode signal to be converted to a differential signal. This degrades common-mode rejection. The differential input capacitor, C 3, reduces the bandwidth and mitigates the effects of mismatch in C and C 2. Make C 3 much larger than C and C 2. If properly matched, C and C 2 also improve CMR. Feedback Surface-mount package version only. C pf OUTPUT VOLTAGE SENSE (SOL-6 Package Only) The surface-mount version of the has a separate output sense feedback connection (pin 2). Pin 2 must be connected, usually to the output terminal, pin, for proper operation. (This connection is made internally on the DIP version of the.) The output feedback connection can be used to sense the output voltage directly at the load for best accuracy. Figure 8 shows how to drive a load through series interconnection resistance. Remotely located feedback paths may cause instability. This can be generally be eliminated with a high frequency feedback path through C. FIGURE 8. Remote Load and Ground Sensing. C C 2 Equal resistance here preserves good common-mode rejection. Load R C f 3dB = 4πR C 3 C 2 R R 2 f c = NOTE: To preserve good low frequency CMR, make R = R 2 and C = C 2. 2πR C R 2 C 3 FIGURE 9. High-Pass Input Filter. C 2 R = R 2 C = C 2 C 3 C ±6V to ±8V Isolated Power V V FIGURE 6. Input Low-Pass Filter. ±V V ISO22 Bridge G = Ω Isolated Common FIGURE. Galvanically Isolated Instrumentation Amplifier. FIGURE 7. Bridge Transducer Amplifier.

11 OPA77 C.µF R MΩ R kω C nf R 2 OPA62 f 3dB = 2πR C =.9Hz Make G where G = k Load V I IN L = G R 2 FIGURE. AC-Coupled Instrumentation Amplifier. FIGURE 2. Voltage Controlled Current Source. 22.kΩ 22.kΩ Ω NOTE: Driving the shield minimizes CMR degradation due to unequally distributed capacitance on the input line. The shield is driven at approximately V below the common-mode input voltage. Ω OPA62 For G = = Ω // 2(22.kΩ) effective = Ω FIGURE 3. Shield Driver Circuit. V Channel Channel 8 MPC8 MUX ADS74 2 Bits Out FIGURE 4. Multiplexed-Input Data Acquisition System.