Single Supply, Low Power, Triple Video Amplifier AD8013

Transcription

1 a FEATURES Three Video Amplifiers in One Package Drives Large Capacitive Load Excellent Video Specifications (R L = 5 ) Gain Flatness. db to MHz.% Differential Gain Error. Differential Phase Error Low Power Operates on Single +5 V to + V Power Supplies ma/amplifier Max Power Supply Current High Speed MHz Unity Gain Bandwidth ( db) Fast Settling Time of ns (.%) V/ s Slew Rate High Speed Disable Function per Channel Turn-Off Time ns Easy to Use 95 ma Short Circuit Current Output Swing to Within V of Rails APPLICATIONS LCD Displays Video Line Driver Broadcast and Professional Video Computer Video Plug-In Boards Consumer Video RGB Amplifier in Component Systems PRODUCT DESCRIPTION The AD is a low power, single supply, triple video amplifier. Each of the three amplifiers has ma of output current, and is optimized for driving one back terminated video load (5 Ω) each. Each amplifier is a current feedback amplifier and features gain flatness of. db to MHz while offering.. R L = 5Ω Single Supply, Low Power, Triple Video Amplifier AD PIN CONFIGURATION -Pin DIP & SOIC Package DISABLE DISABLE DISABLE +V S +IN 5 IN OUT 7 AD OUT IN +IN V S +IN 9 IN OUT differential gain and phase error of.% and.. This makes the AD ideal for broadcast and professional video electronics. The AD offers low power of ma per amplifier max and runs on a single +5 V to + V power supply. The outputs of each amplifier swing to within one volt of either supply rail to easily accommodate video signals. The AD is unique among current feedback op amps by virtue of its large capacitive load drive. Each op amp is capable of driving large capacitive loads while still achieving rapid settling time. For instance it can settle in ns driving a resistive load, and achieves ns (.%) settling while driving pf. The outstanding bandwidth of MHz along with V/µs of slew rate make the AD useful in many general purpose high speed applications where a single +5 V or dual power supplies up to ±.5 V are required. Furthermore the AD s high speed disable function can be used to power down the amplifier or to put the output in a high impedance state. This can then be used in video multiplexing applications. The AD is available in the industrial temperature range of C to +5 C. NORMALIZED GAIN db.... V S = ± 5V 9 5mV 5ns.5 % M M M 5V Fine-Scale Gain Flatness vs. Frequency,, R L = 5 Ω Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Channel Switching Characteristics for a : Mux Analog Devices, Inc., 995 One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7/9-7 Fax: 7/-7

2 AD SPECIFICATIONS T A = +5 C, R LOAD = 5, unless otherwise noted) Model ADA Conditions V S Min Typ Max Units DYNAMIC PERFORMANCE Bandwidth ( db) No Peaking, +5 V 5 MHz No Peaking, ±5 V MHz Bandwidth (. db) No Peaking, +5 V 5 MHz No Peaking, ±5 V MHz Slew Rate V Step +5 V V/µs V Step ±5 V V/µs Settling Time to.% V to + V ±5 V ns.5 V Step, C LOAD = pf ± V ns R LOAD > kω, R FB = kω NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion f C = 5 MHz, R L = k ±5 V 7 dbc f C = 5 MHz, R L = 5 Ω ±5 V dbc Input Voltage Noise f = khz +5 V, ±5 V.5 nv/ Hz Input Current Noise f = khz ( I IN ) +5 V, ±5 V pa/ Hz Differential Gain (R L = 5 Ω) f =.5 MHz, +5 V.5 % ±5 V..5 % Differential Phase (R L = 5 Ω) f =.5 MHz, +5 V. Degrees ±5 V.. Degrees DC PERFORMANCE Input Offset Voltage T MIN to T MAX +5 V, ±5 V 5 mv Offset Drift 7 µv/ C Input Bias Current ( ) +5 V, ±5 V µa Input Bias Current (+) T MIN to T MAX +5 V, ±5 V 5 µa Open-Loop Transresistance +5 V 5 kω T MIN to T MAX 55 kω ±5 V k. M Ω T MIN to T MAX 5 kω INPUT CHARACTERISTICS Input Resistance +Input ±5 V kω Input ±5 V 5 Ω Input Capacitance ±5 V pf Input Common-Mode Voltage Range ±5 V. ±V +5 V.. +V Common-Mode Rejection Ratio Input Offset Voltage +5 V 5 5 db Input Offset Voltage ±5 V 5 5 db Input Current +5 V, ±5 V.. µa/v +Input Current +5 V, ±5 V 5 7 µa/v OUTPUT CHARACTERISTICS Output Voltage Swing R L = kω V OL V EE.. V V CC V OH.. V R L = 5 Ω V OL V EE.. V V CC V OH.. V Output Current +5 V ma ±5 V 5 ma Short-Circuit Current ±5 V 95 ma Capacitive Load Drive ±5 V pf MATCHING CHARACTERISTICS Dynamic Crosstalk, f = 5 MHz +5 V, ±5 V 7 db Gain Flatness Match f = MHz ±5 V. db DC Input Offset Voltage +5 V, ±5 V. mv Input Bias Current +5 V, ±5 V. µa

3 Model AD ADA Conditions V S Min Typ Max Units POWER SUPPLY Operating Range Single Supply +. + V Dual Supply ±. ±.5 V Quiescent Current/Amplifier +5 V..5 ma ±5 V.. ma ±.5 V.5 ma Quiescent Current/Amplifier Power Down +5 V.5.5 ma ±5 V.. ma Power Supply Rejection Ratio Input Offset Voltage V S = ±.5 V to ±5 V 7 7 db Input Current +5 V, ±5 V.. µa/v +Input Current +5 V, ±5 V.7. µa/v DISABLE CHARACTERISTICS Off Isolation f = MHz +5 V, ±5 V 7 db Off Output Impedance G = + +5 V, ±5 V pf Turn-On Time 5 ns Turn-Off Time ns Switching Threshold V S + xv...9 V NOTES The test circuit for differential gain and phase measurements on a +5 V supply is ac coupled. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Supply Voltage V Total Internal Power Dissipation Plastic (N) Watts (Observe Derating Curves) Small Outline (R)..... Watts (Observe Derating Curves) Input Voltage (Common Mode).. Lower of ±V S or ±.5 V Differential Input Voltage Output ± V (Clamped) Output Voltage Limit Maximum Lower of (+ V from V S ) or (+V S ) Minimum Higher of (.5 V from +V S ) or ( V S ) Output Short Circuit Duration Observe Power Derating Curves Storage Temperature Range N and R Package C to +5 C Operating Temperature Range ADA C to +5 C Lead Temperature Range (Soldering sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for device in free air: -Pin Plastic DIP Package: θ JA = 75 C/Watt -Pin SOIC Package: θ JA = C/Watt ORDERING GUIDE Temperature Package Package Model Range Description Options ADAN C to +5 C -Pin Plastic DIP N- ADAR- C to +5 C -Pin Plastic SOIC R- ADAR--REEL C to +5 C -Pin Plastic SOIC R- ADAR--REEL7 C to +5 C -Pin Plastic SOIC R- ADACHIPS C to +5 C Die Form Maximum Power Dissipation The maximum power that can be safely dissipated by the AD is limited by the associated rise in junction temperature. The maximum safe junction temperature for the plastic encapsulated parts is determined by the glass transition temperature of the plastic, about 5 C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 75 C for an extended period can result in device failure. While the AD is internally short circuit protected, this may not be enough to guarantee that the maximum junction temperature is not exceeded under all conditions. To ensure proper operation, it is important to observe the derating curves. It must also be noted that in (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may result in a significant power dissipation in the input stage. This power must be included when computing the junction temperature rise due to total internal power. MAXIMUM POWER DISSIPATION Watts PIN SOIC T J = +5 C -PIN DIP PACKAGE AMBIENT TEMPERATURE C Maximum Power Dissipation vs. Ambient Temperature

4 AD METALIZATION PHOTO Contact factory for latest dimensions. Dimensions shown in inches and (mm). +IN 5 +v s DISABLE IN DISABLE OUT 7 DISABLE. (.) OUT OUT IN 9 +IN.7 (.) V +IN S IN CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE COMMON-MODE VOLTAGE RANGE ± Volts 5 OUTPUT VOLTAGE SWING V p-p NO LOAD R L = 5Ω 5 7 SUPPLY VOLTAGE ± Volts 5 7 SUPPLY VOLTAGE ± Volts Figure. Input Common-Mode Voltage Range vs. Supply Voltage Figure. Output Voltage Swing vs. Supply Voltage

5 AD OUTPUT VOLTAGE SWING V p-p INPUT BIAS CURRENT µa I B +I B k k LOAD RESISTANCE Ω JUNCTION TEMPERATURE C Figure. Output Voltage Swing vs. Load Resistance Figure. Input Bias Current vs. Junction Temperature SUPPLY CURRENT ma 9 7 V S = ± 5V INPUT OFFSET VOLTAGE mv JUNCTION TEMPERATURE C JUNCTION TEMPERATURE C Figure. Total Supply Current vs. Junction Temperature Figure 7. Input Offset Voltage vs. Junction Temperature V S = ± 5V SUPPLY CURRENT ma 9 T A = +5 C SHORT CIRCUIT CURRENT ma 9 SINK SOURCE SUPPLY VOLTAGE ± Volts JUNCTION TEMPERATURE C Figure 5. Supply Current vs. Supply Voltage Figure. Short Circuit Current vs. Junction Temperature 5

6 AD k 7 CLOSED-LOOP OUTPUT RESISTANCE Ω. COMMON-MODE REJECTION db 5 V CM R R R R. k M M M k M M M Figure 9. Closed-Loop Output Resistance vs. Frequency Figure. Common-Mode Rejection vs. Frequency k 7 OUTPUT RESISTANCE Ω k k POWER SUPPLY REJECTION db 5 PSR +PSR M M M k M M M Figure. Output Resistance vs. Frequency, Disabled State Figure. Power Supply Rejection Ratio vs. Frequency VOLTAGE NOISE nv/ Hz k NONINVERTING I INVERTING I k CURRENT NOISE pa/ Hz TRANSIMPEDANCE db R L = k PHASE Degrees V NOISE k k k M k k M M M Figure. Input Current and Voltage Noise vs. Frequency Figure. Open-Loop Transimpedance vs. Frequency (Relative to Ω)

7 AD HARMONIC DISTORTION dbc V O = V p-p nd R L = 5Ω nd R L = kω rd R L = kω CLOSED-LOOP GAIN (NORMALIZED) db + PHASE GAIN G = + R L = 5Ω 9 7 PHASE SHIFT Degrees k k rd R L = 5Ω k M M M 5 M M M Figure 5. Harmonic Distortion vs. Frequency Figure. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = 5 Ω R L = 5Ω G = + G = + SLEW RATE V/µs G = G = + SLEW RATE V/µs G = G = OUTPUT STEP SIZE V p-p SUPPLY VOLTAGE ±Volts Figure. Slew Rate vs. Output Step Size Figure 9. Maximum Slew Rate vs. Supply Voltage V ns 5mV ns V IN 9 V IN 9 % % V 5mV Figure 7. Large Signal Pulse Response, Gain = +, (R F = kω, R L = 5 Ω, V S = ±5 V) Figure. Small Signal Pulse Response, Gain = +, (R F = kω, R L = 5 Ω, V S = ±5 V) 7

8 AD 5mV ns V ns V IN 9 V IN 9 % % 5mV V Figure. Large Signal Pulse Response, Gain = +, R F = Ω, R L = 5 Ω, V S = ±5 V) Figure. Large Signal Pulse Response, Gain =, (R F = 9 Ω, R L = 5 Ω, V S = ±5 V) CLOSED-LOOP GAIN (NORMALIZED) db + PHASE GAIN G = + R L = 5Ω 9 7 PHASE SHIFT Degrees CLOSED-LOOP GAIN (NORMALIZED) db + PHASE GAIN G = R L = 5Ω 9 9 PHASE SHIFT Degrees 5 5 M M M M M M Figure. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = 5 Ω Figure 5. Closed-Loop Gain and Phase vs. Frequency, G =, R L = 5 Ω 5mV ns 5mV ns V IN 9 V IN 9 % % 5mV 5mV Figure. Small Signal Pulse Response, Gain = +, (R F = Ω, R L = 5 Ω, V S = ±5 V) Figure. Small Signal Pulse Response, Gain =, (R F = 9 Ω, R L = 5 Ω, V S = ±5 V)

9 AD CLOSED-LOOP GAIN (NORMALIZED) db + 5 M PHASE GAIN M M G = R L = 5Ω Figure 7. Closed-Loop Gain and Phase vs. Frequency, G =, R L = 5 Ω General The AD is a wide bandwidth, triple video amplifier that offers a high level of performance on less than. ma per amplifier of quiescent supply current. The AD uses a proprietary enhancement of a conventional current feedback architecture, and achieves bandwidth in excess of MHz with low differential gain and phase errors, making it an extremely efficient video amplifier. The AD s wide phase margin coupled with a high output short circuit current make it an excellent choice when driving any capacitive load. High open-loop gain and low inverting input bias current enable it to be used with large values of feedback resistor with very low closed-loop gain errors. It is designed to offer outstanding functionality and performance at closed-loop inverting or noninverting gains of one or greater. Choice of Feedback & Gain Resistors Because it is a current feedback amplifier, the closed-loop bandwidth of the AD may be customized using different values of the feedback resistor. Table I shows typical bandwidths at different supply voltages for some useful closed-loop gains when driving a load of 5 Ω. The choice of feedback resistor is not critical unless it is important to maintain the widest, flattest frequency response. The resistors recommended in the table are those (chip resistors) that will result in the widest. db bandwidth without peaking. In applications requiring the best control of bandwidth, % resistors are adequate. Package parasitics vary between the -pin plastic DIP and the -pin plastic SOIC, and may result in a slight difference in the value of the feedback resistor used to achieve the optimum dynamic performance. Resistor values and widest bandwidth figures are shown in parenthesis for the SOIC where they differ from those of the DIP. Wider bandwidths than those in the table can be attained by reducing the magnitude of the feedback resistor (at the expense of increased peaking), while peaking can be reduced by increasing the magnitude of the feedback resistor. Increasing the feedback resistor is especially useful when driving large capacitive loads as it will increase the phase margin of the closed-loop circuit. (Refer to the section on driving capacitive loads for more information.) 9 9 PHASE SHIFT Degrees To estimate the db bandwidth for closed-loop gains of or greater, for feedback resistors not listed in the following table, the following single pole model for the AD may be used: G ACL + SC T (R F + Gn rin) where: C T = transcapacitance pf R F = feedback resistor G = ideal closed loop gain Gn = + R F R = noise gain G rin = inverting input resistance 5 Ω ACL = closed loop gain The db bandwidth is determined from this model as: f π C T (R F + Gn rin) This model will predict db bandwidth to within about % to 5% of the correct value when the load is 5 Ω and V S = ±5 V. For lower supply voltages there will be a slight decrease in bandwidth. The model is not accurate enough to predict either the phase behavior or the frequency response peaking of the AD. It should be noted that the bandwidth is affected by attenuation due to the finite input resistance. Also, the open-loop output resistance of about Ω reduces the bandwidth somewhat when driving load resistors less than about 5 Ω. (Bandwidths will be about % greater for load resistances above a few hundred ohms.) Table I. db Bandwidth vs. Closed-Loop Gain and Feedback Resistor, R L = 5 Ω (SOIC) V S Volts Gain R F Ohms BW MHz ± (9) 5 (5) + 9 (5) () (9) () (5) () 99 Driving Capacitive Loads When used in combination with the appropriate feedback resistor, the AD will drive any load capacitance without oscillation. The general rule for current feedback amplifiers is that the higher the load capacitance, the higher the feedback resistor required for stable operation. Due to the high open-loop transresistance and low inverting input current of the AD, the use of a large feedback resistor does not result in large closedloop gain errors. Additionally, its high output short circuit current makes possible rapid voltage slewing on large load capacitors. For the best combination of wide bandwidth and clean pulse response, a small output series resistor is also recommended. Table II contains values of feedback and series resistors which result in the best pulse responses. Figure 9 shows the AD driving a pf capacitor through a large voltage step with virtually no overshoot. (In this case, the large and small signal pulse responses are quite similar in appearance.) 9

10 AD V IN R G R T R F +V S.µF.µF AD.µF.µF V S 5Ω Figure. Circuit for Driving a Capacitive Load Table II. Recommended Feedback and Series Resistors vs. Capacitive Load and Gain R S Ohms C L pf R F Ohms G = G k k 5 5 k 5 k 5 5 k k 5 5 V IN 9 % 5mV V R S 5ns Figure 9. Pulse Response Driving a Large Load Capacitor. C L = pf,, R F = k, R S = 5 Ω Overload Recovery The three important overload conditions are: input commonmode voltage overdrive, output voltage overdrive, and input current overdrive. When configured for a low closed-loop gain, the amplifier will quickly recover from an input commonmode voltage overdrive; typically in under 5 ns. When configured for a higher gain, and overloaded at the output, the recovery time will also be short. For example, in a gain of +, with 5% overdrive, the recovery time of the AD is about ns (see Figure ). For higher overdrive, the response is somewhat slower. For db overdrive, (in a gain of +), the recovery time is about 5 ns. V IN 9 5mV 5ns C L V O As noted in the warning under Maximum Power Dissipation, a high level of input overdrive in a high noninverting gain circuit can result in a large current flow in the input stage. Though this current is internally limited to about ma, its effect on the total power dissipation may be significant. High Performance Video Line Driver At a gain of +, the AD makes an excellent driver for a back terminated 75 Ω video line (Figures,, and ). Low differential gain and phase errors and wide. db bandwidth can be realized. The low gain and group delay matching errors ensure excellent performance in RGB systems. Figures and 5 show the worst case matching. V IN CABLE R G R F +V S AD.µF V S.µF CABLE Figure. A Video Line Driver Operating at a Gain of + (R F = R G from Table I) CLOSED-LOOP GAIN (NORMALIZED) db + 5 M PHASE GAIN M M R L = 5Ω 9 7 Figure. Closed-Loop Gain & Phase vs. Frequency for the Line Driver NORMALIZED GAIN db R L = 5Ω PHASE SHIFT Degrees % M M M 5V Figure. 5% Overload Recovery, G = + (R F = Ω, R L = kω, V S = ±5 V) Figure. Fine-Scale Gain Flatness vs. Frequency,, R L = 5 Ω

11 AD.5 V I +5V. R L = 5Ω k GAIN MATCHING db M M M Figure. Closed-Loop Gain Matching vs. Frequency GROUP DELAY ns k R L = 5Ω R L = 5Ω DELAY DELAY MATCHING M M M Figure 5. Group Delay and Group Delay Matching vs. Frequency,, R L = 5 Ω Disable Mode Operation Pulling the voltage on any one of the Disable pins about. V up from the negative supply will put the corresponding amplifier into a disabled, powered down, state. In this condition, the amplifier s quiescent current drops to about. ma, its output becomes a high impedance, and there is a high level of isolation from input to output. In the case of the gain of two line driver for example, the impedance at the output node will be about the same as for a. kω resistor (the feedback plus gain resistors) in parallel with a pf capacitor and the input to output isolation will be about db at 5 MHz. Leaving the Disable pin disconnected (floating) will leave the corresponding amplifier operational, in the enabled state. The input impedance of the disable pin is about kω in parallel with a few picofarads. When driven to V, with the negative supply at 5 V, about µa flows into the disable pin. When the disable pins are driven by complementary output CMOS logic, on a single 5 V supply, the disable and enable times are about 5 ns. When operated on dual supplies, level shifting will be required from standard logic outputs to the Disable pins. Figure shows one possible method which results in a negligible increase in switching time. k k 5V TO DISABLE PIN V I HIGH => AMPLIFIER ENABLED V I LOW => AMPLIFIER DISABLED Figure. Level Shifting to Drive Disable Pins on Dual Supplies The AD s input stages include protection from the large differential input voltages that may be applied when disabled. Internal clamps limit this voltage to about ± V. The high input to output isolation will be maintained for voltages below this limit. : Video Multiplexer Wiring the amplifier outputs together will form a : mux with excellent switching behavior. Figure 7 shows a recommended configuration which results in. db bandwidth of 5 MHz and OFF channel isolation of db at MHz on ±5 V supplies. The time to switch between channels is about 5 ns. Switching time is virtually unaffected by signal level. V IN DISABLE V IN DISABLE V IN DISABLE 5Ω 5Ω 5Ω 5Ω 5 +V S 5Ω 9 5Ω V S 7 Ω Ω Ω CABLE Figure 7. A Fast Switching : Video Mux (Supply Bypassing Not Shown) 9 % 5mV 5V ns Figure. Channel Switching Characteristic for the : Mux

12 AD : Video Multiplexer Configuring two amplifiers as unity gain followers and using the third to set the gain results in a high performance : mux (Figures 9 and ). This circuit takes advantage of the very low crosstalk between Channels and to achieve the OFF channel isolation shown in Figure. This circuit can achieve differential gain and phase of.% and.7 respectively. V IN A V IN B 9 DISABLE DISABLE R kω R Ω R Ω R kω 5 R 5Ω 7 R5 5Ω Figure 9. : Mux with High Isolation and Low Differential Gain and Phase Errors The AD can be used to build a circuit for switching between any two arbitrary gains while maintaining a constant input impedance. The example of Figure shows a circuit for switching between a noninverting gain of and an inverting gain of. The total time for channel switching and output voltage settling is about ns. V IN Ω 5Ω k k k 9Ω 5Ω 5 9 9Ω 5Ω +5V 7 DIS DIS 5V 5Ω Figure. Circuit to Switch Between Gains of and + C /95 CLOSED-LOOP GAIN db 5 7 M GAIN FEEDTHROUGH M M 5 7 FEEDTHROUGH db 9 % 5mV 5mV ns 5V Figure. Switching Characteristic for Circuit of Figure Figure. : Mux ON Channel Gain and Mux OFF Channel Feedthrough vs. Frequency Gain Switching. (.).5 (.9). (.55). (.5) -Lead Plastic DIP (N-).795 (.9).75 (.) 7. (7.). (.). (.5) PIN.5 (.). (5.) MAX.. (.5) BSC.7 (.77).5 (.5) (.) MIN SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm)..5 (.5). (7.).95 (.95).5 (.9).5 (.). (.).57 (.).97 (.).9 (.5). (.) SEATING PLANE -Lead SOIC (R-). (.75).7 (.55) 7 PIN.5 (.7) BSC. (.). (5.). (.75).5 (.5).9 (.9). (.5).9 (.5).75 (.9).9 (.5).99 (.5) x 5.5 (.7). (.) PRINTED IN U.S.A.

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