Fast-Settling FET-Input INSTRUMENTATION AMPLIFIER

Transcription

1 INA Fast-Settling FET-Input INSTRUMENTATION AMPLIFIER FEATURES LOW BIAS CURRENT: pa max FAST SETTLING: 4µs to.% HIGH CMR: db min; db at khz INTERNAL GAINS:,,,, VERY LOW GAIN DRIFT: to ppm/ C LOW OFFSET DRIFT: µv/ C LOW COST PINOUT SIMILAR TO AD4 AND AD4 APPLICATIONS MULTIPLEXED INPUT DATA ACQUISITION SYSTEM FAST DIFFERENTIAL PULSE AMPLIFIER HIGH SPEED GAIN BLOCK AMPLIFICATION OF HIGH IMPEDANCE SOURCES DESCRIPTION The INA is a versatile monolithic FET-input instrumentation amplifier. Its current-feedback circuit topology and laser trimmed input stage provide excellent dynamic performance and accuracy. The INA settles in 4µs to.%, making it ideal for high speed or multiplexed-input data acquisition systems. () In X X X X FET Input 4.44kΩ 44Ω Ω.Ω A kω kω INA kω kω A Sense Output Internal gain-set resistors are provided for gains of,,,, and V/V. Inputs are protected for differential and common-mode voltages up to ±V CC. Its very high input impedance and low input bias current make the INA ideal for applications requiring input filters or input protection circuitry. R G +In FET Input A kω kω 4 4 Ref The INA is available in -pin plastic and ceramic DIPs, and in the SOL- surface-mount package. Military, industrial and commercial temperature range grades are available. Input Offset Adjust +V CC V CC NOTE: () Connect to R G for desired gain. Output Offset Adjust International Airport Industrial Park Mailing Address: PO Box 4 Tucson, AZ 4 Street Address: S. Tucson Blvd. Tucson, AZ Tel: () 4- Twx: -- Cable: BBRCORP Telex: -4 FAX: () - Immediate Product Info: () 4- Burr-Brown Corporation PDS-4E Printed in U.S.A. September,

2 SPECIFICATIONS ELECTRICAL At + C, ±V CC = VDC, and R L = kω, unless otherwise specified. INAAG INABG, SG INAKP, KU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS GAIN Range of Gain * * * * V/V Gain Equation () * G = + [4k/(R G + Ω)] * V/V Gain Error, DC: G =..4 *. * * % G =.... * * % G =.... * * % G = * * % G =... * * % Gain Temp. Coefficient: G = ± ± * ± * ppm/ C G = ±4 ± ± ± * ppm/ C G = ± ±4 ± ± * ppm/ C G = ± ± ± ± * ppm/ C G = ± ± ± ± * ppm/ C Nonlinearity, DC: G = ±. ±. ±. ±. * * % of FS G = ±. ±. ±. ±. * * % of FS G = ±.4 ±. ±. ±. * * % of FS G = ±. ±. ±. ±. * * % of FS G = ±. ±.4 ±. ±. * * % of FS OUTPUT Voltage, R L = kω Over Temperature ± ±. * * * * V Current Over Temperature ± ± * * * * ma Short-Circuit Current ± * * ma Capacitive Load Stability * * pf INPUT OFFSET VOLTAGE () Initial Offset: G, P ±( + ±( + ±( + ±( + * * µv /G) /G) /G) /G) U ±( + ±( + µv /G) /G) vs Temperature ±( + ±( + ±( + ±( + * µv/ C /G) /G) /G) /G) vs Supply V CC = ±V to ±V ±(4 + ±( + ±( + ±( + * * µv/v /G) /G) /G) /G) BIAS CURRENT Initial Bias Current Each Input * * pa Initial Offset Current * * pa Impedance: Differential x * * Ω pf Common-Mode x * * Ω pf VOLTAGE RANGE V IN Diff. = V () Range, Linear Response ± ± * * V CMR with kω Source Imbalance: G = DC * * db G = DC 4 * * db G = DC * * db G = DC * * db G = DC * * db INPUT NOISE (4) Voltage, f O = khz * * nv/ Hz f B =.Hz to Hz * * µvp-p Current, f O = khz. * * fa/ Hz OUTPUT NOISE (4) Voltage, f O = khz * * nv/ Hz f B =.Hz to Hz * * µvp-p DYNAMIC RESPONSE Small Signal: G = db. * * MHz G =. * * MHz G = 4 * * khz G = 4 * * khz G = * * khz Full Power V OUT = ±V, G = to * * * * khz Slew Rate G = to * * * * V/µs Settling Time:.%, G = V O = V Step 4 * * µs G = * * µs G = * * µs G = * * µs G = * * µs INA

3 SPECIFICATIONS (CONT) ELECTRICAL At + C, ±V CC VDC, and R L = KΩ, unless otherwise specified. INAAG INABG, SG INAKP, KU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DYNAMIC RESPONSE (CONT) Settling Time:.%,G = V O = V Step. * * * µs G =. * * * µs G = 4. * * * µs G =. * * * µs G = * * * µs Recovery () % Overdrive * * µs POWER SUPPLY Rated Voltage ± * * V Voltage Range ± ± * * * * V Quiescent Current V O = V ± ±4. * * * * ma TEMPERATURE RANGE Specification: A, B, K + * * + C S + C Operation + * * + C Storage + * * 4 + C θ JA * * C/W * Same as INAAG. NOTES: () Gains other than,,,, and can be set by adding an external resistor, R G, between pin and pins, and. Gain accuracy is a function of R G and the internal resistors which have a ±% tolerance with ppm/ C drift. () Adjustable to zero. () For differential input voltage other than zero, see Typical Performance Curves. (4) V NOISE RTI = V N INPUT + (V N OUTPUT /Gain). () Time required for output to return from saturation to linear operation following the removal of an input overdrive voltage. PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View In +In R G Input Offset Adj. 4 4 DIP/SOIC x Output Offset Adj. Output Offset Adj. x Supply Voltage... ±V Input Voltage Range... ±V CC Operating Temperature Range: G... C to + C P, U... C to + C Storage Temperature Range: G... C to + C P, U... 4 C to + C Lead Temperature (soldering, s): G, P... + C (soldering, s): U... + C Output Short Circuit Duration... Continuous to Common Input Offset Adj. Reference x x PACKAGE INFORMATION V CC +V CC Output Sense Output PACKAGE DRAWING MODEL PACKAGE NUMBER () INAAG -Pin Ceramic DIP INABG -Pin Ceramic DIP INASG -Pin Ceramic DIP INAKP -Pin Plastic DIP INAKU SOL- SOIC NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL PACKAGE TEMPERATURE RANGE INAAG -Pin Ceramic DIP C to + C INABG -Pin Ceramic DIP C to + C INASG -Pin Ceramic DIP C to + C INAKP -Pin Plastic DIP C to + C INAKU SOL- SOIC C to + C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. INA

4 DICE INFORMATION 4 A B 4 INA DIE TOPOGRAPHY PAD FUNCTION In +In A,B R G (connect both) 4 Input Offset Adjust Input Offset Adjust Reference V CC +V CC Output Output Sense x x x 4 Output Offset Adjust Output Offset Adjust x Pads A and B must be connected. Substrate Bias: Internally connected to V CC power supply. MECHANICAL INFORMATION MILS (.") MILLIMETERS Die Size x ±. x. ±. Die Thickness ±. ±. Min. Pad Size 4 x 4. x. Backing Gold TYPICAL PERFORMANCE CURVES At T A = + C, and ±V CC = VDC, unless otherwise noted. ± INPUT VOLTAGE RANGE vs SUPPLY ± OUTPUT SWING vs SUPPLY Input Voltage Range (V) ± ± ± Output Voltage (V) ± ± ± R L = kω ± ± ± ± ± ± Power Supply Voltage (V) ±4 ± ± ± ± ± Power Supply Voltage (V) ± OUTPUT SWING vs LOAD RESISTANCE BIAS CURRENT vs SUPPLY Output Voltage (V) ± ± ±4 Input Bias Current (pa) 4.k.k M Load Resistance (Ω) ± ± ± ± ± Power Supply Voltage (V) INA 4

5 TYPICAL PERFORMANCE CURVES (CONT) T A = + C, ±V CC = VDC, unless otherwise noted. na BIAS CURRENT vs TEMPERATURE k G = GAIN vs FREQUENCY na G = Input Bias Current pa pa Gain (V/V) G = G = pa pa G = k k k M M Temperature ( C) Frequency (Hz) Common-Mode Rejection (db) 4 CMR vs FREQUENCY G = G = G = G = G = Power Supply Rejection (db) 4 POWER SUPPLY REJECTION vs FREQUENCY G = G = G = G = G = k k k M Frequency (Hz) k k k M Frequency (Hz) LARGE SIGNAL TRANSIENT RESPONSE (G = ) SMALL SIGNAL TRANSIENT RESPONSE (G = ) Output Voltage (V) Output Voltage (V) Time (µs) Time (µs) INA

6 TYPICAL PERFORMANCE CURVES (CONT) T A = + C, ±V CC = VDC, unless otherwise noted. SETTLING TIME vs GAIN (.%, V Step) OUTPUT NOISE VOLTAGE vs FREQUENCY Settling Time (µs) Output Noise Voltage (nv/ Hz) k Gain (V/V) k k Frequency (Hz) INPUT NOISE VOLTAGE vs FREQUENCY COMMON-MODE VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE Input Noise Voltage (nv/ Hz) Common-Mode Voltage (V) k k Frequency (Hz) Differential Input Voltage x Gain (V) = V O WARM-UP DRIFT vs TIME Change In Input Offset Voltage (µv) 4 4 Time (minutes) INA

7 DISCUSSION OF PERFORMANCE A simplified diagram of the INA is shown on the first page. The design consists of the classical three operational amplifier configuration using current-feedback type op amps with precision FET buffers on the input. The result is an instrumentation amplifier with premium performance not normally found in integrated circuits. The input section (A and A ) incorporates high performance, low bias current, and low drift amplifier circuitry. The amplifiers are connected in the noninverting configuration to provide high input impedance ( Ω). Laser-trimming is used to achieve low offset voltage. Input cascoding assures low bias current and high CMR. Thin-film resistors on the integrated circuit provide excellent gain accuracy and temperature stability. The output section (A ) is connected in a unity-gain difference amplifier configuration. Precision matching of the four kω resistors, especially over temperature and time, assures high common-mode rejection. BASIC POWER SUPPLY AND SIGNAL CONNECTIONS Figure shows the proper connections for power supply and signal. Supplies should be decoupled with µf tantalum capacitors as close to the amplifier as possible. To avoid gain and CMR errors introduced by the external circuit, connect grounds as indicated, being sure to minimize ground resistance. Resistance in series with the reference (pin ) will degrade CMR. To maintain stability, avoid capacitance from the output to the gain set, offset adjust, and input pins. x x x x V OUT = G INA +V CC Sense V OUT µf R L INA s input (RTI) is the offset of the input stage plus the offset of the output stage divided by the gain of the input stage. This allows specification of offset independent of gain. Input Offset Adjust kω kω 4 4 FIGURE. Offset Adjustment Circuit. +V CC INA V CC Output Offset Adjust V OUT For systems using computer autozeroing techniques, neither offset nor offset drift are of concern. In many other applications, the factory-trimmed offset gives excellent results. When greater accuracy is desired, one adjustment is usually sufficient. In high gains (>) adjust only the input offset, and in low gains the output offset. For higher precision in all gains, both can be adjusted by first selecting high gain and adjusting input offset and then low gain and adjusting output offset. The offset adjustment will, however, add to the drift by approximately.µv/ C per µv of input offset voltage that is adjusted. Therefore, care should be taken when considering use of adjustment. Output offsetting can be accomplished as shown in Figure by applying a voltage to the reference (pin ) through a buffer. This limits the resistance in series with pin to minimize CMR error. Be certain to keep this resistance low. Note that the offset error can be adjusted at this reference point with no appreciable degradation in offset drift. INA V OUT +V CC V CC µf R V OFFSETTING OPA R V CC FIGURE. Basic Circuit Connection. OFFSET ADJUSTMENT Figure shows the offset adjustment circuit for the INA. Both the offset of the input stage and output stage can be adjusted separately. Notice that the offset referred to the V OUT = V OFFSETTING + G. FIGURE. Output Offsetting. V OFFSETTING With ±V CC = V, R = kω, R = MΩ. R = kω, V OFFSETTING = ±mv. R INA

8 GAIN SELECTION Gain selection is accomplished by connecting the appropriate pins together on the INA. Table I shows possible gains from the internal resistors. Keep the connections as short as possible to maintain accuracy. CONNECT PIN GAIN GAIN GAIN TO PIN ACCURACY (%) DRIFT (ppm/ C) The following gains have guaranteed accuracy: none..... The following gains have typical accuracy as shown:,.,. 4, 4,, TABLE I. Internal Gain Connections. Gains other than,,,, and can be set by adding an external resistor, R G, between pin and pins,, and. Gain accuracy is a function of R G and the internal resistors which have a ±% tolerance with ppm/ C drift. The equation for choosing R G is shown below. 4k R G = Ω G Gain can also be changed in the output stage by adding resistance to the feedback loop shown in Figure 4. This is useful for increasing the total gain or reducing the input stage gain to prevent saturation of input amplifiers. The output gain can be changed as shown in Table II. Matching of R and R is required to maintain high CMR. R sets the gain with no effect on CMR. OUTPUT STAGE GAIN R AND R R.kΩ.4kΩ kω Ω.kΩ 4Ω TABLE II. Output Stage Gain Control. COMMON-MODE INPUT RANGE It is important not to exceed the input amplifiers dynamic range (see Typical Performance Curves). The differential input signal and its associated common-mode voltage should not cause the output of A and A (input amplifiers) to exceed approximately ±V with ±V supplies or nonlinear operation will result. Such large common-mode voltages, when the INA is in high gain, can cause saturation of the input stage even though the differential input is very small. This can be avoided by reducing the input stage gain and increasing the output stage gain with an H pad attenuator (see Figure 4). OUTPUT SENSE An output sense has been provided to allow greater accuracy in connecting the load. By attaching this feedback point to the load at the load site, IR drops due to load currents that are eliminated since they are inside the feedback loop. Proper connection is shown in Figure. When more current is to be supplied, a power booster can be placed within the feedback loop as shown in Figure. Buffer errors are minimized by the loop gain of the output amplifier. FIGURE 4. Gain Adjustment of Output Stage Using H Pad Attenuator. INA INA Sense FIGURE. Current Boosting the Output. V OUT I L = ma R L V OUT LOW BIAS CURRENT OF FET INPUT ELIMINATES DC ERRORS Because the INA has FET inputs, bias currents drawn through input source resistors have a negligible effect on DC accuracy. The picoamp levels produce no more than microvolts through megohm sources. Thus, input filtering and input series protection are readily achievable. A return path for the input bias currents must always be provided to prevent charging of stray capacitance. Otherwise, the output can wander and saturate. A MΩ to MΩ resistor from the input to common will return floating sources such as transformers, thermocouples, and AC-coupled inputs (see Applications section). DYNAMIC PERFORMANCE The INA is a fast-settling FET input instrumentation amplifier. Therefore, careful attention to minimize stray capacitance is necessary to achieve specified performance. High source resistance will interact with input capacitance to reduce the overall bandwidth. Also, to maintain stability, avoid capacitance from the output to the gain set, offset adjust, and input pins. Applications with balanced-source impedance will provide the best performance. In some applications, mismatched source impedances may be required. If the impedance in the R R R Output Stage Gain = (R kω) + R + R R kω INA

9 negative input exceeds that in the positive input, stray capacitance from the output will create a net negative feedback and improve the circuit stability. If the impedance in the positive input is greater, the feedback due to stray capacitance will be positive and instability may result. The degree of positive feedback depends upon source impedance imbalance, operating gain, and board layout. The addition of a small bypass capacitor of pf to pf directly between the inputs of the IA will generally eliminate any positive feedback. CMR errors due to the input impedance mismatch will also be reduced by the capacitor. The INA is designed for fast settling with easy gain selection. It has especially excellent settling in high gain. It can also be used in fast-settling unity-gain applications. As with all such amplifiers, the INA does exhibit significant gain peaking when set to a gain of. It is, however, unconditionally stable. The gain peaking can be cancelled by band-limiting the negative input to 4kHz with a simple external RC circuit for applications requiring flat response. CMR is not affected by the addition of the 4kHz RC in a gain of. Another distinct advantage of the INA is the high frequency CMR response. High frequency noise and sharp common-mode transients will be rejected. To preserve AC CMR, be sure to minimize stray capacitance on the input lines. Matching the RCs in the two inputs will help to maintain high AC CMR. APPLICATIONS In addition to general purpose uses, the INA is designed to accurately handle two important and demanding applications: () inputs with high source impedances such as capacitance/crystal/photodetector sensors and low-pass filters and series-input protection devices, and () rapidscanning data acquisition systems requiring fast settling time. Because the user has access to the output sense, current sources can also be constructed using a minimum of external components. Figures through show application circuits. +V Transducer X INA V OUT V FIGURE. Transformer-Coupled Amplifier. Thermocouple Transducer or Other Floating Source X MΩ +V INA V V OUT X +V INA V V OUT FIGURE. Floating Source Instrumentation Amplifier. Ω OPA Divider minimizes degredation of CMR due to distributed capacitance on the input lines. FIGURE. Instrumentation Amplifier with Shield Driver. INA

10 V REF Ω kω () kω () µf () X +V INA V OUT V FET input allows low-pass filtering with minimal effect on DC accuracy. NOTE: () Larger resistors and a smaller capacitor can be used. FIGURE. Bridge Amplifier with Hz Low-Pass Input Filter. µf MΩ mvp-p X +V INA V OUT In In In In B-B MPC X +V INA SHC V OUT µf MΩ V V FIGURE. AC-Coupled Differential Amplifier for Frequencies Greater Than.Hz. FIGURE. Rapid-Scanning-Rate Data Acquisition Channel with µs Settling to.%. +V Decoder/ Latch/Driver X X X X +V V V OUT V IN.4MΩ () X.4MΩ () pf.mω () INA V V OUT kω A A A NOTE: Use manual switch or low resistance relay. Layout is critical (see section on Dynamic Performance). pf pf FIGURE. Programmable-Gain Instrumentation Amplifier (Precision Noninverting or Inverting Buffer with Gain). NOTE: () For Hz use.mω and.mω. kω potentiometer sets Q. FIGURE. Hz Input Notch Filter. INA

11 V R +V D D X V +V R D V V D 4 +V INA V V OUT V V kω kω kω X +V INA Overall G = V OUT For lower voltage, lower resistor noise: R = R = kω, D D 4 = FDH (na leakage) For higher voltage, higher resistor noise: R = R = kω, D D 4 = N4A (pa leakage) Matching of RCs on inputs will affect CMR, but can be optimized by trimming R or R. kω V Common-mode range = ±V. CMR is dependent on ratio matching of external input resistors. FIGURE 4. Input-Protected Instrumentation Amplifier. FIGURE. High Common-Mode Voltage Differential Amplifier. V +V +V X A V IN PGA OUT R G 4 V CODE GAIN TYPICAL.% SETTLING TIME µs µs µs X X PGA Gain Select FIGURE. Digitally-Controlled Fast-Settling Programmable Gain Instrumentation Amplifier. X X X X R G +V INA +V NA kω R X X X X R G +V INA V I OUT = ( ) (G) (/k + /R) For ma to ma output, R =.Ω with ( ) (G) = V R I OUT R L X X X X R G V INA + V OUT FIGURE. Differential Input FET Buffered Current Source. FIGURE. Differential Input/Differential Output Amplifier. INA

12 PACKAGE DRAWINGS INA