Low Cost, Low Power Instrumentation Amplifier AD620

Transcription

1 a FEATURES EASY TO USE Gain Set with One External Resistor (Gain Range to 000) Wide Power Supply Range (.3 V to V) Higher Performance than Three Op Amp IA Designs Available in -Lead DIP and SOIC Packaging Low Power,.3 ma max Supply Current EXCELLENT DC PERFORMANCE ( B GRADE ) 0 V max, Input Offset Voltage 0. V/ C max, Input Offset Drift.0 na max, Input Bias Current 00 db min Common-Mode Rejection Ratio (G = 0) LOW NOISE 9 nv/ khz, Input Voltage Noise 0. V p-p Noise (0. Hz to 0 Hz) EXCELLENT AC SPECIFICATIONS 0 khz Bandwidth (G = 00) s Settling Time to 0.0% APPLICATIONS Weigh Scales ECG and Medical Instrumentation Transducer Interface Data Acquisition Systems Industrial Process Controls Battery Powered and Portable Equipment PRODUCT DESCRIPTION The is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of to Low Cost, Low Power Instrumentation Amplifier CONNECTION DIAGRAM -Lead Plastic Mini-DIP (N), Cerdip (Q) and SOIC (R) Packages IN +IN 3 4 TOP VIEW Furthermore, the features -lead SOIC and DIP packaging that is smaller than discrete designs, and offers lower power (only.3 ma max supply current), making it a good fit for battery powered, portable (or remote) applications. The, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 0 µv max and offset drift of 0. µv/ C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the make it well suited for medical applications such as ECG and noninvasive blood pressure monitors. The low input bias current of.0 na max is made possible with the use of Superβeta processing in the input stage. The works well as a preamplifier due to its low input voltage noise of 9 nv/ Hz at khz, 0. µv p-p in the 0. Hz to 0 Hz band, 0. pa/ Hz input current noise. Also, the is well suited for multiplexed applications with its settling time of µs to 0.0% and its cost is low enough to enable designs with one inamp per channel. REF 30,000 0,000 TOTAL ERROR, PPM OF FULL SCALE,000 0,000,000 0,000,000 A 3 OP-AMP IN-AMP (3 OP-07s) RTI VOLTAGE NOISE (0. 0Hz) V p-p, G = 00 TYPICAL STANDARD BIPOLAR INPUT IN-AMP SUPER ETA BIPOLAR INPUT IN-AMP SUPPLY CURRENT ma Figure. Three Op Amp IA Designs vs. 0. k 0k 00k M 0M 00M SOURCE RESISTANCE Figure. Total Voltage Noise vs. Source Resistance Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 90, Norwood, MA 00-90, U.S.A. Tel: 7/ World Wide Web Site: Fax: 7/3-703 Analog Devices, Inc., 999

2 SPECIFICATIONS + C, VS = V, and R L = k, unless otherwise noted) A B S Model Conditions Min Typ Max Min Typ Max Min Typ Max Units GAIN G = + (49.4 k/ ) Gain Range 0,000 0,000 0,000 Gain Error = ± 0 V G = % G = % G = % G = % Nonlinearity, = 0 V to +0 V, G = 000 R L = 0 kω ppm G = 00 R L = kω ppm Gain vs. Temperature G = ppm/ C Gain > ppm/ C VOLTAGE OFFSET (Total RTI Error = V OSI + V OSO /G) Input Offset, V OSI V S = ± V to ± V µv Over Temperature V S = ± V to ± V µv Average TC V S = ± V to ± V µv/ C Output Offset, V OSO V S = ± V µv V S = ± V µv Over Temperature V S = ± V to ± V µv Average TC V S = ± V to ± V µv/ C Offset Referred to the Input vs. Supply (PSR) V S = ±.3 V to ± V G = db G = db G = db G = db INPUT CURRENT Input Bias Current na Over Temperature.. 4 na Average TC pa/ C Input Offset Current na Over Temperature na Average TC...0 pa/ C INPUT Input Impedance Differential GΩ pf Common-Mode GΩ pf Input Voltage Range 3 V S = ±.3 V to ± V V Over Temperature V V S = ± V to ± V V Over Temperature V Common-Mode Rejection Ratio DC to 0 Hz with I kω Source Imbalance V CM = 0 V to ±0 V G = db G = db G = db G = db Output Swing R L = 0 kω, V S = ±.3 V to ± V V Over Temperature V V S = ± V to ± V V Over Temperature V Short Current Circuit ± ± ± ma

3 A B S Model Conditions Min Typ Max Min Typ Max Min Typ Max Units DYNAMIC RESPONSE Small Signal 3 db Bandwidth G = khz G = khz G = khz G = 000 khz Slew Rate V/µs Settling Time to 0.0% 0 V Step G = 00 µs G = µs NOISE Voltage Noise, khz Total RTI Noise = (e ni )+(e no / G) Input, Voltage Noise, e ni nv/ Hz Output, Voltage Noise, e no nv/ Hz RTI, 0. Hz to 0 Hz G = µv p-p G = µv p-p G = µv p-p Current Noise f = khz fa/ Hz 0. Hz to 0 Hz pa p-p INPUT R IN kω I IN V IN+, V REF = µa Voltage Range V Gain to Output ± ± ± POWER SUPPLY Operating Range 4 ±.3 ± ±.3 ± ±.3 ± V Quiescent Current V S = ±.3 V to ± V ma Over Temperature ma TEMPERATURE RANGE For Specified Performance 40 to + 40 to + to + C NOTES See Analog Devices military data sheet for 3B tested specifications. Does not include effects of external resistor. 3 One input grounded. G =. 4 This is defined as the same supply range which is used to specify PSR. Specifications subject to change without notice. 3

4 ABSOLUTE IMUM RATINGS Supply Voltage ± V Internal Power Dissipation mw Input Voltage (Common Mode) ±V S Differential Input Voltage ± V Output Short Circuit Duration Indefinite Storage Temperature Range (Q) C to +0 C Storage Temperature Range (N, R) C to + C Operating Temperature Range (A, B) C to + C (S) C to + C Lead Temperature Range (Soldering 0 seconds) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for device in free air: -Lead Plastic Package: θ JA = 9 C/W -Lead Cerdip Package: θ JA = 0 C/W -Lead SOIC Package: θ JA = C/W ORDERING GUIDE Model Temperature Ranges Package Options* AN 40 C to + C N- BN 40 C to + C N- AR 40 C to + C SO- AR-REEL 40 C to + C 3" REEL AR-REEL7 40 C to + C 7" REEL BR 40 C to + C SO- BR-REEL 40 C to + C 3" REEL BR-REEL7 40 C to + C 7" REEL ACHIPS 40 C to + C Die Form SQ/3B C to + C Q- *N = Plastic DIP; Q = Cerdip; SO = Small Outline. METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions. * (.799) 3 4 * IN 0. (3.0) *FOR CHIP APPLICATIONS: THE PADS AND MUST BE CONNECTED IN PARALLEL TO THE EXTERNAL GAIN REGISTER. DO NOT CONNECT THEM IN SERIES TO. FOR UNITY GAIN APPLICATIONS WHERE IS NOT REQUIRED, THE PADS MAY SIMPLY BE BONDED TOGETHER, AS WELL AS THE PADS. +IN CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 4

5 I 0 A V B 0 A I... C A A C 0k 0k A3... IN R3 400 Q R GAIN SENSE R GAIN SENSE Q 0k R k +IN REF Figure 3b. Gain Nonlinearity, G = 00, R L = 0 kω (00 µv = 0 ppm) Figure 3c. Gain Nonlinearity, G = 000, R L = 0 kω ( mv = 00 ppm) INPUT 0V p-p 00k k k 00 G= k * G= G=00 G= k *ALL RESISTORS % TOLERANCE k 0T 0k Figure 3. Settling Time Test Circuit Figure 33. Simplified Schematic of THEORY OF OPERATION The is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.% at G = 00) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The input transistors Q and Q provide a single differentialpair bipolar input for high precision (Figure 33), yet offer 0 lower Input Bias Current thanks to Superβeta processing. Feedback through the Q-A-R loop and the Q-A-R loop maintains constant collector current of the input devices Q, Q thereby impressing the input voltage across the external gain setting resistor. This creates a differential gain from the inputs to the A/A outputs given by G = (R + R)/ +. The unity-gain subtracter A3 removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of also determines the transconductance of the preamp stage. As is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gainrelated errors. (b) The gain-bandwidth product (determined by C, C and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nv/ Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R and R, are trimmed to an absolute value of 4.7 kω, allowing the gain to be programmed accurately with a single external resistor. The gain equation is then G = 49.4 kω + so that = 49.4 kω G 0

6 Make vs. Buy: A Typical Bridge Application Error Budget The offers improved performance over homebrew three op amp IA designs, along with smaller size, fewer components and 0 lower supply current. In the typical application, shown in Figure 34, a gain of 00 is required to amplify a bridge output of 0 mv full scale over the industrial temperature range of 40 C to + C. The error budget table below shows how to calculate the effect various error sources have on circuit accuracy. Regardless of the system in which it is being used, the provides greater accuracy, and at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle will remove all absolute accuracy and drift errors leaving only the resolution errors of gain nonlinearity and noise, thus allowing full 4-bit accuracy. Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error. +0V R = 30 R = 30 OP07D 0k ** 0k * 0k * R = 30 R = A 00 ** 0k ** OP07D OP07D 0k * 0k * PRECISION BRIDGE TRANSDUCER A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 00 SUPPLY CURRENT =.3mA Figure 34. Make vs. Buy HOMEBREW IN-AMP, G = 00 *0.0% RESISTOR MATCH, 3PPM/ C TRACKING **DISCRETE % RESISTOR, 00PPM/ C TRACKING SUPPLY CURRENT = ma Table I. Make vs. Buy Error Budget Circuit Homebrew Circuit Error, ppm of Full Scale Error Source Calculation Calculation Homebrew ABSOLUTE ACCURACY at T A = + C Input Offset Voltage, µv µv/0 mv (0 µv )/0 mv,0 0,07 Output Offset Voltage, µv 000 µv/00/0 mv ((0 µv )/00)/0 mv 4,00 0,0 Input Offset Current, na na 30 Ω/0 mv ( na 30 Ω)/0 mv 4, 4,3 CMR, db 0 db 3. ppm, V/0 mv (0.0% Match V)/0 mv/00 4,79 0,00 Total Absolute Error 7,,30 DRIFT TO + C Gain Drift, ppm/ C (0 ppm + 0 ppm) 0 C 00 ppm/ C Track 0 C 3,00,000 Input Offset Voltage Drift, µv/ C µv/ C 0 C/0 mv (. µv/ C 0 C)/0 mv 3,000 0,07 Output Offset Voltage Drift, µv/ C µv/ C 0 C/00/0 mv (. µv/ C 0 C)/00/0 mv 4,40 0,0 Total Drift Error 7,00,77 RESOLUTION Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 4,40 0,40 Typ 0. Hz 0 Hz Voltage Noise, µv p-p 0. µv p-p/0 mv (0.3 µv p-p )/0 mv 4,4 3,7 G = 00, V S = ± V. (All errors are min/max and referred to input.) Total Resolution Error 4,4 0,7 Grand Total Error 4,,34

7 +V 3k 3k.7mA 3k 3k G= mA 7 B 4 0k 0k 0.0mA 0k AD70 0.mA REF IN AGND ADC DIGITAL DATA Figure 3. A Pressure Monitor Circuit which Operates on a + V Single Supply Pressure Measurement Although useful in many bridge applications such as weigh scales, the is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. Figure 3 shows a 3 kω pressure transducer bridge powered from + V. In such a circuit, the bridge consumes only.7 ma. Adding the and a buffered voltage divider allows the signal to be conditioned for only 3. ma of total supply current. Small size and low cost make the especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it will also serve applications such as diagnostic noninvasive blood pressure measurement. Medical ECG The low current noise of the allows its use in ECG monitors (Figure 3) where high source resistances of MΩ or higher are not uncommon. The s low power, low supply voltage requirements, and space-saving -lead mini-dip and SOIC package offerings make it an excellent choice for battery powered data recorders. Furthermore, the low bias currents and low current noise coupled with the low voltage noise of the improve the dynamic range for better performance. The value of capacitor C is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. PATIENT/CIRCUIT PROTECTION/ISOLATION +3V C R4 M R 0k R3 4.9k R 4.9k.k A G = Hz HIGH PASS FILTER G = 43 AMPLIFIER V/mV AD70J 3V Figure 3. A Medical ECG Monitor Circuit

8 Precision V-I Converter The, along with another op amp and two resistors, makes a precision current source (Figure 37). The op amp buffers the reference terminal to maintain good CMR. The output voltage V X of the appears across R, which converts it to a current. This current less only, the input bias current of the op amp, then flows out to the load. V IN+ V IN 3 7 Vx I L = R = [(V IN+ ) (V IN )] G R 4 AD70 + V X R LOAD Figure 37. Precision Voltage-to-Current Converter (Operates on. ma, ±3 V) GAIN SELECTION The s gain is resistor programmed by, or more precisely, by whatever impedance appears between Pins and. The is designed to offer accurate gains using 0.% % resistors. Table II shows required values of for various gains. Note that for G =, the pins are unconnected ( = ). For any arbitrary gain can be calculated by using the formula: = 49.4 kω G To minimize gain error, avoid high parasitic resistance in series with ; to minimize gain drift, should have a low TC less than 0 ppm/ C for the best performance. Table II. Required Values of Gain Resistors I L INPUT AND OFFSET VOLTAGE The low errors of the are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains and the output errors dominate at low gains. The total V OS for a given gain is calculated as: Total Error RTI = input error + (output error/g) Total Error RTO = (input error G) + output error TERMINAL The reference terminal potential defines the zero output voltage, and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR. INPUT PROTECTION The features 400 Ω of series thin film resistance at its inputs, and will safely withstand input overloads of up to ± V or ±0 ma for several hours. This is true for all gains, and power on and off, which is particularly important since the signal source and amplifier may be powered separately. For longer time periods, the current should not exceed ma (I IN V IN /400 Ω). For input overloads beyond the supplies, clamping the inputs to the supplies (using a low leakage diode such as an FD333) will reduce the required resistance, yielding lower noise. RF INTERFERENCE All instrumentation amplifiers can rectify out of band signals, and when amplifying small signals, these rectified voltages act as small dc offset errors. The allows direct access to the input transistor bases and emitters enabling the user to apply some first order filtering to unwanted RF signals (Figure 3), where RC /( πf) and where f the bandwidth of the ; C 0 pf. Matching the extraneous capacitance at Pins and and Pins and 3 helps to maintain high CMR. % Std Table Calculated 0.% Std Table Calculated Value of, Gain Value of, Gain 49.9 k k.00.4 k k k k k k k k ,003 IN R C 7 +IN R C 3 4 Figure 3. Circuit to Attenuate RF Interference 3

9 COMMON-MODE REJECTION Instrumentation amplifiers like the offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. For optimal CMR the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications shielded cables are used to minimize noise, and for best CMR over frequency the shield should be properly driven. Figures 39 and 40 show active data guards that are configured to improve ac common-mode rejections by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. GROUNDING Since the output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate local ground. In order to isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 4). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package as shown. INPUT ANALOG P.S. +V C V DIGITAL P.S. C +V AD4 + INPUT 0. F 0. F AD S/H F F AD74A ADC F + DIGITAL DATA Figure 39. Differential Shield Driver Figure 4. Basic Grounding Practice INPUT 00 AD4 + INPUT Figure 40. Common-Mode Shield Driver 4

10 GROUND RETURNS FOR INPUT BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents; therefore, when amplifying floating input sources such as transformers, or ac-coupled sources, there must be a dc path from each input to ground as shown in Figure 4. Refer to the Instrumentation Amplifier Application Guide (free from Analog Devices) for more information regarding in amp applications. INPUT INPUT LOAD LOAD + INPUT + INPUT TO POWER SUPPLY GROUND Figure 4a. Ground Returns for Bias Currents with Transformer Coupled Inputs TO POWER SUPPLY GROUND Figure 4b. Ground Returns for Bias Currents with Thermocouple Inputs INPUT LOAD + INPUT 00k 00k TO POWER SUPPLY GROUND Figure 4c. Ground Returns for Bias Currents with AC Coupled Inputs

11 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-) Package (0.9) 0.34 (.4) 0.0 (.33) 0.0 (4.0) 0. (.93) 4 PIN 0.0 (0.) (0.3) (.4) BSC 0.0 (7.) 0.40 (.0) 0.00 (.) 0.0 (0.3) (.77) 0.04 (.) 0.30 (3.30) MIN SEATING PLANE 0.3 (.) (7.) 0.0 (0.3) 0.00 (0.04) 0.9 (4.9) 0. (.93) C99c 0 7/99 Cerdip (Q-) Package 0.00 (0.3) MIN 0.0 (.4) (7.7) 0.0 (.9) 0.00 (.0) PIN 0.40 (0.9) 0.00 (.) 0.0 (0.3) 0.00 (.0) 0. (3.) 0.03 (0.) (.7) 0.04 (0.3) (.4) (0.7) BSC 0.0 (3.) MIN SEATING PLANE (.3) 0.90 (7.37) 0.0 (0.3) 0.00 (0.0) SOIC (SO-) Package 0.9 (.00) 0.90 (4.0) 0.74 (4.00) (3.0) (.0) 0.4 (.0) PIN (0.) (0.0) 0.0 (.7) 0.03 (.3) 0.09 (0.0) (0.) x 4 SEATING PLANE (0.49) (.7) 0.03 (0.3) BSC (0.) (0.9) (.7) 0.00 (0.4) PRINTED IN U.S.A.