Micropower, Single- and Dual-Supply, Rail-to-Rail Instrumentation Amplifier AD627

Transcription

1 Micropower, Single- and Dual-Supply, Rail-to-Rail Instrumentation Amplifier FEATURES Micropower, 85 μa maximum supply current Wide power supply range (+. V to ±8 V) Easy to use Gain set with one external resistor Gain range 5 (no resistor) to 000 Higher performance than discrete designs Rail-to-rail output swing High accuracy dc performance 0.03% typical gain accuracy (G = +5) (A) 0 ppm/ C typical gain drift (G = +5) 5 μv maximum input offset voltage (B dual supply) 00 μv maximum input offset voltage (A dual supply) μv/ C maximum input offset voltage drift (B) 3 μv/ C maximum input offset voltage drift (A) 0 na maximum input bias current Noise: 38 nv/ Hz RTI khz (G = +00) Excellent ac specifications A: 77 db minimum CMRR (G = +5) B: 83 db minimum CMRR (G = +5) 80 khz bandwidth (G = +5) 35 μs settling time to 0.0% (G = +5, 5 V step) APPLICATIONS 4 to 0 ma loop-powered applications Low power medical instrumentation ECG, EEG Transducer interfacing Thermocouple amplifiers Industrial process controls Low power data acquisition Portable battery-powered instruments CMRR (db) FUNCTIONAL BLOCK DIAGRAM IN +IN OUTPUT REF Figure. 8-Lead PDIP (N) and SOIC_N (R) TRADITIONAL LOW POWER DISCRETE DESIGN FREQUENCY (Hz) k Figure. CMRR vs. Frequency, ±5 VS, Gain = +5 0k GENERAL DESCRIPTION The is an integrated, micropower instrumentation amplifier that delivers rail-to-rail output swing on single and dual (+. V to ±8 V) supplies. The provides excellent ac and dc specifications while operating at only 85 μa maximum. The offers superior flexibility by allowing the user to set the gain of the device with a single external resistor while conforming to the 8-lead industry-standard pinout configuration. With no external resistor, the is configured for a gain of 5. With an external resistor, it can be set to a gain of up to 000. A wide supply voltage range (+. V to ±8 V) and micropower current consumption make the a perfect fit for a wide range of applications. Single-supply operation, low power consumption, and rail-to-rail output swing make the Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. ideal for battery-powered applications. Its rail-to-rail output stage maximizes dynamic range when operating from low supply voltages. Dual-supply operation (±5 V) and low power consumption make the ideal for industrial applications, including 4 to 0 ma loop-powered systems. The does not compromise performance, unlike other micropower instrumentation amplifiers. Low voltage offset, offset drift, gain error, and gain drift minimize errors in the system. The also minimizes errors over frequency by providing excellent CMRR over frequency. Because the CMRR remains high up to 00 Hz, line noise and line harmonics are rejected. The provides superior performance, uses less circuit board area, and costs less than micropower discrete designs. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... 3 Single Supply... 3 Dual Supply... 5 Dual and Single Supplies... 6 Absolute Maximum Ratings... 7 ESD Caution... 7 Pin Configurations and Function Descriptions... 8 Typical Performance Characteristics... 9 Theory of Operation... 4 Using the... 5 Basic Connections... 5 Setting the Gain... 5 Reference Terminal... 6 Input Range Limitations in Single-Supply Applications... 6 Output Buffering... 7 Input and Output Offset Errors... 7 Make vs. Buy: A Typical Application Error Budget... 8 Errors Due to AC CMRR... 9 Ground Returns for Input Bias Currents... 9 Layout and Grounding... 0 Input Protection... RF Interference... Applications Circuits... Classic Bridge Circuit... 4 to 0 ma Single-Supply Receiver... Thermocouple Amplifier... Outline Dimensions... 4 Ordering Guide... 4 REVISION HISTORY /07 Rev. C to Rev. D Changes to Features... Changes to Figure 9 to Figure 34 Captions... 3 Changes to Setting the Gain Section... 5 Changes to Input Range Limitations in Single-Supply Applications Section... 6 Changes to Table Changes to Figure /05 Rev. B to Rev. C Updated Format...Universal Added Pin Configurations and Function Descriptions Section... 8 Change to Figure Updated Outline Dimensions... 4 Changes to Ordering Guide... 4 Rev. A to Rev. B Changes to Figure 4 and Table I, Resulting Gain column... Change to Figure Rev. D Page of 4

3 SPECIFICATIONS SINGLE SUPPLY 5 C single supply, VS = 3 V and 5 V, and RL = 0 kω, unless otherwise noted. Table. A B Parameter Conditions Min Typ Max Min Typ Max Unit GAIN G = +5 + (00 kω/rg) Gain Range V/V Gain Error VOUT = ( VS) + 0. to (+VS) 0.5 G = % G = % G = % G = % Nonlinearity G = ppm G = ppm Gain vs. Temperature G = ppm/ C G > ppm/ C VOLTAGE OFFSET Input Offset, VOSI μv Over Temperature VCM = VREF = +VS/ μv Average TC μv/ C Output Offset, VOSO μv Over Temperature μv Average TC μv/ C Offset Referred to the Input vs. Supply (PSRR) G = db G = db G = db G = db INPUT CURRENT Input Bias Current na Over Temperature 5 5 na Average TC 0 0 pa/ C Input Offset Current na Over Temperature na Average TC pa/ C INPUT Input Impedance Differential 0 0 GΩ pf Common-Mode 0 0 GΩ pf Input Voltage Range 3 VS =. V to 36 V ( VS) 0. (+VS) ( VS) 0. (+VS) V Common-Mode Rejection VREF = VS/ Ratio 3 DC to 60 Hz with kω Source Imbalance G = +5 VS = 3 V, VCM = 0 V to.9 V db G = +5 VS = 5 V, VCM = 0 V to 3.7 V db OUTPUT Output Swing RL = 0 kω ( VS) + 5 (+VS) 70 ( VS) + 5 (+VS) 70 mv RL = 00 kω ( VS) + 7 (+VS) 5 ( VS) + 7 (+VS) 5 mv Short-Circuit Current Short circuit to ground ±5 ±5 ma Rev. D Page 3 of 4

4 A B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal 3 db Bandwidth G = khz G = khz G = khz Slew Rate +0.05/ / 0.07 V/μs Settling Time to 0.0% VS = 3 V,.5 V output step G = μs G = μs Settling Time to 0.0% VS = 5 V,.5 V output step G = μs G = μs Overload Recovery 50% input overload 3 3 μs Does not include effects of External Resistor RG. See Table 8 for total RTI errors. 3 See the Using the section for more information on the input range, gain range, and common-mode range. Rev. D Page 4 of 4

5 DUAL SUPPLY 5 C dual supply, VS = ±5 V and ±5 V, and RL = 0 kω, unless otherwise noted. Table. A B Parameter Conditions Min Typ Max Min Typ Max Unit GAIN G = +5 + (00 kω/rg) Gain Range V/V Gain Error VOUT = ( VS) + 0. to (+VS) 0.5 G = % G = % G = % G = % Nonlinearity G = +5 VS = ±5 V/±5 V 0/5 00 0/5 00 ppm G = +00 VS = ±5 V/±5 V 0/5 00 0/5 00 ppm Gain vs. Temperature G = ppm/ C G > ppm/ C VOLTAGE OFFSET Total RTI error = VOSI + VOSO/G Input Offset, VOSI μv Over Temperature VCM = VREF = 0 V μv Average TC μv/ C Output Offset, VOSO μv Over Temperature μv Average TC μv/ C Offset Referred to the Input vs. Supply (PSRR) G = db G = db G = db G = db INPUT CURRENT Input Bias Current 0 0 na Over Temperature 5 5 na Average TC 0 0 pa/ C Input Offset Current na Over Temperature 5 5 na Average TC 5 5 pa/ C INPUT Input Impedance Differential 0 0 GΩ pf Common Mode 0 0 GΩ pf Input Voltage Range 3 VS = ±. V to ±8 V ( VS) 0. (+VS) ( VS) 0. (+VS) V Common-Mode Rejection Ratio 3 DC to 60 Hz with kω Source Imbalance G = +5 to +000 VS = ±5 V, VCM = db 4 V to +3.0 V G = +5 to +000 VS = ±5 V, VCM = db V to +0.9 V OUTPUT Output Swing RL = 0 kω ( VS) + 5 (+VS) 70 ( VS) + 5 (+VS) 70 mv RL = 00 kω ( VS) + 7 (+VS) 5 ( VS) + 7 (+VS) 5 mv Short-Circuit Current Short circuit to ground ±5 ±5 ma Rev. D Page 5 of 4

6 A B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal 3 db Bandwidth G = khz G = khz G = khz Slew Rate +0.05/ / 0.06 V/μs Settling Time to 0.0% VS = ±5 V, +5 V output step G = μs G = μs Settling Time to 0.0% VS = ±5 V, +5 V output step G = μs G = μs Overload Recovery 50% input overload 3 3 μs Does not include effects of External Resistor RG. See Table 8 for total RTI errors. 3 See the Using the section for more information on the input range, gain range, and common-mode range. DUAL AND SINGLE SUPPLIES Table 3. A B Parameter Conditions Min Typ Max Min Typ Max Unit NOISE Voltage Noise, khz Total RTI Noise = e + e R ( ) ( ) ni no / G Input, Voltage Noise, eni nv/ Hz Output, Voltage Noise, eno nv/ Hz RTI, 0. Hz to 0 Hz G = +5.. μv p-p G = μv p-p Current Noise f = khz fa/ Hz 0. Hz to 0 Hz.0.0 pa p-p REFERENCE INPUT RIN RG = 5 5 kω Gain to Output Voltage Range POWER SUPPLY Operating Range Dual supply ±. ±8 ±. ±8 V Single supply V Quiescent Current μa Over Temperature na/ C TEMPERATURE RANGE For Specified Performance C See Using the section for more information on the reference terminal, input range, gain range, and common-mode range. Rev. D Page 6 of 4

7 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage ±8 V Internal Power Dissipation PDIP (N-8).3 W SOIC_N (R-8) 0.8 W IN, +IN VS 0 V to +VS + 0 V Common-Mode Input Voltage VS 0 V to +VS + 0 V Differential Input Voltage (+IN ( IN)) +VS ( VS) Output Short-Circuit Duration Indefinite Storage Temperature Range (N, R) 65 C to +5 C Operating Temperature Range 40 C to +85 C Lead Temperature (Soldering, 0 sec) 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Specification is for device in free air: 8-lead PDIP package: θja = 90 C/W. 8-lead SOIC_N package: θja = 55 C/W. Rev. D Page 7 of 4

8 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN +IN 3 4 TOP VIEW (Not to Scale) OUTPUT 5 REF Figure 3. 8-Lead PDIP Pin Configuration IN +IN 3 4 TOP VIEW (Not to Scale) OUTPUT REF Figure 4. 8-Lead SOIC_N Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description RG External Gain Setting Resistor. Place gain setting resistor across RG pins to set the gain. IN Negative Input. 3 +IN Positive Input. 4 VS Negative Voltage Supply Pin. 5 REF Reference Pin. Drive with low impedance voltage source to level shift the output voltage. 6 OUTPUT Output Voltage. 7 +VS Positive Supply Voltage. 8 RG External Gain Setting Resistor. Place gain setting resistor across RG pins to set the gain. Rev. D Page 8 of 4

9 TYPICAL PERFORMANCE CHARACTERISTICS At 5 C, VS = ±5 V, RL = 0 kω, unless otherwise noted NOISE (nv/ Hz, RTI) GAIN = +5 GAIN = +000 GAIN = +00 INPUT BIAS CURRENT (na) V S = ±5V V S = +5V V S = ±5V k 0k 00k FREQUENCY (Hz) Figure 5. Voltage Noise Spectral Density vs. Frequency TEMPERATURE ( C) Figure 8. Input Bias Current vs. Temperature CURRENT NOISE (fa/ Hz) k 0k FREQUENCY (Hz) Figure 6. Current Noise Spectral Density vs. Frequency POWER SUPPLY CURRENT (µa) TOTAL POWER SUPPLY VOLTAGE (V) Figure 9. Supply Current vs. Supply Voltage V+ INPUT BIAS CURRENT (na) COMMON-MODE INPUT (V) Figure 7. Input Bias Current vs. CMV, VS = ±5 V OUTPUT VOLTAGE SWING (V) (V+) (V+) V S = ±5V V S = ±.5V V S = ±5V V S = ±.5V SOURCING (V+) 3 (V ) + SINKING (V ) + V S = ±.5V V S = ±5V V S = ±.5V V S = ±5V V OUTPUT CURRENT (ma) Figure 0. Output Voltage Swing vs. Output Current Rev. D Page 9 of 4

10 500mV s POSITIVE PSRR (db) G = +000 G = +00 G = +5 Figure. 0. Hz to 0 Hz Current Noise (0.7 pa/div) k 0k 00k FREQUENCY (Hz) Figure 4. Positive PSRR vs. Frequency, ±5 V mV s NEGATIVE PSRR (db) G = +000 G = +00 G = Figure. 0. Hz to 0 Hz RTI Voltage Noise (400 nv/div), G = k 0k 00k FREQUENCY (Hz) Figure 5. Negative PSRR vs. Frequency, ±5 V V s POSITIVE PSRR (db) G = +5 G = +000 G = Figure Hz to 0 Hz RTI Voltage Noise (00 nv/div), G = k 0k 00k FREQUENCY (Hz) Figure 6. Positive PSRR vs. Frequency (VS = 5 V, 0 V) Rev. D Page 0 of 4

11 SETTLING TIME (ms) SETTLING TIME (µs) k 0 ± ±4 ±6 ±8 ±0 GAIN (V/V) OUTPUT PULSE (V) Figure 7. Settling Time to 0.0% vs. Gain for a 5 V Step at Output, RL = 0 kω, CL = 00 pf, VS = ±5 V Figure 0. Settling Time to 0.0% vs. Output Swing, G = +5, RL = 0 kω, CL = 00 pf mv V 50µs 00µV V 00µs Figure 8. Large Signal Pulse Response and Settling Time, G = 5, RL = 0 kω, CL = 00 pf (.5 mv = 0.0%) Figure. Large Signal Pulse Response and Settling Time, G = 00, RL = 0 kω, CL = 00 pf (00 μv = 0.0%) mv V 50µs 00µV V 500µs Figure 9. Large Signal Pulse Response and Settling Time, G = 0, RL = 0 kω, CL = 00 pf (.0 mv = 0.0%) Figure. Large Signal Pulse Response and Settling Time, G = 000, RL = 0 kω, CL = 00 pf (0 μv = 0.0%) Rev. D Page of 4

12 CMRR (db) G = G = G = k 0k 00k FREQUENCY (Hz) Figure 3. CMRR vs. Frequency, ±5 VS (CMV = 00 mv p-p) A 0µs 86mV EXT CH 0mV Figure 6. Small Signal Pulse Response, G = +0, RL = 0 kω, CL = 50 pf G = +000 CH 0mV A 00µs 86mV EXT G = +00 GAIN (db) G = +0 G = k 0k 00k FREQUENCY (Hz) Figure 4. Gain vs. Frequency (VS = 5 V, 0 V), VREF =.5 V Figure 7. Small Signal Pulse Response, G = +00, RL = 0 kω, CL = 50 pf CH 0mV A 0µs 88mV EXT CH 50mV A ms 86mV EXT Figure 5. Small Signal Pulse Response, G = +5, RL = 0 kω, CL = 50 pf Figure 8. Small Signal Pulse Response, G = +000, RL = 0 kω, CL = 50 pf Rev. D Page of 4

13 0µV/DIV 00µV/DIV 0.5V/DIV Figure 9. Gain Nonlinearity, Negative Input, VS = ±.5 V, G = +5 (4 ppm/div) V/DIV Figure 3. Gain Nonlinearity, Negative Input, VS = ±5 V, G = +00 (7 ppm/div) µV/DIV 00µV/DIV 0.5V/DIV Figure 30. Gain Nonlinearity, Negative Input, VS = ±.5 V, G = +00 (8 ppm/div) V/DIV Figure 33. Gain Nonlinearity, Negative Input, VS = ±5 V, G = +5 (7 ppm/div) µV/DIV 00µV/DIV 3V/DIV Figure 3. Gain Nonlinearity, Negative Input, VS = ±5 V, G = +5 (.5 ppm/div) V/DIV Figure 34. Gain Nonlinearity, Negative Input, VS = ±5 V, G = +00 (7 ppm/div) Rev. D Page 3 of 4

14 THEORY OF OPERATION The is a true instrumentation amplifier, built using two feedback loops. Its general properties are similar to those of the classic two-op-amp instrumentation amplifier configuration but internally the details are somewhat different. The uses a modified current feedback scheme, which, coupled with interstage feedforward frequency compensation, results in a much better common-mode rejection ratio (CMRR) at frequencies above dc (notably the line frequency of 50 Hz to 60 Hz) than might otherwise be expected of a low power instrumentation amplifier. In Figure 35, A completes a feedback loop that, in conjunction with V and R5, forces a constant collector current in Q. Assume that the gain-setting resistor (RG) is not present. Resistors R and R complete the loop and force the output of A to be equal to the voltage on the inverting terminal with a gain of nearly.5. A completes a nearly identical feedback loop that forces a current in Q that is nearly identical to that in Q; A also provides the output voltage. When both loops are balanced, the gain from the noninverting terminal to VOUT is equal to 5, whereas the gain from the output of A to VOUT is equal to 4. The inverting terminal gain of A (.5) times the gain of A ( 4) makes the gain from the inverting and noninverting terminals equal. The differential mode gain is equal to + R4/R3, nominally 5, and is factory trimmed to 0.0% final accuracy. Adding an external gain setting resistor (RG) increases the gain by an amount equal to (R4 + R)/RG. The output voltage of the is given by VOUT = [VIN(+) VIN( )] ( kω/rg) + VREF () Laser trims are performed on R through R4 to ensure that their values are as close as possible to the absolute values in the gain equation. This ensures low gain error and high commonmode rejection at all practical gains. EXTERNAL GAIN RESISTOR REF R 00kΩ R 5kΩ R3 5kΩ R4 00kΩ IN kω Q Q kω +IN A A OUTPUT R5 00kΩ V 0.V R6 00kΩ Figure 35. Simplified Schematic Rev. D Page 4 of 4

15 USING THE BASIC CONNECTIONS Figure 36 shows the basic connection circuit for the. The +VS and VS terminals connect to the power supply. The supply can be either bipolar (VS = ±. V to ±8 V) or single supply ( VS = 0 V, +VS =. V to 36 V). Capacitively decouple the power supplies close to the power pins of the device. For best results, use surface-mount 0. μf ceramic chip capacitors. The input voltage can be single-ended (tie either IN or +IN to ground) or differential. The difference between the voltage on the inverting and noninverting pins is amplified by the programmed gain. The gain resistor programs the gain as described in the Setting the Gain and Reference Terminal sections. Basic connections are shown in Figure 36. The output signal appears as the voltage difference between the output pin and the externally applied voltage on the REF pin, as shown in Figure 37. SETTING THE GAIN The gain of the is resistor programmed by RG, or, more precisely, by whatever impedance appears between Pin and Pin 8. The gain is set according to Gain = 5 + (00 kω/rg) or RG = 00 kω/(gain 5) () Therefore, the minimum achievable gain is 5 (for 00 kω/ (Gain 5)). With an internal gain accuracy of between 0.05% and 0.7%, depending on gain and grade, a 0.% external gain resistor is appropriate to prevent significant degradation of the overall gain error. However, 0.% resistors are not available in a wide range of values and are quite expensive. Table 6 shows recommended gain resistor values using % resistors. For all gains, the size of the gain resistor is conservatively chosen as the closest value from the standard resistor table that is higher than the ideal value. This results in a gain that is always slightly less than the desired gain, thereby preventing clipping of the signal at the output due to resistor tolerance. The internal resistors on the have a negative temperature coefficient of 75 ppm/ C maximum for gains > 5. Using a gain resistor that also has a negative temperature coefficient of 75 ppm/ C or less tends to reduce the overall gain drift of the circuit. +.V TO +8V 0.µF +IN +.V TO +36V 0.µF +IN V IN IN OUTPUT R REF G 0.µF REF (INPUT) V IN IN OUTPUT R REF G REF (INPUT).V TO 8V GAIN = 5 + (00kΩ/ ) Figure 36. Basic Connections for Single and Dual Supplies V+ V DIFF +IN REF EXTERNAL GAIN RESISTOR 00kΩ 5kΩ 5kΩ 00kΩ V CM V DIFF V IN IN kω Q Q kω +IN A A 00kΩ 0.V V A 00kΩ Figure 37. Amplifying Differential Signals with a Common-Mode Component OUTPUT Rev. D Page 5 of 4

16 Table 6. Recommended Values of Gain Resistors % Standard Table Desired Gain Value of RG Resulting Gain kω kω kω kω kω kω kω kω kω kω kω kω kω kω kω kω kω Ω Ω REFERENCE TERMINAL The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output. The reference terminal is also useful when amplifying bipolar signals, because it provides a virtual ground voltage. The output voltage is developed with respect to the potential on the reference terminal; therefore, tying the REF pin to the appropriate local ground solves many grounding problems. For optimal CMR, tie the REF pin to a low impedance point. INPUT RANGE LIMITATIONS IN SINGLE-SUPPLY APPLICATIONS In general, the maximum achievable gain is determined by the available output signal range. However, in single-supply applications where the input common-mode voltage is nearly or equal to 0, some limitations on the gain can be set. Although the Specifications section nominally defines the input, output, and reference pin ranges, the voltage ranges on these pins are mutually interdependent. Figure 37 shows the simplified schematic of the, driven by a differential voltage (VDIFF) that has a common-mode component, VCM. The voltage on the A op amp output is a function of VDIFF, VCM, the voltage on the REF pin, and the programmed gain. This voltage is given by VA =.5 (VCM V) 0.5 VREF VDIFF (5 kω/rg 0.65) (3) The voltage on A can also be expressed as a function of the actual voltages on the IN and +IN pins (V and V+) such that VA =.5 ((V ) V) 0.5 VREF ((V+) (V )) 5 kω/rg (4) The output of A is capable of swinging to within 50 mv of the negative rail and to within 00 mv of the positive rail. It is clear, from either Equation 3 or Equation 4, that an increasing VREF (while it acts as a positive offset at the output of the ) tends to decrease the voltage on A. Figure 38 and Figure 39 show the maximum voltages that can be applied to the REF pin for a gain of 5 for both the single-supply and dual-supply cases. V REF (V) V REF (V) MAXIMUM V REF MINIMUM V REF V IN ( ) (V) Figure 38. Reference Input Voltage vs. Negative Input Voltage, VS = ±5 V, G = MAXIMUM V REF MINIMUM V REF V IN ( ) (V) Figure 39. Reference Input Voltage vs. Negative Input Voltage, VS = 5 V, G = +5 Raising the input common-mode voltage increases the voltage on the output of A. However, in single-supply applications where the common-mode voltage is low, a differential input voltage or a voltage on REF that is too high can drive the output of A into the ground rail. Some low-side headroom is added because both inputs are shifted upwards by about 0.5 V (that is, by the VBE of Q and Q). Use Equation 3 and Equation 4 to check whether the voltage on Amplifier A is within its operating range Rev. D Page 6 of 4

17 Table 7. Maximum Gain for Low Common-Mode, Single-Supply Applications VIN REF Pin Supply Voltage RG (% Tolerance) Resulting Maximum Gain Output Swing WRT 0 V ±00 mv, VCM = 0 V V 5 V to 5 V 8.7 kω V to 3. V ±50 mv, VCM = 0 V V 5 V to 5 V 0.7 kω V to 3. V ±0 mv, VCM = 0 V V 5 V to 5 V.74 kω V to 3. V V = 0 V, V+ = 0 V to V V 0 V to 5 V 78.7 kω 7.5 V to 8.5 V V = 0 V, V+ = 0 mv to 00 mv V 5 V to 5 V 7.87 kω 3 V to 4. V V = 0 V, V+ = 0 mv to 0 mv V 5 V to 5 V 787 Ω 59. V to 3.6 V Table 8. RTI Error Sources Maximum Total RTI Offset Error (μv) Maximum Total RTI Offset Drift (μv/ C) Total RTI Noise (nv/ Hz) Gain A B A B A /B Table 7 gives values for the maximum gain for various singlesupply input conditions. The resulting output swings refer to 0 V. To maximize the available gain and output swing, set the voltages on the REF pins to either V or V. In most cases, there is no advantage to increasing the single supply to greater than 5 V (the exception is an input range of 0 V to V). OUTPUT BUFFERING The is designed to drive loads of 0 kω or greater but can deliver up to 0 ma to heavier loads at lower output voltage swings (see Figure 0). If more than 0 ma of output current is required at the output, buffer the output with a precision op amp, such as the OP3. Figure 40 shows this for a single supply. This op amp can swing from 0 V to 4 V on its output while driving a load as small as 600 Ω. INPUT AND OUTPUT OFFSET ERRORS The low errors of the are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, input errors dominate at high gains and output errors dominate at low gains. The total offset error for a given gain is calculated as Total Error RTI = Input Error + (Output Error/Gain) (5) Total Error RTO = (Input Error G) + Output Error (6) RTI offset errors and noise voltages for different gains are listed in Table 8. 0.µF 0.µF V IN 0.µF REF OP3 0.µF Figure 40. Output Buffering Rev. D Page 7 of 4

18 MAKE vs. BUY: A TYPICAL APPLICATION ERROR BUDGET The example in Figure 4 serves as a good comparison between the errors associated with an integrated and a discrete in-amp implementation. A ±00 mv signal from a resistive bridge (common-mode voltage =.5 V) is amplified. This example compares the resulting errors from a discrete two-op-amp instrumentation amplifier and the. The discrete implementation uses a four-resistor precision network (% match, 50 ppm/ C tracking). The errors associated with each implementation (see Table 9) show the integrated in-amp to be more precise at both ambient and overtemperature. Note that the discrete implementation is more expensive, primarily due to the relatively high cost of the low drift precision resistor network. The input offset current of the discrete instrumentation amplifier implementation is the difference in the bias currents of the twoop amplifiers, not the offset currents of the individual op amps. In addition, although the values of the resistor network are chosen so that the inverting and noninverting inputs of each op amp see the same impedance (about 350 Ω), the offset current of each op amp adds another error that must be characterized. +5V +5V +5V 350Ω 350Ω LT078SB 350Ω 350Ω ±00mV 40.kΩ % +0ppm/ C A / LT078SB / +.5V 3.5kΩ* 350Ω* 350Ω* 3.5kΩ* +.5V A GAIN = 9.98 (5+(00kΩ/ )) HOMEBREW IN-AMP, G = +0 *% RESISTOR MATCH, 50ppm/ C TRACKING Figure 4. Make vs. Buy Table 9. Make vs. Buy Error Budget Error Source Circuit Calculation Homebrew Circuit Calculation Total Error (ppm) Total Error Homebrew (ppm) ABSOLUTE ACCURACY at TA = 5 C Total RTI Offset Voltage, mv (50 μv + (000 μv/0))/00 mv (80 μv )/00 mv 3,500 3,600 Input Offset Current, na na 350 Ω/00 mv 0 na 350 Ω/00 mv Internal Offset Current Not applicable 0.7 na 350 Ω/00 mv.45 (Homebrew Only) CMRR, db 77 db 4 ppm.5 V/00 mv (% match.5 V)/0/00 mv 3,53 5,000 Gain 0.35% + 0.% % match 3,500 0,000 Total Absolute Error 0,535 38,67 DRIFT TO 85 C Gain Drift, ppm/ C ( ) ppm/ C 60 C 50 ppm/ C 60 C 3,900 3,000 Total RTI Offset Voltage, mv/ C (3.0 μv/ C + (0 μv/ C/0)) ( 3.5 μv/ C 60 C)/00 mv,600 4,00 60 C/00 mv Input Offset Current, pa/ C (6 pa/ C 350 Ω 60 C)/00 mv (33 pa/ C 350 Ω 60 C)/00 mv Total Drift Error 6,504 7,07 Grand Total Error 7,039 45,879 Rev. D Page 8 of 4

19 ERRORS DUE TO AC CMRR In Table 9, the error due to common-mode rejection results from the common-mode voltage from the bridge.5 V. The ac error due to less than ideal common-mode rejection cannot be calculated without knowing the size of the ac common-mode voltage (usually interference from 50 Hz/60 Hz mains frequencies). A mismatch of 0.% between the four gain setting resistors determines the low frequency CMRR of a two-op-amp instrumentation amplifier. The plot in Figure 43 shows the practical results of resistor mismatch at ambient temperature. The CMRR of the circuit in Figure 4 (Gain = +) was measured using four resistors with a mismatch of nearly 0.% (R = Ω, R = Ω, R3 = 000. Ω, R4 = Ω). As expected, the CMRR at dc was measured at about 84 db (calculated value is 85 db). However, as frequency increases, CMRR quickly degrades. For example, a 00 mv p-p harmonic of the mains frequency at 80 Hz would result in an output voltage of about 800 μv. To put this in context, a -bit data acquisition system, with an input range of 0 V to.5 V, has an LSB weighting of 60 μv. By contrast, the uses precision laser trimming of internal resistors, along with patented CMR trimming, to yield a higher dc CMRR and a wider bandwidth over which the CMRR is flat (see Figure 3). CMRR (db) VIN VIN R Ω A / OP96 5V R Ω R3 000.Ω +5V A / OP96 R Ω Figure 4. 0.% Resistor Mismatch Example GROUND RETURNS FOR INPUT BIAS CURRENTS Input bias currents are dc currents that must flow to bias the input transistors of an amplifier. They are usually transistor base currents. When amplifying floating input sources, such as transformers or ac-coupled sources, there must be a direct dc path into each input so that the bias current can flow. Figure 44, Figure 45, and Figure 46 show how to provide a bias current path for the cases of, respectively, transformer coupling, a thermocouple application, and capacitive ac-coupling. In dc-coupled resistive bridge applications, providing this path is generally not necessary because the bias current simply flows from the bridge supply through the bridge and into the amplifier. However, if the impedance that the two inputs see are large, and differ by a large amount (>0 kω), the offset current of the input stage causes dc errors compatible with the input offset voltage of the amplifier. INPUT +INPUT REFERENCE LOAD TO POWER SUPPLY GROUND Figure 44. Ground Returns for Bias Currents with Transformer Coupled Inputs INPUT +INPUT REFERENCE LOAD TO POWER SUPPLY GROUND Figure 45. Ground Returns for Bias Currents with Thermocouple Inputs INPUT 8 +INPUT 3 00kΩ REFERENCE LOAD TO POWER SUPPLY GROUND Figure 46. Ground Returns for Bias Currents with AC-Coupled Inputs k 0k 00k FREQUENCY (Hz) Figure 43. CMRR over Frequency of Discrete In-Amp in Figure Rev. D Page 9 of 4

20 LAYOUT AND GROUNDING The use of ground planes is recommended to minimize the impedance of ground returns (and hence, the size of dc errors). To isolate low level analog signals from a noisy digital environment, many data acquisition components have separate analog and digital ground returns (see Figure 47). Return all ground pins from mixed-signal components, such as analog-to-digital converters, through the high quality analog ground plane. Digital ground lines of mixed-signal components should also be returned through the analog ground plane. This may seem to break the rule of separating analog and digital grounds; however, in general, there is also a requirement to keep the voltage difference between digital and analog grounds on a converter as small as possible (typically, <0.3 V). The increased noise, caused by the digital return currents of the converter flowing through the analog ground plane, is generally negligible. To maximize isolation between analog and digital, connect the ground planes back at the supplies. If there is only one power supply available, it must be shared by both digital and analog circuitry. Figure 48 shows how to minimize interference between the digital and analog circuitry. As in the previous case, use separate analog and digital ground planes or use reasonably thick traces as an alternative to a digital ground plane. Connect the ground planes at the ground pin of the power supply. Run separate traces (or power planes) from the power supply to the supply pins of the digital and analog circuits. Ideally, each device should have its own power supply trace, but they can be shared by multiple devices if a single trace is not used to route current to both digital and analog circuitry. ANALOG POWER SUPPLY +5V 5V GND DIGITAL POWER SUPPLY GND +5V 0.µF 0.µF 0.µF 0.µF V IN V DD AGND DGND V IN ADC AD789- AGND V DD MICRO- PROCESSOR Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies POWER SUPPLY 5V GND 0.µF 0.µF 0.µF V IN V DD ADC AGND DGND AD789- Figure 48. Optimal Ground Practice in a Single-Supply Environment V DD DGND MICRO- PROCESSOR Rev. D Page 0 of 4

21 INPUT PROTECTION As shown in the simplified schematic (see Figure 35), both the inverting and noninverting inputs are clamped to the positive and negative supplies by ESD diodes. In addition, a kω series resistor on each input provides current limiting in the event of an overvoltage. These ESD diodes can tolerate a maximum continuous current of 0 ma. So an overvoltage (that is, the amount by which the input voltage exceeds the supply voltage) of ±0 V can be tolerated. This is true for all gains, and for power on and off. This last case is particularly important because the signal source and amplifier can be powered separately. If the overvoltage is expected to exceed 0 V, use additional external series current-limiting resistors to keep the diode current below 0 ma. RF INTERFERENCE All instrumentation amplifiers can rectify high frequency outof-band signals. Once rectified, these signals appear as dc offset errors at the output. The circuit in Figure 49 provides good RFI suppression without reducing performance within the pass band of the instrumentation amplifier. Resistor R and Capacitor C (and likewise, R and C) form a low-pass RC filter that has a 3 db BW equal to f = /(π(r C)) (7) Using the component values shown in Figure 49, this filter has a 3 db bandwidth of approximately 8 khz. Resistor R and Resistor R were selected to be large enough to isolate the circuit input from the capacitors but not large enough to significantly increase circuit noise. To preserve common-mode rejection in the amplifier pass band, Capacitor C and Capacitor C must be 5% mica units, or low cost 0% units can be tested and binned to provide closely matched devices. Capacitor C3 is needed to maintain common-mode rejection at low frequencies. R/R and C/C form a bridge circuit whose output appears across the input pins of the in-amp. Any mismatch between C and C unbalances the bridge and reduces commonmode rejection. C3 ensures that any RF signals are common mode (the same on both in-amp inputs) and are not applied differentially. This second low-pass network, R + R and C3, has a 3 db frequency equal to /(π((r + R) C3)) (8) +IN IN R 0kΩ % R 0kΩ % C 000pF 5% C3 0.0µF C 000pF 5% 0.33µF 0.33µF 0.0µF REFERENCE 0.0µF Figure 49. Circuit to Attenuate RF Interference Using a C3 value of 0.0 μf, as shown in Figure 49, the 3 db signal bandwidth of this circuit is approximately 00 Hz. The typical dc offset shift over frequency is less than mv and the RF signal rejection of the circuit is better than 57 db. To increase the 3 db signal bandwidth of this circuit, reduce the value of Resistor R and Resistor R. The performance is similar to that when using 0 kω resistors, except that the circuitry preceding the in-amp must drive a lower impedance load. When building a circuit like that shown in Figure 49, use a PC board with a ground plane on both sides. Make all component leads as short as possible. Resistor R and Resistor R can be common % metal film units, but Capacitor C and Capacitor C must be ±5% tolerance devices to avoid degrading the commonmode rejection of the circuit. Either the traditional 5% silver mica units or Panasonic ±% PPS film capacitors are recommended Rev. D Page of 4

22 APPLICATIONS CIRCUITS CLASSIC BRIDGE CIRCUIT Figure 50 shows the configured to amplify the signal from a classic resistive bridge. This circuit works in dual-supply mode or single-supply mode. Typically, the same voltage that powers the instrumentation amplifiers excites the bridge. Connecting the bottom of the bridge to the negative supply of the instrumentation amplifiers (usually 0 V, 5 V, V, or 5 V), sets up an input common-mode voltage that is optimally located midway between the supply voltages. It is also appropriate to set the voltage on the REF pin to midway between the supplies, especially if the input signal is bipolar. However, the voltage on the REF pin can be varied to suit the application. For example, the REF pin is tied to the VREF pin of an analog-to-digital converter (ADC) whose input range is (VREF ± VIN). With an available output swing on the of ( VS + 00 mv) to (+VS 50 mv), the maximum programmable gain is simply this output range divided by the input range. V DIFF = 00kΩ GAIN 5 0.µF 0.µF Figure 50. Classic Bridge Circuit V REF TO 0 ma SINGLE-SUPPLY RECEIVER Figure 5 shows how a signal from a 4 to 0 ma transducer can be interfaced to the ADuC8, a -bit ADC with an embedded microcontroller. The signal from a 4 to 0 ma transducer is single-ended, which initially suggests the need for a simple shunt resistor to convert the current to a voltage at the high impedance analog input of the converter. However, any line resistance in the return path (to the transducer) adds a current dependent offset error; therefore, the current must be sensed differentially. In this example, a 4.9 Ω shunt resistor generates a maximum differential input voltage to the of between 00 mv (for 4 ma in) and 500 mv (for 0 ma in). With no gain resistor present, the amplifies the 500 mv input voltage by a factor of 5, to.5 V, the full-scale input voltage of the ADC. The zero current of 4 ma corresponds to a code of 89 and the LSB size is 60 μa. THERMOCOUPLE AMPLIFIER Because the common-mode input range of the extends 0. V below ground, it is possible to measure small differential signals that have a low, or no, common-mode component. Figure 5 shows a thermocouple application where one side of the J-type thermocouple is grounded. Over a temperature range from 00 C to +00 C, the J-type thermocouple delivers a voltage ranging from mv to mv. A programmed gain on the of 00 (RG =. kω) and a voltage on the REF pin of V result in the output voltage of the ranging from.0 V to V relative to ground. For a different input range or different voltage on the REF pin, it is important to verify that the voltage on Internal Node A (see Figure 37) is not driven below ground. This can be checked using the equations in the Input Range Limitations in Single-Supply Applications section. 5V 0.µF J-TYPE THERMOCOUPLE.kΩ REF V REF Figure 5. Amplifying Bipolar Signals with Low Common-Mode Voltage Rev. D Page of 4

23 5V 5V 5V 0.µF 0.µF 0.µF V REF AV DD DV DD 4 0mA TRANSDUCER LINE IMPEDANCE 4 0mA 4.9Ω G = +5 REF AIN 0 to AIN 7 ADuC8 MICROCONVERTER AGND DGND Figure 5. 4 to 0 ma Receiver Circuit Rev. D Page 3 of 4

24 OUTLINE DIMENSIONS (0.6) (9.7) (9.0) 0.0 (5.33) MAX 0.50 (3.8) 0.30 (3.30) 0.5 (.9) 0.0 (0.56) 0.08 (0.46) 0.04 (0.36) (.78) (.5) (.4) (.54) BSC (7.) 0.50 (6.35) (6.0) 0.05 (0.38) MIN SEATING PLANE (0.3) MIN (.5) MAX 0.05 (0.38) GAUGE PLANE 0.35 (8.6) 0.30 (7.87) (7.6) (0.9) MAX 0.95 (4.95) 0.30 (3.30) 0.5 (.9) 0.04 (0.36) 0.00 (0.5) (0.0) 4.00 (0.574) 3.80 (0.497) 0.5 (0.0098) 0.0 (0.0040) COPLANARITY 0.0 SEATING PLANE 5.00 (0.968) 4.80 (0.890) (0.0500) BSC 6.0 (0.44) 5.80 (0.84).75 (0.0688).35 (0.053) 0.5 (0.00) 0.3 (0.0) (0.0098) 0.7 (0.0067) 0.50 (0.096) 0.5 (0.0099).7 (0.0500) 0.40 (0.057) 45 COMPLIANT TO JEDEC STANDARDS MS-00 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches (and millimeters) COMPLIANT TO JEDEC STANDARDS MS-0-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Small Standard Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters (and inches) 0407-A ORDERING GUIDE Model Temperature Range Package Description Package Option AN 40 C to +85 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 ANZ 40 C to +85 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AR 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 AR-REEL 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 AR-REEL7 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 ARZ 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 ARZ-R7 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 ARZ-RL 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 BN 40 C to +85 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 BNZ 40 C to +85 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 BR 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 BR-REEL 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 BR-REEL7 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 BRZ 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 BRZ-RL 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 BRZ-R7 40 C to +85 C 8-Lead Small Standard Outline [SOIC_N] R-8 Z = RoHS Compliant part. 007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /07(D) Rev. D Page 4 of 4