Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp AD822

Transcription

1 Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp FEATURES True Single-Supply Operation Output Swings Rail-to-Rail Input Voltage Range Extends Below Ground Single-Supply Capability from 3 V to 36 V Dual-Supply Capability from.5 V to 8 V High Load Drive Capacitive Load Drive of 35 pf, G = + Minimum Output Current of 5 ma Excellent AC Performance for Low Power 8 A Max Quiescent Current per Amplifier Unity Gain Bandwidth:.8 MHz Slew Rate of 3. V/ms Good DC Performance 8 V Max Input Offset Voltage 2 V/ C Typ Offset Voltage Drift 25 pa Max Input Bias Current Low Noise 3 nv/ khz No Phase Inversion APPLICATIONS Battery-Powered Precision Instrumentation Photodiode Preamps Active Filters 2- to -Bit Data Acquisition Systems Medical Instrumentation Low Power References and Regulators GENERAL DESCRIPTION The is a dual precision, low power FET input op amp that can operate from a single supply of 3. V to 36 V or dual supplies of ±.5 V to ± 8 V. It has true single-supply capability CONNECTION DIAGRAM 8-Lead Plastic DIP, MSOP, and SOIC OUT IN +IN V V+ OUT2 with an input voltage range extending below the negative rail, allowing the to accommodate input signals below ground in the Single-Supply Mode. Output voltage swing extends to within mv of each rail providing the maximum output dynamic range. Offset voltage of 8 mv maximum, offset voltage drift of 2 mv/ C, input bias currents below 25 pa, and low input voltage noise provide dc precision with source impedances up to a gigaohm..8 MHz unity gain bandwidth, 93 db THD at khz, and 3V/ms slew rate are provided with a low supply current of 8 ma per amplifier. The drives up to 35 pf of direct capacitive load as a follower and provides a minimum output current of 5 ma. This allows the amplifier to handle a wide range of load conditions. Its combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single-supply user. The is available in two performance grades. The A and B grades are rated over the industrial temperature range of C to +85 C. The is offered in three varieties of 8-lead packages: plastic PDIP, MSOP, and SOIC. IN2 +IN2 V V 2µs INPUT VOLTAGE NOISE nv/ HZ 5V V OUT V (GND) % V k k FREQUENCY Hz Figure. Input Voltage Noise vs. Frequency Figure 2. Gain-of-2 Amplifier; V S = 5,, V IN = 2.5 V Sine Centered at.25 V, R L = kw Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: 78/ Fax: 78/ Analog Devices, Inc. All rights reserved.

2 SPECIFICATIONS (V S =, 5 T A = 25 C, V CM = V, V OUT =.2 V, unless otherwise noted.) A B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset..8.. mv Max Offset over Temperature mv Offset Drift 2 2 mv/ C Input Bias Current V CM = V to V pa at T MAX na Input Offset Current pa at T MAX.5.5 na Open-Loop Gain V O =.2 V to V R L = kw 5 5 V/mV T MIN to T MAX V/mV R L = kw V/mV T MIN to T MAX 8 8 V/mV R L = kw V/mV T MIN to T MAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz 2 2 mv p-p f = Hz nv/ Hz f = Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kw to 2.5 V f = khz V O =.25 V to.75 V db DYNAMIC PERFORMANCE Unity Gain Frequency.8.8 MHz Full Power Response V O p-p =.5 V 2 2 khz Slew Rate 3 3 V/ms Settling Time to.% V O =.2 V to.5 V.. ms to.%.8.8 ms MATCHING CHARACTERISTICS Initial Offset..5 mv Max Offset over Temperature.6.3 mv Offset Drift 3 3 mv/ C Input Bias Current 2 pa f = khz R L = 5 kw 3 3 db f = khz db INPUT CHARACTERISTICS Input Voltage Range V T MIN to T MAX V Common-Mode Rejection Ratio (CMRR) V CM = V to 2 V db T MIN to T MAX V CM = V to 2 V db Input Impedance Differential W pf Common Mode W pf OUTPUT CHARACTERISTICS Output Saturation Voltage 2 V OL V EE I SINK = 2 ma mv T MIN to T MAX mv V CC V OH I SOURCE = 2 ma mv T MIN to T MAX 2 2 mv V OL V EE I SINK = 2 ma mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = 2 ma 8 8 mv T MIN to T MAX 6 6 mv V OL V EE I SINK = 5 ma mv T MIN to T MAX mv V CC V OH I SOURCE = 5 ma mv T MIN to T MAX mv Operating Output Current 5 5 ma T MIN to T MAX 2 2 ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current T MIN to T MAX ma Power Supply Rejection V S + = 5 V to 5 V db T MIN to T MAX 66 7 db Specifications subject to change without notice. 2

3 SPECIFICATIONS (V S = 5 T A = 25 C, V CM = V, V OUT = V, unless otherwise noted.) 3 A B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset..8.. mv Max Offset over Temperature mv Offset Drift 2 2 mv/ C Input Bias Current V CM = 5 V to + V pa at T MAX na Input Offset Current pa at T MAX.5.5 na Open-Loop Gain V O = V to + V R L = kw V/mV T MIN to T MAX V/mV R L = kw V/mV T MIN to T MAX 8 8 V/mV R L = kw V/mV T MIN to TMAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz 2 2 mv p-p f = Hz nv/ Hz f = Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kw f = khz V O = ±.5 V db DYNAMIC PERFORMANCE Unity Gain Frequency.9.9 MHz Full Power Response V O p-p = 9 V 5 5 khz Slew Rate 3 3 V/ms Settling Time to.% V O = V to ±.5 V.. ms to.%.8.8 ms MATCHING CHARACTERISTICS Initial Offset..5 mv Max Offset over Temperature 3 2 mv Offset Drift 3 3 mv/ C Input Bias Current 25 pa f = khz R L = 5 kw 3 3 db f = khz db INPUT CHARACTERISTICS Input Voltage Range V T MIN to T MAX V Common-Mode Rejection Ratio (CMRR) V CM = 5 V to +2 V db T MIN to T MAX V CM = 5 V to +2 V db Input Impedance Differential W pf Common Mode W pf OUTPUT CHARACTERISTICS Output Saturation Voltage 2 V OL V EE I SINK = 2 ma mv T MIN to T MAX mv V CC V OH I SOURCE = 2 ma mv T MIN to T MAX 2 2 mv V OL V EE I SINK = 2 ma mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = 2 ma 8 8 mv T MIN to T MAX 6 6 mv V OL V EE I SINK = 5 ma mv T MIN to T MAX mv V CC V OH I SOURCE = 5 ma mv T MIN to T MAX mv Operating Output Current 5 5 ma T MIN to T MAX 2 2 ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current T MIN to T MAX ma Power Supply Rejection V S + = 5 V to 5 V db T MIN to T MAX 66 7 db Specifications subject to change without notice.

4 SPECIFICATIONS (V S = 5 T A = 25 C, V CM = V, V OUT = V, unless otherwise noted.) A B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset mv Max Offset over Temperature mv Offset Drift 2 2 mv/ C Input Bias Current V CM = V pa V CM = V pa at T MAX V CM = V na Input Offset Current pa at T MAX.5.5 na Open-Loop Gain V O = + V to V R L = kw V/mV T MIN to T MAX 5 5 V/mV R L = kw 5 5 V/mV T MIN to T MAX V/mV R L = kw V/mV T MIN to T MAX 2 2 V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz 2 2 mv p-p f = Hz nv/ Hz f = Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kw f = khz V O = ± V db DYNAMIC PERFORMANCE Unity Gain Frequency.9.9 MHz Full Power Response V O p-p = 2 V 5 5 khz Slew Rate 3 3 V/ms Settling Time to.% V O = V to ± V.. ms to.%.5.5 ms MATCHING CHARACTERISTICS Initial Offset 3 2 mv Max Offset over Temperature 2.5 mv Offset Drift 3 3 mv/ C Input Bias Current 25 2 pa f = khz R L = 5 kw 3 3 db f = khz db INPUT CHARACTERISTICS Input Voltage Range V T MIN to T MAX V Common-Mode Rejection Ratio (CMRR) V CM = 5 V to +2 V db T MIN to T MAX V CM = 5 V to +2 V 7 7 db Input Impedance Differential W pf Common Mode W pf OUTPUT CHARACTERISTICS Output Saturation Voltage 2 V OL V EE I SINK = 2 ma mv T MIN to T MAX mv V CC V OH I SOURCE = 2 ma mv T MIN to T MAX 2 2 mv V OL V EE I SINK = 2 ma mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = 2 ma 8 8 mv T MIN to T MAX 6 6 mv V OL V EE I SINK = 5 ma mv T MIN to T MAX mv V CC V OH I SOURCE = 5 ma mv T MIN to T MAX mv Operating Output Current 2 2 ma T MIN to T MAX 5 5 ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current T MIN to T MAX ma Power Supply Rejection V S + = 5 V to 5 V db T MIN to T MAX 7 7 db Specifications subject to change without notice.

5 SPECIFICATIONS (V S =, 3 T A = 25 C, V CM = V, V OUT =.2 V, unless otherwise noted.) Parameter Conditions Typ Unit DC PERFORMANCE Initial Offset.2 mv Max Offset over Temperature.5 mv Offset Drift mv/ C Input Bias Current V CM = V to 2 V 2 pa at T MAX.5 na Input Offset Current 2 pa at T MAX.5 na Open-Loop Gain V O =.2 V to 2 V R L = kw V/mV R L = kw 5 V/mV R L = kw 3 V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise. Hz to Hz 2 mv p-p f = Hz 25 nv/ Hz f = Hz 2 nv/ Hz f = khz 6 nv/ Hz f = khz 3 nv/ Hz Input Current Noise. Hz to Hz 8 fa p-p f = khz.8 fa/ Hz Harmonic Distortion R L = kw to.5 V f = khz V O = ±.25 V 92 db DYNAMIC PERFORMANCE Unity Gain Frequency.5 MHz Full Power Response V O p-p = 2.5 V 2 khz Slew Rate 3 V/ms Settling Time to.% V O =.2 V to 2.5 V ms to.%. ms MATCHING CHARACTERISTICS Offset Drift 2 mv/ C f = khz R L = 5 kw 3 db f = khz 93 db INPUT CHARACTERISTICS CMRR V CM = V to V 7 db Input Impedance Differential 3.5 W pf Common Mode W pf OUTPUT CHARACTERISTICS Output Saturation Voltage 2 V OL V EE I SINK = 2 ma 5 mv V CC V OH I SOURCE = 2 ma mv V OL V EE I SINK = 2 ma mv V CC V OH I SOURCE = 2 ma 8 mv V OL V EE I SINK = ma 2 mv V CC V OH I SOURCE = ma 5 mv Capacitive Load Drive 35 pf POWER SUPPLY Quiescent Current.2 ma Power Supply Rejection V S + = 3 V to 5 V 8 db NOTES This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+V S V) to +V S. Common-mode error voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. 2 V OL V EE is defined as the difference between the lowest possible output voltage (V OL ) and the negative voltage supply rail (V EE ). V CC V OH is defined as the difference between the highest possible output voltage (V OH ) and the positive supply voltage (V CC ). Specifications subject to change without notice. 5

6 ABSOLUTE MAXIMUM RATINGS Supply Voltage ± 8 V Internal Power Dissipation 2 Plastic DIP (N) Observe Derating Curves SOIC (R) Observe Derating Curves Input Voltage (+V S +.2 V) to (2 V + V S ) Output Short Circuit Duration Indefinite Differential Input Voltage ± 3 V Storage Temperature Range (N) C to +25 C Storage Temperature Range (R, RM) C to +5 C Operating Temperature Range A/B C to +85 C Lead Temperature Range (Soldering, 6 sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-Lead Plastic DIP Package: JA = C/W 8-Lead SOIC Package: JA = 6 C/W 8-Lead MSOP Package: JA = C/W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the is limited by the associated rise in junction temperature. For plastic packages, the maximum safe junction temperature is 5 C. If these maximums are exceeded momentarily, proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the derating curves shown in TPC 2. While the is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. With power supplies ± 2 V (or less) at an ambient temperature of 25 C or less, if the output node is shorted to a supply rail, then the amplifier will not be destroyed, even if this condition persists for an extended period. ORDERING GUIDE Model* Temperature Range Package Description Package Option Branding Information AN C to +85 C 8-Lead PDIP N-8 AR C to +85 C 8-Lead SOIC R-8 ARM C to +85 C 8-Lead MSOP RM-8 BA BR C to +85 C 8-Lead SOIC R-8 *SPICE model is available at CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 6

7 7 6 V S = V, 5V Typical Performance Characteristics 5 NUMBER OF UNITS INPUT BIAS CURRENT pa V S = 5V V S = V, +5V, AND 5V OFFSET VOLTAGE mv COMMON-MODE VOLTAGE V TPC. Typical Distribution of Offset Voltage (3 Units) TPC. Input Bias Current vs. Common-Mode Voltage; V S = 5 V, V, and V S = ±5 V 6 k V S = 5V V S = 5V % IN BIN INPUT BIAS CURRENT pa OFFSET VOLTAGE DRIFT V/ C TPC 2. Typical Distribution of Offset Voltage Drift ( Units) COMMON-MODE VOLTAGE V TPC 5. Input Bias Current vs. Common-Mode Voltage; V S = ±5 V 5 5 k k NUMBER OF UNITS INPUT BIAS CURRENT pa k INPUT BIAS CURRENT pa TEMPERATURE C TPC 3. Typical Distribution of Input Bias Current (23 Units) TPC 6. Input Bias Current vs. Temperature; V S = 5 V, V CM = 7

8 M V S = 5V 2 R L = 2k R L = 2k POS RAIL PEN-LOOP GAIN V/V M k V S = V, 5V V S = V, 3V INPUT VOLTAGE V 2 POS RAIL POS RAIL NEG RAIL NEG RAIL R L = k k k k LOAD RESISTANCE k NEG RAIL OUTPUT VOLTAGE FROM SUPPLY RAILS mv TPC 7. Open-Loop Gain vs. Load Resistance TPC. Input Error Voltage with Output Voltage within 3 mv of Either Supply Rail for Various Resistive Loads; V S = ±5 V M k OPEN-LOOP GAIN V/V M k R L = k R L = k R L = 6 V S = 5V V S = V, 5V V S = 5V V S = V, 5V V S = 5V INPUT VOLTAGE NOISE nv/ HZ V S = V, 5V k TEMPERATURE C TPC 8. Open-Loop Gain vs. Temperature k k FREQUENCY Hz TPC. Input Voltage Noise vs. Frequency R L = k A CL = INPUT VOLTAGE V R L = k R L = k R L = OUTPUT VOLTAGE V THD db 6 7 V S = V, 3V; V OUT = 2.5V p-p 8 V S = 5V; V OUT = 2V p-p V S = 5V; V OUT = 9V p-p V S = V, 5V; V OUT =.5V p-p k k k FREQUENCY Hz TPC 9. Input Error Voltage vs. Output Voltage for Resistive Loads TPC 2. Total Harmonic Distortion vs. Frequency 8

9 OPEN-LOOP GAIN db R L = 2k C L = pf GAIN PHASE PHASE MARGIN IN DEGREES COMMON-MODE REJECTION db V S = V, 3V V S = 5V V S = V, 5V 2 2 k k k M M FREQUENCY Hz k k k M FREQUENCY Hz M TPC 3. Open-Loop Gain and Phase Margin vs. Frequency TPC 6. Common-Mode Rejection vs. Frequency OUTPUT IMPEDANCE k. A CL = + V S = 5V. k k k M M FREQUENCY Hz COMMON-MODE ERROR VOLTAGE mv NEGATIVE RAIL +25 C POSITIVE RAIL +25 C 55 C 55 C +25 C 2 3 COMMON-MODE VOLTAGE FROM SUPPLY RAILS V TPC. Output Impedance vs. Frequency TPC 7. Absolute Common-Mode Error vs. Common-Mode Voltage from Supply Rails (V S V CM ) 6 2 OUTPUT SWING FROM TO VOLTS % %.%.% ERROR.% OUTPUT SATURATION VOLTAGE mv V S V OH V OL V S SETTLING TIME s TPC 5. Output Swing and Error vs. Settling Time... LOAD CURRENT ma TPC 8. Output Saturation Voltage vs. Load Current 9

10 OUTPUT SATURATION VOLTAGE mv I SOURCE = ma I SINK = ma I SOURCE = ma I SINK = ma I SOURCE = A I SINK = A POWER SUPPLY REJECTION db PSRR PSRR TEMPERATURE C TPC 9. Output Saturation Voltage vs. Temperature k k k M M FREQUENCY Hz TPC 22. Power Supply Rejection vs. Frequency V S = 5V 25 R L = 2k SHORT CIRCUIT CURRENT LIMIT ma V S = 5V V S = V, 5V V S = V, 3V V S = V, 5V V S = V, 3V OUT OUTPUT VOLTAGE V V S = V, 5V V S = V, 3V V S = 5V TEMPERATURE C TPC 2. Short Circuit Current Limit vs. Temperature k k M M FREQUENCY Hz TPC 23. Large Signal Frequency Response QUIESCENT CURRENT A T = +25 C T = +25 C T = 55 C TOTAL SUPPLY VOLTAGE V TPC 2. Quiescent Current vs. Supply Voltage vs. Temperature TOTAL POWER DISSIPATION W LEAD SOIC 8-LEAD MSOP 8-LEAD PDIP AMBIENT TEMPERATURE C TPC 2. Maximum Power Dissipation vs. Temperature for Plastic Packages

11 7 8 V OUT CROSSTALK db 2 3 2V p-p V IN 2 3 +V S 8 /2. F F /2 7 5k CROSSTALK = 2LOG V OUT V IN 5k 2k V S 6 5. F 2.2k F 3 k 3k k 3k k 3k M FREQUENCY Hz TPC 25. Crosstalk vs. Frequency TPC 28. Crosstalk Test Circuit 5V 5µs /2 +V S. F 8 V IN. F R L pf V OUT % TPC 26. Unity Gain Follower TPC 29. Large Signal Response Unity Gain Follower; V S = ±5 V, R L = kw 5V µs mv 5ns % % TPC V p-p, 25 khz Sine Wave Input; Unity Gain Follower; R L = 6 W, V S = ±5 V TPC 3. Small Signal Response Unity Gain Follower; V S = ±5 V, R L = kw

12 V 2µs V 2µs GND % GND % TPC 3. V S = 5 V, V; Unity Gain Follower Response to V to V Step TPC 3. V S = 5 V, V; Unity Gain Follower Response to V to 5 V Step mv 2µs +V S. F V IN 8 /2 R L pf V OUT GND % TPC 32. Unity Gain Follower TPC 35. V S = 5 V, V; Unity Gain Follower Response, to mv Step Centered mv above Ground, R L = kw mv 2µs V IN k +V S 2k V OUT. F 8 /2 R L pf GND % TPC 33. Gain-of-T2 Inverter TPC 36. V S = 5 V, V; Gain-of-2 Inverter Response to 2 mv Step, Centered 2 mv below Ground, R L = kw 2

13 V 2µs V µs GND % GND % V TPC 37. V S = 5 V, V; Gain-of-2 Inverter Response to 2.5 V Step Centered.25 V below Ground, R L = kw (a) 5mV µs +V S V V µs GND % GND % V (b) TPC 38. V S = 3 V, V; Gain-of-2 Inverter, V IN =.25 V, 25 khz, Sine Wave Centered at.75 V, R L = 6 W R P 5V V IN V OUT TPC 39. (a) Response with R P = ; V IN from to +V S (b) V IN = to +V S + 2 mv V OUT = to +V S R P = 9.9 kw APPLICATION NOTES Input Characteristics In the, n-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input common-mode voltage extends from.2 V below V S to V less than +V S. Driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in TPCs 3 and 3) and increased common-mode voltage error as illustrated in TPC 7. The does not exhibit phase reversal for input voltages up to and including +V S. TPC 39a shows the response of an voltage follower to a V to 5 V (+V S ) square wave input. The input and output are superimposed. The output tracks the input up to +V S without phase reversal. The reduced bandwidth above a V input causes the rounding of the output waveform. For input voltages greater than +V S, a resistor in series with the s 3 noninverting input will prevent phase reversal, at the expense of greater input voltage noise. This is illustrated in TPC 39b. Since the input stage uses n-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than +V S. V, the input current will reverse direction as internal device junctions become forward biased. This is illustrated in TPC. A current limiting resistor should be used in series with the input of the if there is a possibility of the input voltage exceeding the positive supply by more than 3 mv, or if an input voltage will be applied to the when ± V S =. The amplifier will be damaged if left in that condition for more than seconds. A kw resistor allows the amplifier to withstand up to V of continuous overvoltage and increases the input voltage noise by a negligible amount.

14 Input voltages less than V S are a completely different story. The amplifier can safely withstand input voltages 2 V below the negative supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. The is designed for 3 nv/ Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to TPC ). This noise performance, along with the s low input current and current noise, means that the contributes negligible noise for applications with source resistances greater than kw and signal bandwidths greater than khz. This is illustrated in Figure 3. INPUT VOLTAGE NOISE V k k k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. khz RESISTOR JOHNSON NOISE Hz AMPLIFIER-GENERATED NOISE. k k M M M G G SOURCE IMPEDANCE Figure 3. Total Noise vs. Source Impedance Output Characteristics The s unique bipolar rail-to-rail output stage swings within 5 mv of the negative supply and mv of the positive supply with no external resistive load. The s approximate output saturation resistance is W sourcing and 2 W sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing 5 ma, the saturation voltage to the positive supply rail will be 2 mv; when sinking 5 ma, the saturation voltage to the negative rail will be mv. The amplifier s open-loop gain characteristic will change as a function of resistive load, as shown in TPCs 7 to. For load resistances over 2 kw, the s input error voltage is virtually unchanged until the output voltage is driven to 8 mv of either supply. If the s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 ms of its input returning to the amplifier s linear operating region. Direct capacitive loads will interact with the amplifier s effective output impedance to form an additional pole in the amplifier s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figure shows the s pulse response as a unity gain follower driving 35 pf. This amount of overshoot indicates approximately 2 degrees of phase margin the system is stable but is nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects mV 2µs % Figure. Small Signal Response of as Unity Gain Follower Driving 35 pf Figure 5 is a plot of capacitive load that will result in a 2 phase margin versus noise gain for the. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. R F NOISE GAIN + R k 3k k 3k CAPACITIVE LOAD FOR 2 O PHASE MARGIN pf R Figure 5. Capacitive Load Tolerance vs. Noise Gain Figure 6 shows a method for extending capacitance load drive capability for a unity gain follower. With these component values, the circuit will drive 5, pf with a % overshoot. V IN +V S 8 /2. F V S 2k. F 2pF R F Figure 6. Extending Unity Gain Follower Capacitive Load Capability Beyond 35 pf C L C L V OUT

15 APPLICATIONS Single-Supply Voltage-to-Frequency Converter The circuit shown in Figure 7 uses the to drive a low power timer that produces a stable pulse of width t. The positive going output pulse is integrated by R C and used as one input to the that is connected as a differential integrator. The other input (nonloading) is the unknown voltage, V IN. The output drives the timer trigger input, closing the overall feedback loop. +V C5. F 2 3 V IN 6 5 U REF2 V REF = 5V R2 99k % R 99k % C2. F, 2% V TO 2.5V FULL SCALE R SCALE ** k U CMOS 7HCO U3B. F, 2% C /2 B U3A 3 2 R3* 6k C3. F U2 CMOS R V+ THR OUT 3 TR 5 CV DIS GND NOTES f OUT = V IN /(V REF t ), t =. R3 C6 = 25kHz F S AS SHOWN * = % METAL FILM, <5ppm/ C TC ** = % 2T FILM, <ppm/ C TC t = 33 s FOR f OUT = V IN = 2.V OUT2 OUT C. F Figure 7. Single-Supply Voltage-to-Frequency Converter Typical bias currents of 2 pa allow megohm-range source impedances with negligible dc errors. Linearity errors on the order of.% full scale can be achieved with this circuit. This performance is obtained with a 5 V single supply that delivers less than ma to the entire circuit. Single-Supply Programmable Gain Instrumentation Amplifier The can be configured as a single-supply instrumentation amplifier that is able to operate from single supplies down to 3 V or dual supplies up to ± 5 V. Using only one rather than three separate op amps, this circuit is cost and power efficient. FET inputs 2 pa bias currents minimize offset errors caused by high unbalanced source impedances. An array of precision thin-film resistors sets the in amp gain to be either or. These resistors are laser trimmed to ratio match to.% and have a maximum differential TC of 5 ppm/ C. Table I. In Amp Performance Parameters V S = 3 V, V V S = 65 V CMRR 7 db 8 db Common-Mode Voltage Range.2 V to +2 V 5.2 V to + V 3 db BW, G = 8 khz 8 khz G = 8 khz 8 khz t SETTLING 2 V Step (V S = V, 3 V) 2 ms 5 V (V S = ± 5 V) 5 ms f = khz, G = 27 nv/ Hz 27 nv/ Hz G = 2.2 mv/ Hz 2.2 mv/ Hz I SUPPLY (Total). ma.5 ma V REF V IN V IN % V Figure 8a. Pulse Response of In Amp to a 5 mv p-p Input Signal; V S = 5 V, V; Gain = R P k R k R2 9k R3 k R k R5 9k 5µs R6 k G = G = G = G = R P k 2 3 +V S. F /2 /2 R6 (G = ) V OUT = (V IN V IN2 ) + +V REF R + R5 R5 + R6 (G = ) V OUT = (V IN V IN2 ) + +V REF R Figure 8b. A Single-Supply Programmable Instrumentation Amplifier OHMTEK PART # 3 V OUT 5

16 3 V, Single-Supply Stereo Headphone Driver The exhibits good current drive and THD + N performance, even at 3 V single supplies. At khz, total harmonic distortion plus noise (THD + N) equals 62 db (.79%) for a 3 mv p-p output signal. This is comparable to other singlesupply op amps that consume more power and cannot run on 3V power supplies. F MYLAR CHANNEL 95.3k 95.3k 7.5k 3V k /2 k.99k.99k. F 5 F +. F HEADPHONES 32 IMPEDANCE L R Low Dropout Bipolar Bridge Driver The can be used for driving a 35 W Wheatstone bridge. Figure shows one half of the being used to buffer the AD589 a.235 V low power reference. The output of.5 V can be used to drive an A/D converter front end. The other half of the is configured as a unity gain inverter and generates the other bridge input of.5 V. Resistors R and R2 provide a constant current for bridge excitation. The AD62 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. The gain of the AD62 is programmed using an external resistor RG and determined by: 9.9k +.235V AD589 +V s /2 9. kw G = + R 2 R G TO A/D CONVERTER REFERENCE INPUT CHANNEL 2 F MYLAR 7.5k /2 5 F k % 25.k % V S Figure 9. 3 V Single-Supply Stereo Headphone Driver In Figure 9, each channel s input signal is coupled via a mf Mylar capacitor. Resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway between the power supplies (.5 V). The gain is.5. Each half of the can then be used to drive a headphone channel. A 5 Hz high-pass filter is realized by the 5 mf capacitors and the headphones that can be modeled as 32 W load resistors to ground. This ensures that all signals in the audio frequency range (2 Hz to 2 khz) are delivered to the headphones. k % k % / R G.5V R2 2 V s AD62 V REF V S +V s +5V + +. F F GND + +. F F V s 5V Figure. Low Dropout Bipolar Bridge Driver 6

17 OUTLINE DIMENSIONS 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters).375 (9.53).365 (9.27).355 (9.2).8 (.57) MAX (7.9).285 (7.2).275 (6.98). (2.5) BSC.5 (.38) MIN.5 (3.8).3 (3.3) SEATING PLANE. (2.79).6 (.52).22 (.56).5 (.27).8 (.6).5 (.). (.36).325 (8.26).3 (7.87).3 (7.62).5 (3.8).35 (3.3).2 (3.5).5 (.38). (.25).8 (.2) COMPLIANT TO JEDEC STANDARDS MO-95AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5. (.968).8 (.8) 8-Lead microsoic Package [MSOP] (RM-8) Dimensions shown in millimeters 3. BSC. (.57) 3.8 (.97) (.2) 5.8 (.228) 3. BSC 8 5. BSC.25 (.98). (.) COPLANARITY..27 (.5) BSC SEATING PLANE.75 (.688).35 (.532).5 (.2).33 (.3).25 (.98).9 (.75) 8.5 (.96) 5.25 (.99).27 (.5). (.6) COMPLIANT TO JEDEC STANDARDS MS-2AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.5. PIN.65 BSC COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87AA.8. 7

18 Revision History Location Page /3 Data sheet changed from REV. D to Edits to SPECIFICATIONS Edits to Figure Updated OUTLINE DIMENSIONS /2 Data sheet changed from REV. C to REV. D Edits to FEATURES Edits to ORDERING GUIDE Updated SOIC PACKAGE OUTLINE /2 Data sheet changed from REV. B to REV. C All figures updated Global Edits to FEATURES Updated all PACKAGE OUTLINES / Data sheet changed from REV. A to REV. B All figures updated Global Cerdip references removed , 6, and 8 Additions to PRODUCT DESCRIPTION Lead SOIC and 8-Lead MSOP Diagrams added Deletion of S column Edits to ABSOLUTE MAXIMUM RATINGS and ORDERING GUIDE Removed Metalization Photograph

19 9

20 PRINTED IN U.S.A. C87 /3(E) 2