OBSOLETE. Parameter AD9621 AD9622 AD9623 AD9624 Units

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1 a FEATURES MHz Small Signal Bandwidth MHz Large Signal BW ( V p-p) High Slew Rate: V/ s Low Distortion: MHz Fast Settling: ns to.%. nv/ Hz Spectral Noise Density V Supply Operation Wideband Voltage Feedback Amplifier AD9* CONNECTION DIAGRAM APPLICATIONS ADC Input Signal Amplifier Differential Amplifiers IF/RF Amplifiers Pulse Amplifiers Professional Video DAC Current-to-Voltage Baseband and Video Communications Active Filters/lntegrators/Log Amps GENERAL DESCRIPTION The AD9 is one of a family of very high speed and wide bandwidth amplifiers utilizing a voltage feedback architecture. These amplifiers define a new level of performance for voltage feedback amplifiers, especially in the categories of large signal bandwidth, slew rate, settling, low distortion, and low noise. Proprietary design architectures have resulted in an amplifier family that combines the most attractive attributes of both current feedback and voltage feedback amplifiers. The AD9 exhibits extraordinarily accurate and fast pulse response characteristics ( ns settling to.%) as well as extremely wide small and large signal bandwidth previously found only in current feedback amplifiers. When combined with balanced high impedance inputs and low input noise current more common to voltage feedback architectures, the AD9 offers performance not previously available in a monolithic operational amplifier. *Protected by U.S. Patent,,7 and others pending. NC # INPUT +INPUT AD9 7 NC # OUTPUT NC # OPTIONAL CAPACITOR CB CONNECTED HERE DECREASES SETTLING TIME (SEE TEXT). Other members of the AD9X amplifier family are the AD9 (G = +), AD9 (G = +), and the AD9 (G = +). A separate data sheet is available from Analog Devices for each model. Each generic device has been designed for a different minimum stable gain setting, allowing users flexibility in optimizing system performance. Dynamic performance specifications such as slew rate, settling time, and distortion vary from model to model. The table below summarizes key performance attributes for the AD9X family and can be used as a selection guide. The AD9 is offered in industrial and military temperature ranges. Industrial versions are available in plastic DIP, SOIC, and cerdip; MIL versions are packaged in cerdips. PRODUCT HIGHLIGHTS. Wide Large Signal Bandwidth. High Slew Rate. Fast Settling. Low Distortion. Output Short-Circuit Protected. Low Intermodulation Distortion of High Frequencies Parameter AD9 AD9 AD9 AD9 Units Minimum Stable Gain V/V Harmonic Distortion ( MHz) db Large Signal Bandwidth ( V p-p) 9 MHz SSBW (. V p-p) 7 MHz Slew Rate V/µs Rise/Fall Time (. V Step)..7.. ns Settling Time (to.%/.%) 7/ / / / ns Input Noise (. MHz MHz) 9 µv rms Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7/9-7 Fax: 7/-7

2 AD9 SPECIFICATIONS DC ELECTRICAL CHARACTERISTICS ( V S = V, OAD = Ω; A V =, = 7 Ω unless otherwise noted) Test AD9AN/AQ/AR AD9SQ Parameter Conditions Temp Level Min Typ Max Min Typ Max Units DC SPECIFICATIONS Input Offset Voltage + C I ± + ± + mv Full VI + + mv Input Bias Current + C I 7 7 µa Full VI µa Bias Current TC Full V na/ C Input Offset Current + C I ±. + ±. + µa Full VI + + µa Offset Current TC Full V.. na/ C Input Resistance + C V kω Input Capacitance + C V.. pf Common-Mode Range Full VI ±. ±. ±. ±. V Common-Mode Rejection Ratio V CM = V + C I db Open-Loop Gain = ± V p-p + C V db Output Voltage Range Full VI ±. ±. ±. ±. V Output Current Full VI 7 7 ma Output Resistance + C V.. Ω FREQUENCY DOMAIN Bandwidth ( db) Small Signal. V p-p Full II MHz Large Signal V p-p + C V MHz Amplitude of Peaking Full Spectrum Full II.... db Amplitude of Roll-off DC to MHz Full II.. db Phase Nonlinearity. to MHz + C V.. Degree nd Harmonic Distortion V p-p; MHz Full II dbc rd Harmonic Distortion V p-p; MHz Full II dbc Common-Mode Rejection MHz + C V + + db Spectral Input Noise Voltage to MHz + C V.. nv/ Hz Spectral Input Noise Current to MHz + C V.. pa/ Hz Average Equivalent Integrated Input Noise Voltage. to MHz + C V 9 9 µv rms TIME DOMAIN Slew Rate = V Step Full IV V/µs Rise/Fall Time =. V Step + C V.7.7 ns = V Step Full IV.... ns Overshoot = V Step Full IV % Settling Time To.% = V Step + C V ns To.% = V Step Full IV 9 9 ns To.% = V Step + C V ns To.% = V Step + C V 7 7 ns Overdrive Recovery to ± mv + C V ns Differential Gain (. MHz) = Ω + C V.. % Differential Phase (. MHz) = Ω + C V <. <. Degree POWER SUPPLY REQUIREMENTS Supply Voltage (±V S ) Full IV V Quiescent Current +I S = + V Full VI 9 9 ma I S = V Full VI 9 9 ma Power Supply Rejection Ratio V S =. V + C I db NOTES Measured at A V =. Effective large signal bandwidth; the device should not be stressed above V MHz ( p-p Frequency) to ensure long term reliability. Measured with a. µf C B capacitor connected across Pins and. Specifications subject to change without notice.

3 AD9 ABSOLUTE MAXIMUM RATINGS Supply Voltages (±V S ) ± V Common-Mode Input Voltage ±V S Voltage Swing Bandwidth Product V MHz Differential Input Voltage V Continuous Output Current ma Operating Temperature Ranges AN, AQ, AR C to + C SQ C to + C Storage Temperature Ceramic C to + C Plastic C to + C Junction Temperature Ceramic C Plastic C Lead Soldering Temperature ( minute) C NOTES Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. Output is short-circuit protected; for maximum reliability, 9 ma continuous current should not be exceeded. Typical thermal impedances (part soldered onto board; no air flow): Ceramic DIP: θ JA = C/W; θ JC = C/W Plastic SOIC: θ JA = C/W; θ JC = C/W Plastic DIP: θ JA = 9 C/W; θ JC = C/W Temperature shown is for surface mount devices, mounted by vapor phase soldering. Throughhole devices (ceramic and plastic DIPs) can be soldered at + C for seconds. ORDERING GUIDE Temperature Package Package Model Range Description Option AD9AN C to + C -Pin Plastic DIP N- AD9AQ C to + C -Pin Cerdip Q- AD9AR C to + C -Pin SOIC R- AD9SQ C to + C -Pin Cerdip Q- EXPLANATION OF TEST LEVELS Test Level I % production tested. II % production tested at + C, and sample tested at specified temperatures. AC testing of A grade devices done on sample basis. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI All devices are % production tested at + C. % production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. OUTPUT THEORY OF OPERATION The AD9 is a wide bandwidth voltage feedback amplifier that is guaranteed for minimum gain stability of +. Since its open-loop frequency response follows the conventional db/ octave roll-off, its gain bandwidth product is basically constant. Increasing its closed-loop gain results in a corresponding decrease in small signal bandwidth. The AD9 typically maintains a degree unity loop gain phase margin with 7 Ω. This high margin minimizes the effects of signal and noise peaking. Feedback Resistor Choice At minimum stable gain (+), the AD9 provides optimum dynamic performance with = 7 Ω. When using this value and following the high speed layout guidelines, a shunt capacitor (C F ) should not be required. This value for provides the best combination of wide bandwidth, low peaking, and distortion. However, if improved gain flatness is desired, a shunt capacitor (C F ) will provide extra phase margin. This reduces both overshoot and peaking with only a slight reduction of bandwidth. As an example, if the amplifier exhibits (worst case) peaking of db with = Ω (A V = ), then using a C F of. pf across will reduce this peaking to db. In addition, overshoot, noise, and settling time (.%) will also improve. This comes at the expense of slightly decreased closed-loop bandwidth due to the C F time constant created. If the equivalent input capacitance greatly exceeds pf (due to source drive or long input traces to the amplifier), then added shunt capacitance (C F ) will be necessary to maintain stability. Likewise, if larger / minimum-gain setting resistors are used, C F will be necessary. As a rule of thumb, if the product of C I 7 seconds, then C F is not required (for maximum bandwidth applications) and the amplifier s phase margin will maintain about. For > Ω, use a C F equal to C I /. As the value of increases, the bandwidth of the amplifier will begin to be controlled by the C F time constant. Increasing C F much beyond these guidelines will also cause amplifier instability. Pulse Unlike a traditional voltage feedback amplifier in which slew speed is usually dictated by its front end dc quiescent current and gain bandwidth product, the AD9 provides on demand transconductance current that increases proportionally to the input step signal amplitude. This results in slew speeds ( V/µs) comparable to wideband current feedback designs. This, combined with relatively low input noise current (. pa/ Hz), gives the AD9 the best attributes of both voltage and current feedback amplifiers. Bootstrap Capacitor (C B ) In most applications, the C B capacitor should not be required. Under certain conditions, it can be used to further enhance settling time performance. CB+ INPUT.mm mils CB INPUT +INPUT.mils Chip Layout

4 AD9.µF.µF V IN 7.µF C B (OPTIONAL) C F V IN 7.µF C B (OPTIONAL) C F.µF Ω.µF Ω.µF A V = Figure. Inverting Gain Connection Diagram.µF A V = + Figure. Noninverting Gain Connection Diagram The C B capacitor (. µf) connects to the internal high impedance nodes of the amplifier. Using this capacitor will reduce the large signal ( V) step output settling time by ns to ns for.% or greater accuracy. For settling accuracy less than.% or for smaller step sizes, its effect will be less apparent. Under heavy slew conditions, this capacitor forces the internal signal (initial step) amplitude to be controlled by the on (slewed) transistor, preventing its complement from completely turning off. This allows for faster settling time of these internal nodes and also the output. In the frequency domain, total (high frequency) distortion will be approximately the same with or without C B. Typically, the rd harmonic will be greater than the nd without C B. This will be reversed with C B in place. APPLICATIONS The AD9 is a voltage feedback amplifier and is well suited for such applications as active filters, and log amplifiers. The device s wide bandwidth ( MHz), phase margin ( ), low noise current (. pa / Hz), and slew rate ( V/µs) give higher performance capabilities to these applications over previous voltage feedback designs. With a settling time of ns to.% and ns to.%, the device is an excellent choice for DAC I/V conversion. The same characteristics along with low harmonic distortion make it a good choice for ADC buffering/ amplification. With its superb linearity at relatively high signal frequencies, it is an ideal driver for ADCs up to bits. Layout Considerations As with all wide bandwidth components, printed circuit layout is critical to obtain best dynamic performance with the AD9. The ground plane in the area of the amplifier and its associated components should cover as much of the component side of the board as possible (or first interior layer of a multilayer surface mount board). The ground plane should be removed in the area of the inputs and and to minimize stray capacitance at the input. The same precaution should be used for C B, if used. Each power supply trace should be decoupled close to the package with a. µf ceramic capacitor, plus a. µf tantalum nearby. All lead lengths for input, output, and feedback resistor should be kept as short as possible. All gain setting resistors should be chosen for low values of parasitic capacitance and inductance, i.e., microwave resistors and/or carbon resistors. Microstrip techniques should be used for lead lengths in excess of one inch. Sockets should be avoided if at all possible because of their high series inductance. If sockets are necessary, individual pin sockets such as AMP p/n -- should be used. These contribute far less stray reactance than molded socket assemblies. An evaluation board is available from Analog Devices for a nominal charge.

5 NOISE VOLTAGE nv/ Hz NOISE CURRENT pa Hz SUPPLY CURRENT ma OUTPUT LEVEL ± Volts R S Ohms t SETTLING TO.% ns MAGNITUDE db SETTLING PERCENTAGE SETTLING PERCENTAGE dbc INTERCEPT (+dbm) POWER SUPPLY AND COMMON-MODE REJECTION RATIOS db OPEN-LOOP GAIN db MAGNITUDE db MAGNITUDE db Typical Performance ( = Ω; A V = +, unless otherwise noted) AD PHASE GAIN k k M M M M FREQUENCY Hz Figure. Open-Loop Gain and Phase 7 nd HARMONIC = Ω = V p-p A V = A V = Figure. Inverting Frequency OUT A V =,, A V = A V = A V = Figure. Noninverting Frequency nd HARMONIC = Ω rd HARMONIC = Ω rd HARMONIC = Ω Figure. Harmonic Distortion vs. Frequency Figure 7. Third Order Intercept CMRR PSRR +7 k k k M M M G FREQUENCY Hz Figure. CMRR and PSRR vs. Frequency + AV = B = 7Ω F = 7Ω OAD = Ω TEST CIRCUIT Ω pf = V STEP... = V STEP TEST CIRCUIT Ω pf OAD = Ω Figure 9. Frequency vs. OAD.. TIME ns Figure. Short-Term Settling Time.. K K K TIME ns Figure. Long-Term Settling Time 7 VOLTAGE R S VOLTAGE CURRENT 7 7 k C L R S 9 CURRENT t SETTLING FREQUENCY Hz Figure. Input Spectral Noise Density.... SUPPLY VOLTAGE ±Volts Figure. Output Level and Supply Current vs. Supply Voltage. C LOAD pf Figure. Settling Time vs. Capacitive Load

6 .V/DIV mv/div SETTLING TIME ns AD9 9 V.V 7 TO.% OAD = Ω = V p-p OAD = Ω OAD = Ω = V p-p =.V p-p V.V INPUT RISE/FALL TIME =.ns INPUT RISE/FALL TIME =.ns ns/div ns/div NONINVERTING GAIN Figure. Large Signal Pulse Cerdip (Suffix Q) Figure. Small Signal Pulse MECHANICAL INFORMATION Dimensions shown in inches and (mm). Figure 7. Settling Time vs. Noninverting Gain Plastic DIP (Suffix N) C7 /9. (.) MIN. (.) MAX PIN. (.) MAX. (.). (.). (.). (.). (.9) MAX. (.) BSC.7 (.7). (.7). (7.7). (.9). (.). (.). (.) MIN SEATING PLANE TO. (.).9 (7.7). (.). (.) PIN. (.) MIN. (.).(.). (9.). (.). (.) BSC. (.9). (.). (.) MAX. (.). (.7) SEATING PLANE.9 (7.). (7.7) -. (.). (.). (.). (.) Plastic SOIC (Suffix R).9 (.). (.7). (.7) TYP. (.). (.). (.). (.). (.). (.). (.). (.) PRINTED IN U.S.A.. (.). (.).9 (.7). (.). (.).7 (.). (.). (.)