Ultra Low Inductance Package for SiC & GaN

Transcription

1 Ultra Low Inductance Package for SiC & GaN Dr.-Ing. Eckart Hoene Powered by

2 Overview The Motivation The Modules The Semiconductors The Measurement Equipment The Simulation The Results The Conclusion

3 Motivation Semiconductors made of high band gap material are a step further towards to ideal switch The switching behavior of an ideal switch is dominated by the electromagnetic properties of its package How can we adapt the semiconductor packaging technologies and the design concept to the upcomming needs?

4 Motivation Design goals are e.g. low DC-link inductance values or reduced electromagnetic interference spreading out from the switch In power electronics well known strategy to reduce inductance is the bus bar design: i fwd i back Two flat conductors with 0.5mm distance, 30mm width and 10cm length show a return inductance of 2.1nH d L * l * * in µh B l : length of the conductors in cm d B : distance : width of of the conductors conductors

5 The more conventional style module Idea: using wire bonds for semiconductor interconnection and bus bars for DC link Low inductance interconnect between module and PCB with DC capacitors

6 The more conventional style module Internal module Busbars Screw PCB Path of the DC link current DBC Semiconductors Cross section through the module including PCB and pressed interconnection

7 The more conventional style module System setup Driver board DC link

8 The embedded module Current measurement DC link capacitors Full bus bar structure using PCB Process on a DBC DCB DC- JFET Gates Out DC+ DC capacitors on the module DC link current measurement included Diode Abb. 1: Explosionsansicht des Modulaufbaus

9 The embedded module 3 active layers (DBC, Interlayer 60µm, Toplayer 100µm) Semiconductors sintered on bottom and stud bumps on top to be compatible with galvanisation 1.8µF on module 100 µm Toplayer 100 µm Prepreg 60 µm Interlayer 100 µm Preprag + Stud Bumps 300 µm Chip 100 µm Solder 300 µm Copper 380 µm Al 2 O µm Copper

10 Low Induction - Process Flow Step 1 Assembly the J-Fets on the DCB by sintering Step 2 Bonding gold-stud-bumbs on the aluminium pads To handle single DCB-ceramics with 2cm x 3cm outline in a production line it is needed a transport substrate Step 3 production of a transport substrate and mounting the DCBs on it Step 4 Lamination of prepregs and Cu-foil for the middle layer The best possible method to contact the Au-stud-bumps is by mechanical milling Step 5 Depth controlled milling through the epoxy exactly into the bumps and drilling of the first blind vias

11 Low Induction - Process Flow Step 6 Galvanic deposition of a copper layer with a thickness of 60µm in preparation to lamination of the photo resist it is required a Step 7 Printing of a paste in the cavities to equalize the surface Step 8 Structuring the copper middle layer over the J-Fets by exposure and chemical etching Step 9 Second lamination of prepreg and Cu-foil for the top layer Step 10 Drilling of blind vias to the ground and the middle layer

12 Low Induction - Process Flow Step 11 Galvanic deposition of a copper layer with a thickness of 100µm Step 12 Structuring the top layer by etching Step 13 Singularize the modules by milling

13 The embedded module DC- Driver Output DC+ Mounts for Voltage Probes

14 The embedded module

15 The Semiconductors First selection: Semisouth normally off (47mΩ/1200V) with a schottky free wheeling diode and a Semisouth driver. This configuration could not be brought to work within the restricted number of modules produced Second selection: Infineon 100mΩ/1200V with included parasitic freewheeling diode. All shown measurements were carried out with this semiconductors

16 The Measurement Equipment Current path Requirements: high bandwidth, low influence on setup, high noise immunity Solution for current sensor: A Rogowski coil placed in an Ω-shaped brass tube, the voltage across the coil measured with a 1GHz low capacitance probe and an oscilloscope Achieved bandwidth: 500MHz Shielded construction 300pH added inductance

17 The Simulation DC link inductance of the conventional module

18 The Simulation Embedded module L 0.67 nh ( without _ primary _ coil) comm L 1.1 nh ( with _ primary _ coil) L comm coil, prim. 0.43nH

19 The Results Embedded module V_DS I_Coil V_Shunt

20 The Results Embedded module Switch on at 0A: Voltage slope 10V/ns Current peak due to internal capacitance I D (1Vs = 1A)

21 The Results Embedded module Switch off at 20A: Voltage slope 22V/ns Current slope max. 4A/ns (50% to 90%) Low overshot (approx. 10V) very little ringing (frequency 240 MHz) I D (1Vs = 1A)

22 The Results Embedded module Switch on at 20A: Voltage slope 10V/ns Current slope 3.13A/ns I D (1Vs = 1A)

23 The Results Damped oscillation after turn-off Turn-off 40V f C res oss MHz 522 pf 1 f res Lcomm 0.866nH 2 C L oss comm Determining of the commutation inductance

24 The Results Observation: Parasitic switch on - intrinsic parasitic capacitances of JFET: Cgd, Cgs, Cds - parasitic influence of wire: Lg_par, Ls_par, Rs_par Cgd-measurement => simulation

25 The Results E1 /V V GS /V time/s assumption: Cds 3xCgd t rise = 25 ns V ds = 600 V V gs = V Cgd =f(uds) look-up table without L s_par with L s_par time/s

26 Outlook The developed package is to good for the switch, even significantly faster switches could be packaged this way The proposed packaging technology leads the way to a package for the ideal switch. Ideal switches will have to be packaged including the commutation cell, in order to make it possible to handle for the average user