3D Si Interposer Design and Electrical Performance Study

Transcription

1 DesignCon D Si Interposer Design and Electrical Performance Study Mandy (Ying) Ji, Rambus Inc. Ming Li, Rambus Inc. Julia Cline, Rambus Inc. Dave Secker, Rambus Inc. Kevin Cai, Rambus Inc. John Lau, Industrial Technology Research Institute Pei-Jer Tzeng, Industrial Technology Research Institute Chau-Jie Zhan, Industrial Technology Research Institute Ching-Kuan Lee, Industrial Technology Research Institute

2 Abstract A Silicon interposer is designed to have two active dies on top and one active die on the bottom. The double-sided RDL layers and TSVs on this Si interposer provide die to die signal connections and vertical/lateral power deliveries. Detailed studies of electrical performance on RDL signal routing and TSV are discussed followed by design strategies of this Si interposer. Die to die signal connections are implemented by RDL transmission lines and TSVs. Different types of transmission lines (stripline, microstrip line, and CPW line) are studied based on measurement results and correlations with modeling results from a 3D field solver. This study provides design guidelines for signal routing and signal integrity up to 20GHz. Author(s) Biography Mandy (Ying) Ji is a System Design Engineering at Rambus Inc. since She is responsible for physical design, signal and power integrity analysis of Si-interposer, package, and board. Previously she worked at Sun Microsystems as a Signal Integrity Engineer. Dr. Ji received her M.S. Electrical Engineering in 2007 and Ph.D. Mechanical Engineering in Ming Li received his B.S., M.S., and Ph. D. degrees in materials science & engineering. He has been a packaging engineer at Rambus Inc. since He is responsible for advanced IC packaging development, IC package design and substrate layout, and thermal and mechanical analysis of IC packages. Previously, he had worked at Sandia National Lab as a research associate, at Tessera Inc. as a modeling engineer, and at PerkinElmer Inc. as a senior packaging engineer. Julia Cline is manager of a System Engineering team at Rambus. Since joining Rambus in 2005, she has held positions as a product engineer and a digital circuit designer working on solutions for PS3 and HDTV customers. In her current role, she manages a team responsible for system solutions and package designs to validate Rambus technologies. Ms. Cline received her M.S. degree from the Massachusetts Institute of Technology in Electrical Engineering and Computer Science and her B.S. from Brown University in Electrical Engineering. Dave Secker is currently a Technical Director in Systems Engineering at Rambus Inc., where he has been for the past 15 years. His responsibilities include physical design, modeling and optimization of high-speed signal interconnect and power delivery networks at the IC package and system board levels. Previously he worked at Los Alamos National Laboratory as a research assistant. Mr. Secker received his M.S. degree in Electrical and Computer Engineering from The University of Arizona in Kevin Cai is a Senior Principal Engineer at Ramus. He has spent many years in the following companies, Juniper Networks, Sun Microsystems and Nortel Networks

3 specializing in high speed signal integrity, system design and test, and material characterization. He received his Ph.D. degree in Electrical Engineering. John Lau has been an ITRI Fellow (in Taiwan) since January Before that, he was with HKUST (a visiting professor) for one year, IME (Packaging Lab Director) for two years, and Agilent/HP (MTS and Sr. Scientist) in California for more than 25 years. His current interest is in 3D IC integration. Pei-Jer Tzeng received the Ph. D degree in Engineering and System Science from National Tsing Hua University, Hsinchu, Taiwan, in He has been with Electronic and Optoelectronic Research Laboratories at Industrial Technology Research Institute (ITRI) in Hsinchu, Taiwan since He has worked on the area of the process integration and characterization of MOS devices, gate dielectrics, high-k material, and their applications in DRAM and non-volatile memory. Currently, he is working on process integration of exploratory 3D IC Technology. Chau-Jie Zhan is an Engineer in the Assembly and Reliability Department, Industrial Technology Research Institute, Taiwan. He studied on flip chip package, lead-free assembly process, 3D chip stacking package and Electromigration in solder joint. Ching-Kuan Lee received her Ph.D. Degree in Chemistry from Fu Jen Catholic University, Taiwan, R.O.C., in Since 2003, she has been with the Industrial Technology Research Institute (ITRI), Material and Chemical Research Laboratories, and shifted to Electronics and Optoelectronic Research Laboratories as a member of the Packaging Technology Division in June 2006, and is mainly responsible for microbumping process. The focus of her work is chemical metallization process and process development of advanced Package technology.

4 Introduction 3D IC stacking technology with through silicon vias (TSVs) has the benefits of lower latency, higher bandwidth, and smaller form factor compared with conventional package technologies such as package on package (PoP), system in package (SiP), and multi-chip module (MCM). However, direct attach 3D IC technology has its own challenges with power delivery, thermal dissipation, supply chain management, and test of known good die. These issues must be resolved before this technology can be practical. 2.5D or 3D Si interposer technology provides an early stage solution to full 3D IC designs, such as shown in the Xilinx 2.5D technology solution [1]. In this reference [1], using TSMC s 65nm fab line, TSVs are manufactured into the silicon interposer along with multi-levelmetal (MLM) interconnects. This foundry back-end-of-line (BEOL) manufacturing process enables submicron width and spacing for high density purposes. This paper proposes a 3D Si interposer which has two dies on top and one die on the bottom. The interposer is manufactured in a similar BEOL process, but with coarser line width and spacing compared with the foundry process. The details of the design rules used will be discussed in detail. In addition to the manufacturing design constraints, this paper describes the electrical performance of the Si interposer technology. Recent studies of this technology have illustrated both the RDL transmission line performance and the TSV electrical performance [2] [3] [4] [5] [6] [7], however, comprehensive electrical performance in combination with manufacturing capabilities and design constraints has not been studied. This work challenges Si interposer design and performance by combining three 40nm dies with high frequency chip to chip interfaces [8] [9] connected on the silicon interposer. The paper will be presented in the following sections. First, double-sided 3D Si interposer manufacture processes are described. Next, electrical studies for RDL transmission lines (microstrip line, stripline, and CPW line) for both single-ended and differential formats, TSVs, and channel performances are presented. And finally, based on these electrical studies, the design strategies for signal connection and power delivery are discussed for this interposer design. Manufacture Process of Double-sided Si Interposer The Si interposer presented has double-sided RDL layers to accommodate the two active silicon dies on top and the one active die on the bottom. There are three layers of RDL, three layers on the top and two layers on the bottom side of the Si interposer. The five layers pose challenges for the manufacturing process. The manufacturing process of this Si interposer starts with a 300mm blanket Si wafer (10S/m) with a SiN x /SiO x insulation layer on the top surface deposited by Chemical Vapor Deposition (CVD). The TSV process is a typical via-first process that starts with deep reactive ion etch (DRIE) hole drilling, followed by CVD of SiO 2 deposition for an insulation layer, Plasma Vapor deposition (PVD) of Tantalum/Titanium deposition for

5 diffusion barrier and seed layers, then electroplating of Copper (Cu) for hole filling. The process is finished with chemical mechanical planarization (CMP) for removal of excessive Cu on top of the TSVs. This TSV process is done on the top side of the Si wafer. The completed TSV is actually a blind via with a depth of slightly more than 100 um and a diameter of approximately 10um; the resulting aspect ratio of the TSV is approximately 10:1. After the TSV formation, this Si interposer wafer is ready for processing the top side RDL. The RDL is a typical Cu BEOL process using a Cu damascene process technology. The critical dimension (CD) of the RDL layers is 3 um and this is limited by the machine capability using a whole wafer mask aligner. Three RDL layers are built sequentially one by one, followed by an under-bump metallization (UBM) layer of solder bump pads for top side flip chip attachment. The solder bumps complete the top side processing of the interposer. The following process requirements are done to complete the back-side RDL. The completed top side of the Si interposer is temporarily bonded to a support wafer. Then the back (bottom) side of the Si interposer wafer is ground, polished and etched to reveal the TSVs on the back side. This leaves the Si interposer approximately 100um thick. Once these TSVs are revealed, an insulation layer is deposited on the backside of the wafer, followed by CMP. As on the front side, after CMP is complete, the backside RDL manufacturing is started using a Cu damascene BEOL process technology. Due to concerns of mask alignment capabilities and wafer warpage from top side processing and the temporary bonding process the CD of the backside RDL is relaxed to 5um. The two layer backside RDL is done sequentially followed by UBM of the solder bump pads for backside flip chip attachment and attachment to the laminate substrate below. The last step of the Si interposer process is to debond the support wafer. At this point, the Si interposer wafer is ready for dicing and characterization. Figure 1 and Figure 2 illustrate the schematic of the manufacturing process and the crosssection structure of the silicon interposer. In addition, Figure 2 shows the names of the RDL layers.

6 Figure 1: 3D Si interposer manufacturing process flow Figure 2: Schematic of Si interposer cross-section

7 Si Interposer Passive Structure Electrical Performance The designed Si interposer has a size of 18mmx18mm. As previously described, the interposer has three RDL layers on the top and two RDL layers on the bottom of a 100 um thick Si core. As shown in Figure 3 and Figure 4, the center inter-connecting region which combines two active dies on top and one die on the bottom has a total area of 9.26mm x 11.78mm. The three dies are exactly same. The top two dies are connected together via traces routed on the top RDL layers. Both of the top two dies talk with the bottom die though TSV and RDL routing layers. Outside the center inter-connecting region, there are passive test structures to test the RDL signaling capabilities and the TSV performance. Passive test structures Inter-connecting region Die1 Die2 Figure 3: Top view of an 18mm x 18mm Si interposer Inter-connecting region Die3 Figure 4: Bottom view of the Si interposer

8 This paper studies various signaling structures on the Si-interposer, including RDL transmission lines, TSVs, and TSV plus transmission lines. VNA measurements up to 20 GHz are made on these different passive test structures. For these measurements, wafer probing pads are designed into the test structures. Ground signal ground (GSG) probes are used for stripline, microstrip line, and CPW line measurements. Ground signal (GS) and signal ground (SG) probes are used for TSV noise characterizations. RDL Transmission Line Measurements and Modeling In this section, studies are focused on describing the RDL layer signaling structures, measurement results, and modeling including single-ended and differential formats with different trace lengths. RDL Single-ended Transmission Line Measurements There are three different types of transmission lines on RDL layer: microstrip line, stripline, and coplanar waveguide (CPW) line. Table 1 shows different test cases and Figure 5 shows the cross-section of the respective cases. Microstrip line structures (Case1-Case4) are similar to package and PCB structures with ground return paths below the signal layer. Case3 and Case4 skip adjacent metal layer (TR2) and use TR1 as the ground. Stripline structures (Case5) are also similar to package and PCB structures with ground planes above and below the signal layers. For coplanar waveguide (CPW) line structures (Case6-Case10) there are three different strategies for signaling: - GSG with two ground lines and one signal line on the same layer (Case6) with the edge-to-edge spacing between the ground and signal lines of 12um for 3um trace widths - GSG where two ground lines are below the signal layer with signal and ground edges aligned (Case7 and Case8) - GSG with two ground lines on the signal layer and one additional ground line on the next layer directly below the signal line (the same layer signal to ground spacing is 12um for a 3um line width and 5um for a 5um line width). Single-ended structures are measured by using GSG 80um probes. As aforementioned, the minimum trace width is 3um due to manufacture limitation. The test structures cover trace length of 1mm, 2mm, and 4mm.

9 Case no. Type Trace Width/Layer/Spacing Ground Layer Case1 Microstrip line 3um/TR3 TR2 Case2 Microstrip line 5um/TR3 TR2 Case3 Microstrip line 3um/TR3 TR1 Case4 Microstrip line 5um/TR3 TR1 Case5 Stripline 5um/TR2 TR3 and TR1 Case6 CPW line 3um/TR3/12um TR3 Case7 CPW line 3um/TR3/0um TR2 Case8 CPW line 5um/TR3/0um TR2 Case9 CPW line 3um/TR3/12um TR3 and TR2 Case10 CPW line 5um/TR3/5um TR3 and TR2 Table 1: Single-ended test structures (a) Case1 and Case2 (b) Case3 and Case4 (c) Case5 (d) Case6 (e) Case7 and Case8 (f) Case9 and Case10 Figure 5: Illustration of different cross section cases Figure 6 - Figure 8 demonstrate the measurement results for the above test cases. For all of the modeling and simulation studies and the measurement results, the termination resistance used is 50ohm. Figure 6(a) shows the results for microstrip line with adjacent ground planes. The SiO 2 dielectric layer thickness between the RDL metal layers is 1um. The insertion loss is dominated by impedance mismatch, which is shown in the return loss plot. The return loss is as high as -5dB when frequency is close to 20GHz. However, for 4mm trace length, the return loss is close to -5dB even at lower frequency due to the

10 quarter wavelength resonance at ~14GHz. Trace widths of 3um or 5um do not play an important role in the loss performance. Due to the RDL manufacturing limitations (e.g., SiO2 thickness, critical dimension of the trace) it is not easy to control the trace impedance. Another option is to make the termination resistance match the RDL transmission line impedance during circuit design period. Case3 and Case4, which skip adjacent metal layers, have the best performance as shown in Figure 6(b). For Case3 and Case4, the impedance is improved since the dielectric layer thickness is increased to 3.5um because of the skipped adjacent layer for ground. This concept is proved in Figure 6(b) which shows much lower return loss and therefore better performance in insertion loss compared to Case1 and Case2 in Figure 6(a). The insertion loss increases linearly with frequency due to the conductor and dielectric loss. Similar to Case1 and Case2, trace width does not play an important role. At the lowest frequency, the insertion starts around -0.8dB; this shows the lossy characteristics for the RDL line compared with an organic package trace of typically between -0.01dB ~ -0.02dB. The high loss characteristics are due to the small cross-section dimensions of the RDL lines (width of 5um and height of 1.5um). Case3 and Case4 show improved performance. However, one main drawback of Case3 and Case4 is the addition of one metal layer and resulting in an increased cost. Therefore, it may not be feasible to have signaling in the form of Case3 and Case4 mainly due to cost requirements.

11 (a) Microstrip line with signal on TR3 and ground on TR2 (b) Microstrip line with signal on TR3 and ground on TR1 Figure 6: Single-ended microstrip line measurement results Figure 7 shows the stripline structure results for both insertion loss and return loss. Stripline structures above or below ground planes will make the impedance smaller, which in turn causes worse return loss (~3dB). In addition, with the two metal ground layers, the cost will increase. Therefore, the stripline structure should be avoided due to both electrical performance and cost.

12 Figure 7: Single-ended stripline measurement results Figure 8 illustrates the measurement results for the CPW line structure cases. The reason for studying different CPW line structures is to understand signal routing density and performance tradeoffs. Case6 has the best performance. From Table 1, the signal line to ground line spacing is 12um; this may be a limiting factor on the signal density. By adding an extra ground line below the signal line (Case9), the performance is degraded compared with Case6. The extra ground line decreases the impedance even further with smaller loop inductance and bigger capacitance. The Case7 and Case8 have similar performance as Case9 and Case10 due to close ground lines. Case6 is conventional GSG CPW line. When considering multiple RDL layers for signaling, it is necessary to avoid having a signal line in one layer right below a signal line on another layer as shown in Figure 9(a). The dielectric thickness of 1um (top and bottom signal spacing) is much smaller than the spacing from signal and ground on the same layer (e.g. 5um); therefore, crosstalk between top and bottom signals will drastically hurt the performance. For multi-layer high density signaling, either Case7/Case8 in Figure 9(b) or Case9/Case10 in Figure 9(c) is suggested. However, the best signaling structure still depends on the other layer assignments if there are more than two RDL layers.

13 (a) GSG CPW line with signal and ground lines at the same layer (b) GSG CPW line with ground lines on the layer below signal layer (c) GSG CPW line with signal and ground lines at the same layer and an extra ground line below the signal line Figure 8: Single-ended coplanar waveguide line measurement results

14 (a) Case6 (b) Case7 and Case8 high density (c) Case9 and Case10 high density Figure 9: CPW line density illustration RDL Single-ended Microstrip Line Modeling Correlation To correlate the model and the measurement results, this paper uses Case2 with 1mm trace length as the benchmark. Figure 10 shows 3D view of the model. The blue color is the trace and the green color is the ground plane below the trace. For the manufacturing requirement, there are 20um x 20um slots with a pitch of 40um on the plane. The 3D model is imported from the APD design file directly and modified at the port definition. In the manufactured test structure there is a via going up to the probing pad at each end of the trace, therefore, the 3D model has one lumped port launched at each probing pad. In order to use the de-embedding feature for different trace length, the 3D model is modified to use wave port. Sanity checks are made between lumped port and wave port for this test structure and the same results are observed. Figure 10: 3D view of the model It is worth mentioning, the cross-section dimensions are off from nominal dimensions due to fabrication error. Figure 11 shows a SEM photo for the cross-section dimensions. This paper compares measurement results with the modeling results using the nominal dimensions and the cross-section dimensions for trace width, dielectric thickness, and metal thickness. Figure 12 shows the comparison. From the graph, it is clear to see that the correlation is very good when the actual manufacturing dimensions are input to the model.

15 Figure 11: SEM photo of cross-section dimensions Figure 12: 3D model and measurement correlation results RDL Differential Microstrip Line Modeling The single-ended model is extended to a differential model, as shown in Figure 13. The cross-section dimensions are used with a center to center pitch of 10um for the trace.

16 Trace n Trace p Figure 13: Differential microstrip line model The modeling results shown in Figure 14 show asymmetry between trace n and trace p, which is due to different ground pattern below the two traces. The ground below trace n is a solid plane, while the ground below trace p has slots. From single-ended measurement results, it is pointed out that microstrip line trace impedance is far below 50ohm with higher return loss. For differential case, trace p has slots in the return path which will increase the loop inductance and decrease the capacitance from signal to ground. Therefore, the impedance for trace p is increased to be closer to 50ohm. Return loss in Figure 14 shows trace p has lower return loss. The slotting size and pattern from the manufacture house need to be considered before laying out the signal traces. For the differential signal routing, it is necessary to keep trace n and p with the same return path pattern in order to reduce differential to common mode conversion. Figure 14: Differential microstrip line modeling results

17 TSV Measurements and Modeling This section focuses on TSV modeling, performance, and noise coupling studies. TSV Model Extraction For this work, a TSV model is extracted by using closed-form formulae from references [6] [7] and 3D modeling from HFSS. A pair of TSVs is modeled and compared between the closed-form formulae and the 3D model. The modeled TSV has a diameter of 10um, a height of 100um, a SiO 2 liner of 0.5um, and a pitch of 80um in the Si core with a conductivity of 10S/m. From the closed-form formulae: Rtsv=0.044ohm, Ltsv=110pH, Gsi=0.0024S, Cox=0.233pF, and Csi=0.0124pF. Figure 15 shows the equivalent circuit model. For HFSS, a 3D model is built based on the above physical dimensions and material properties (Figure 16). Figure 17 compares the insertion and return loss for these two models and shows good matches except for a slight discrepancy for insertion loss at higher frequency. Rtsv Ltsv Cox Csi Csi Cox Figure 15: TSV equivalent circuit model Figure 16: TSV 3D model

18 Figure 17: Circuit model and 3D model comparison Measurement Results for TSV and Microstrip Line To compare microstrip line and microstripline with TSVs, two test structures are built. The first one is a microstrip line routed on the top RDL layer (trace without TSV). The second structure is a microstrip line routed on the first bottom layer (BR1) with a TSV on either end (trace with TSV). The two lines have the same dimensions with the exception of the TSVs on the end of the second trace. The GSG probing pads are on the top side. The GSG TSV model is derived from the RLGC equivalent circuit model for the pair of TSVs. Figure 18 shows the measured results of the trace without TSV and the trace with TSV. In addition, the TSV model is cascaded with the trace without TSV. Figure 18 shows the comparison between this cascaded model and the direct trace with TSV measurement. The insertion loss results between the cascaded model and the pure measurement results match well. It is shown that at lower frequency, the capacitive TSV pulls down the insertion loss drastically compared with the case trace without TSV. The two end TSVs create about a 0.5dB difference at higher frequency. Therefore, the TSV effect cannot be ignored for the accurate channel performance. The return loss comparison is off by more than the insertion loss; this may be due to the different manufacturing tolerance on the different RDL layers.

19 Figure 18: TSV model cascaded with trace measurement results TSV Noise Coupling Several test structures are built to study the noise coupling between two signal TSVs. The TSV pitch covers 35um, 45um, 65um, 105um, and 185um (Figure 19). There are ground ring surrounding the two TSVs. As shown in Figure 20, the noise increases with increasing frequency and decreases with pitch width. For the application with TSV pitch of 185um (same pitch as C4 bump), the coupled noise is smaller than -38dB at 20GHz; this pitch may not be a concern for signal integrity. The coupled noise measurement results can be used as a design guideline for high speed link application. Figure 19: Top view of test structures (pitch of 35um, 45um, 65um, 105um, 185um from left to right) Figure 20: TSV noise coupling measurement results

20 Channel Simulation This section utilizes the previously proved model to illustrate a channel simulation for PCIe 2.0. For this simulated channel example, the driver and receiver are ideal and no jitter and equalization are applied. To speed the simulation time and guarantee symmetrical return path of the signals, the ground plane is modeled as a solid plane. Two differential pairs with different trace dimensions are modeled with trace width / intra-pair spacing / inter-pair spacing of 5um/5um/5um, 1um/1um/1um, and 1um/1um/2um. The maximum trace length is found for each of above three cases without considering crosstalk. The simulation results in Figure21 show that for the 5um trace width case, the maximum RDL trace length is 11mm; for 1mm trace width, the maximum trace length is only 6mm. Therefore, tradeoff simulations between channel performance and dimensions (trace width and trace length) should be performed for RDL signaling. Figure 21: PCIe Gen 2 eye diagram for different trace dimensions without crosstalk In addition to the results shown without crosstalk, the same maximum trace length model is used with next end crosstalk (NEXT) and far end crosstalk (FEXT) turned on separately. Figure 22 shows the simulation results for the different cases with crosstalk. As expected, NEXT plays a more important role than FEXT. The highest density case of a 1um trace with 1um intra-pair and 1um inter-pair spacing is the worst case. To mitigate

21 crosstalk effects the inter-pair spacing can be increased. For the case of 2um inter-pair spacing, eye width and height are improved compared with the case of 1um inter-pair spacing. However, increasing the inter-pair spacing will decrease the routing density. To achieve highest bandwidth, detailed simulations needs to be performed to optimize between the electrical performance and the routing density (trace width and spacing) [10]. Figure 22: PCIe Gen2 eye diagram for different trace dimensions with crosstalk Double-sided Interposer Design Strategies Previous results are used as design guidelines for implementing the Si interposer design. For the designed Si interposer, there are three RDL layers on the top side and two RDL layers on the bottom side. These layers are assigned for both signal routing and power delivery. For a double sided interposer with the configuration of two dies on top and one die on the bottom, there are power delivery limitations.

22 RDL traces are utilized for signal connections between the top two dies. Both RDL traces and TSV are used for signal connections between the top dies and bottom die. Due to the existence of the bottom die, direct vertical power delivery from the C4 power bump to the top dies is not feasible. Therefore, the power delivery to both top dies and the bottom die depends on the lateral power distribution. With lateral power delivery, the DC IR drop on the silicon interposer needs to be monitored. Two methods are adopted in this design to mitigate the DC IR drop issue. First, a thick RDL metal of 1.5-2um is used. Second, a wide slotting pitch is designed (40um with slots of 20umx20um). With a 40um slotting pitch the metal coverage is 75%. As a comparison, if a slot pitch of 25um (slots of 20umx20um) is used, the metal coverage would only be 36%. To optimize the design based on signal density, power delivery, and electrical performance, this design assigns the top three and bottom two RDL layers as signal, ground, power, signal/power, and ground respectively from top to bottom. As previously illustrated, the signal traces are microstrip lines, which are not the best performance but are most feasible when considering all of the above parameters. Conclusions This paper studies the RDL signaling performance, TSV modeling, and design strategies for a 3D Si interposer with two dies on top and one die on the bottom. Based on the manufacturing limitations, the design strategies are presented. The measurement results show microstrip line and CPW line have similar performance as well as cost efficiency. The RDL slotting required by manufacturing on any plane will impact the signal performance, especially for differential signal pairs. Attention needs to be paid for differential pair routing to guarantee the symmetric return path for both traces. In addition, this paper presents TSV performance by using an equivalent circuit model and a 3D model. The results show that the presence of TSVs will degrade the signal performance due to the TSV parasitics. The channel simulation show detailed analysis is needed before making decisions on signal dimension (width and length) and signal density (spacing) for longer trace (several millimeter and above) application. References [1] K. Saban, Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency, October [2] X. Gu et al., High-Density Silicon Carrier Transmission Line Design for Chip-to- Chip Interconnects, Electrical Performance of Electric Packaging and Systems, 2011, pp [3] N. Kim et al., Through Silicon Via (TSV) Design Considering Technology Challenges for Very High-Speed Signal Transmission, DesignCon, [4] T. Sung et al., Electrical Analyses of TSV-RDL-Bump of Interposers for High Speed 3D IC Integration, Electronic Components and Technology Conference, 2012, pp

23 [5] V. Sundaram et al., Low-Cost and Low-Loss 3D Silicon Interposer for High Bandwidth Logic-to-Memory Interconnections without TSV in the Logic IC, Electronic Components and Technology Conference, 2012 pp [6] E.X. Liu et al., Multi-Physics Modeling of Through-Silicon Vias with Equivalent- Circuit Approach, Electrical Performance of Electronic packaging and Systems, 2010 pp [7] R.B. Sun et al., RC Passive Equalizer for Through Silicon Via, Electrical Performance of Electronic packaging and Systems, 2010 pp [8] A. Amirkhany et al., A 12.8-Gbps/link Tri-Modal Single-Ended Memory Interface for Graphics Applications, Proc. IEEE Symposium on VLSI Circuits, [9] K. Kaviani et al., A Tri-Modal 20Gbps/link Differential/DDR3/GDDR5 Memory Interface, Proc. IEEE Symposium on VLSI Circuits, 2011, pp [10] M. Detalle et al., Fat damascene wires for high bandwidth routing in silicon interposer, IMEC in SSDM, Kyoto, Japan, September 25-27, 2012.