ON-WAFER CALIBRATION USING SPACE-CONSERVATIVE (SOLT) STANDARDS. M. Imparato, T. Weller and L. Dunleavy

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1 ON-WAFER CALIBRATION USING SPACE-CONSERVATIVE (SOLT) STANDARDS M. Imparato, T. Weller and L. Dunleavy Electrical Engineering Department University of South Florida, Tampa, FL ABSTRACT In this paper the accuracy of on-wafer calibration using space-conservative (SOLT) standards is evaluated. The calibration approach relies on measurement-based standard definitions. Results are presented using CPW standards with 50 and 300 micron offsets, over the range from ghz. In comparing to a multi-line TRL, the magnitude of the difference between the S- parameters is less than up to 40 GHz, and below 0.1 up to 65 GHz. INTRODUCTION The Thru-Reflect-Line (TRL) calibration method [1] is partly based on the measurement of two similar, but different length lines to determine the propagation constant of the transmission line medium. Typically, the offset length between the lines is a quarter-wavelength at the center frequency of interest. In the case of multi-line TRL, multiple delay lines are used to enhance the accuracy and bandwidth of the calibration [2]. Although the accuracy and convenience of TRL are well established, the amount of substrate area needed to accommodate the standards may be prohibitive in some circumstances. This is true, for example, when calibration standards are desired on production MMIC wafers. A solution to this problem that is often used is to perform what is known as an off-wafer calibration. This usually involves an SOLT (Short-Open-Load- Thru) or LRM (Line-Reflect-Match) calibration using standards on an alumina calibration substrate, such as the GGB CS-5. Two factors that limit the accuracy of this method are the use of lumped element models to represent the standards, and the fact that the substrate and pitch of the standards may not match that of the on-wafer devices to be measured. Comparisons between offwafer and on-wafer calibrations have been reported previously in the literature (e.g., [3]). msolt CALIBRATION METHOD The objective of this work is to investigate a calibration method that employs spaceconservative, on-wafer SOLT standards that have measurement-based definitions. In this approach, one substrate or die is available that contains the standards necessary for a TRL calibration, along with each of the SOLT standards. A TRL calibration is first performed, after which each SOLT standard is measured in order to generate a characterization file. Subsequent calibrations can then be performed using only the SOLT standards, which are readily accommodated in a small amount of wafer space. The larger TRL standards are needed only for the initial characterization. In the following, results from a series of comparisons between multi-line TRL and the measurement-based SOLT (hereafter referred to as msolt) are presented. All standards used in this study are coplanar waveguide (CPW) printed on semi-insulating GaAs. Factors that may limit the accuracy of the msolt technique are the fringing field or evanescent mode effects in the vicinity of the microwave probe, and 1999 IEEE International Microwave Symposium

2 repeatability of the resistor used for the match standard. An attempt to address the first point has been made by examining the differences between SOL standards with varying offsets from the probing location. The second point is still under study. The results obtained to date indicate that an msolt calibration using point (50 µm) standards provides the same level of accuracy as a TRL calibration, and is considerably better than offwafer calibration approaches. This accuracy is obtained using a minimal amount of wafer space, and with standards that can be designed to match the geometry of devices under test. STANDARD GEOMETRIES Several sets of coplanar waveguide calibration standards and verification devices were used for the investigation. The first calibration set is designed to have a nominal characteristic impedance of 50 Ω, with a cross-section of S+2W=120 um and a ground plane width, Wg, of 150 um (see Figure 1). The TRL standards are comprised of a mm thru line, a mm delay line, a mm delay line, a mm delay line, and an open and short reflect. For the msolt calibration standards, geometries with 50, 100, and 300 um offsets from the probing position were designed. The circuits were fabricated on 625 um-thick gallium arsenide and the metal was plated gold with a thickness of 4.7 um. W S Wg 25 um Alignment marker length Figure 1. Illustration of a general CPW structure used in this work. Probe alignment markers were placed 25 um from the edge of the transmission lines. The verification devices that were used to perform the calibration comparisons consisted of the following: the SOL short, open and load standards; the mm delay line; 15, 18, 30, and 40 db attenuators; a series LC-stub resonator; a 0.03 pf MIM capacitor; an open-short reflect; and a Ω resistor (see Figure 2). Resonator Open-Short Reflect Attenuator ohm resistor Figure 2. Illustration of some verification devices used for the calibration comparisons. CALIBRATION COMPARISONS As described in Section I, the msolt standard definitions are comprised of measured S-parameter data. The calibration used for these standard measurements was a multi-line TRL, which was performed with the NIST Multical software [2]. A program called Wafercal, written by Anritsu, is

3 Sij - S'ij used to generate the characterization file that contains the TRL-calibrated S-parameter measurements for the msolt standards. After the characterization file is created, subsequent onwafer msolt calibrations are performed using only the SOLT standards. The error correction calculations are done off-line on a PC using Wafercal, which stores the 12-term error coefficients to the VNA upon completion. The measurements were completed using a Wiltron 360B VNA, a Jmicro probe-station and GGB 150 um-pitch GSG probes msolt 300 um msolt 50 um CS5 NIST The overall accuracy of the msolt approach is illustrated concisely in Figure 3. The y-axis in the plot represents the maximum difference in any S- parameter relative to a NIST multi-line TRL calibration measurement. These results include measured data for all the verification devices described in the preceding section. The curve labeled NIST is a repeatability test between two multi-line TRL calibrations. The two curves labeled msolt correspond to comparisons using the 50 and 300 um-offset SOLT standards; the maximum differences here are approximately 0.08 for both offset designs, respectively. Finally, the curve labeled CS5 corresponds to an off-wafer LRM calibration using the GGB CS5 alumina substrate. The results indicate that an improvement of better than 2:1 is achieved using the msolt approach relative to the off-wafer calibration. The comparison between the msolt calibrations and the NIST repeatability test is encouraging, although it should be noted that the msolt standards used were the same structures characterized in the initial TRL measurements. Accuracy limiting effects such as variations in the load are currently being investigated. Figure 3. Maximum difference among all S- parameters relative to a NIST multi-line TRL calibration. msolt 300 um and msolt 50 um refer to calibrations using 300 and 50 um offset standards, respectively. The NIST curve is a repeatability test. In order to gain a better insight into the errorcorrection performance of the msolt method, the S-parameter comparisons for individual verification devices were examined. For the calibrations using both the 50 and 300 um offset standards, the four devices showing the largest differences were the LC-resonator, the delay line and the open and short standards. Individual curves for these devices are shown in Figure 4 and Figure 5. The difference between NIST TRL and msolt measurements for the remaining verification circuits was typically less than 0.02 to 0.03 across the band. It might be assumed that with the type of comparison being made, the greatest differences occur when a given S-parameter has a magnitude close to 1. This is supported by the fact that the delay, short and open are among the standards with the largest levels of error. This is not true for the LC-stub resonator, however, as all of its S- parameters are approximately 0.5 above 50 GHz.

4 Sij - S'ij Sij - S'ij Sij - S'ij LC-Res Delay Short Open msolt 300 um Figure 4. Maximum difference among all S- parameters between the 50 um-offset msolt for selected verification devices. LC-Res Delay Short Open Figure 6. Maximum difference in magnitude among all S-parameters between the 300 um-offset msolt for all verification devices. Sij - S'ij LC-Res (S11) LC-Res (S21) Delay (S21) Short (S11) 4 Figure 5. Maximum difference among all S- parameters between the 300 um-offset msolt for selected verification devices. A closer look at the data reveals that phase error is dominating the results for the LC-resonator. In Figure 6, the magnitude in the differences of the S- parameter magnitudes is shown for the 300 um offset case. As in Figure 3, this curve corresponds to the maximum difference among all the verification devices. The difference is typically below 0.03 when compared in this sense. The difference in the phase of selected S-parameters for the four worst-case devices is given in Figure 7. This plot proves that phase error in S11 of the LCresonator is the largest contributor to the msolt results in Figure Figure 7. Maximum difference in phase among selected S-parameters between the 300 um-offset msolt calibration and a NIST multi-line TRL calibration, for selected verification devices. SUMMARY This paper has presented an investigation into the accuracy of an on-wafer calibration approach developed around space-conservative SOLT standards. The methodology involves the initial use of a highly accurate TRL calibration to characterize the point standards. Subsequent calibration can then be performed using the measurement-based standard definitions. The approach has the advantage of requiring minimal

5 wafer space for the standards while providing improved accuracy relative to off-wafer calibrations made with commercial calibration substrates. ACKNOWLEDGEMENTS The Anritsu Company supported this work. The authors also thank ITT GaAsTEK for providing layout assistance and foundry services, and acknowledge the support provided by Suss and GGB Industries. We also thank Ed Daw (Anritsu), David Walker, Dylan Williams and Roger Marks (all at NIST) for their helpful suggestions. REFERENCES 1) G. F. Engen and C.A. Hoer, " Thru-Reflect-Line": An Improved Technique for Calibrating the Dual Six port Automatic Network Analyzer," IEEE Trans. MTT, vol. MTT-27, pg , Dec ) R. B. Marks, "A Multiline Method of Network Analyzer Calibration," IEEE Trans., vol. 39 No. 7, July ) R.B Marks and D.F. Williams "Verification of Commercial Probe Tip Calibrations," 42nd ARFTG Conference Digest, pp , Nov