Test Structures and Techniques for On-Wafer CMOS TRL Calibration

Transcription

1 Test Structures and Techniques for On-Wafer CMOS Calibration Michael Bohl Jenner and Troels Emil Kolding RF Integrated Systems & Circuits (RISC) group, Aalborg University, Denmark. Internet: Abstract In this paper, we demonstrate for the first time a calibration kit fabricated in CMOS technology. To fulfill a basic requirement of high probe-isolation of the method, we have based all fabricated calibration standards on a shield-based measuring fixture that heavily reduces the effects of the semiconducting substrate. We analyze the electrical performance of the standards, including their accuracy, and the performance of CMOS-based calibration is compared to a reference calibration based on the technique and a high-precision impedance standard substrate. We find that CMOS calibration is indeed feasible for measurements in the low-gigahertz frequency range but not without implementation problems. I. INTRODUCTION THE commercial break-through of low-cost silicon CMOS technology as a competitive RF-IC contender is conditioned on the availability of accurate and reliable device models. However, accurate modeling calls for precise on-wafer measurements that are hard to obtain due to high substrate losses and low interconnect conductance inherent to CMOS technology []. On-wafer RF measurements are typically calibrated with a high-precision impedance standard substrate (ISS) fabricated with gold metallization and isolating alumina substrate. However, the actual measurement on the deviceunder-test is conducted on a different chip which displays different physical characteristics than the reference ISS. Most linear changes associated with substrate losses, contact effects, and metallization issues may be handled using accurate deembedding techniques. However, nonlinear changes that relate to the mode of propagation onto the chip are not easily handled by simple measures. Instead, on-wafer calibration directly from the die-under-test is a feasible solution. So far, on-wafer two-port calibration has only been demonstrated for silicon processes with highly insulating substrates; e.g. silicon on insulator []. However, the above mentioned mode problem is even more significant for low-cost CMOS processes with semi-insulating substrates. As these technologies are widely applied in various RF applications, the relevance of an on-wafer CMOS thru-reflect-line () calibration technique is therefore very high. In this paper, we will present a design method that facilitates the fabrication of effective standards which mitigate the effects of the silicon substrate. We shall investigate the accuracy by which we may fabricate these calibration standards in standard submicron CMOS technologies. For the first time, we conduct and benchmark-test a CMOS calibration using the NIST calibration comparison method []. II. CMOS IMPLEMENTATION With typical tolerances on resisitors on the order of -%, an accurate 5Ω standard cannot be easily fabricated in CMOS technology. Most common calibration methods depend heavily on the accuracy of the load standard and therefore it appears that [] is the most convincing form of on-chip calibration for low-cost silicon technologies. calibration is generally viewed as a highly accurate form of calibration and current standardized test measurements are based on this technique. circumvents some of the difficulties that are associated with getting a sufficiently accurate specification of the calibration standards. In this sense, it is attractive for low-accuracy technologies such as silicon CMOS technology. Basically, the only "practical" disadvantage of calibration is that very long line standards are needed to facilitate measurements in the low-gigahertz frequency range where RF CMOS circuitry usually operates. Compared to other approaches, such as the short-open-load-thru (SOLT) calibration, the algorithm does not relate directly to the error network representation of commonly used vector network analyzers (VNAs). Hence, some concerns of converting between the error network shown in Fig. and the VNA representation exist. In the following, we will adress some of these issues and show a solution. Fig.. Illustration of standards and error network. One basic issue of is the assumption of negligible forward coupling between the two ports. With standard CMOS substrates and test-structures, this condition is not fulfilled which previously has disqualified CMOS-based calibration. However, recently a new shield-based test fixture has been presented which effectively reduces the forward coupling to very low values even for low-resistivity substrates [5]. The basics of the shield-based test-fixture are illustrated in Fig.. In this work, we have utilized the general idea of shielding to fabricate a high-isolation calibration kit in a standard CMOS technology. By doing this, we ensure that (i) mode assumptions for calibration and device measurement are the same and (ii) the basic propagation becomes that of a pure microstrip rather than the hybrid of a coplanar waveguide and a microstrip which is the common CMOS scenario. Forward coupling levels of less than -5dB are easily obtained up to

2 8Hz using the shield-based approach [6]. S p- substrate round shield DUT ap S Shield extension metal layers. Both kits are shield based, i.e. the ground plane is formed by the lowest metal layer (M). A. 7Ω Calibration Kit The first calibration kit is shown in Fig.. The upper strip consists of the three uppermost metal layers (M6, M5, and M, see Fig. ). Due to the shield based approach the distance from strip to ground plane is very small, approximately µm. This gives a high capacitive coupling, and with the wide lines (85µm) the L/C ratio is small. The result is a low nominal reference impedance of approximately 7Ω. S Oxide p- substrate Top metal layer (M6) round shield (M) Fig.. Basics of shield-based test-fixture/transmission line [7]. A second issue of CMOS relates to the characteristic impedance of transmission lines and its specification in the VNA system. For typical aluminum based transmission lines the ohmic-loss per unit length is typically large compared to the per-unit-length reactance. As a result the imaginary part of transmission lines becomes significant at lower gigahertz frequencies. However, on most VNAs the specification of characteristic impedance is limited to real frequency-independent values. Due to this aspect, it is necessary to estimate/predict the characteristic impedance of the transmission line and to use off-line software to perform the calibration and extract the VNA error network parameters. A final issue is general to calibration and is concerned with the mapping between the error model and the VNA error model. If a direct transfer between the two representation is used, it is found that E SF = E LR = ε () E SR = E LF = ε () where the E-factors refer to the standard VNA error coefficients [8]. This implies that the impedance seen towards the switch does not depend on its switch setting (either forward or reverse). However, by utilizing the knowledge that has been extracted during the calibration algorithm, it is possible to take another set of measurements on the line and thru standards in order to isolate the switching errors. Thus a =a and a =a should be measured for the line and the thru providing additional information for characterizing the switches. However, in the present work switching errors are not accounted for. III. DESIN OF CMOS STANDARDS In the present work two calibration kits are presented. The first uses a line width equal to the RF pads (85µm). This reduces discontinuities and loss, but gives a small characteristic impedance. The other calibration kit is aimed for providing a nominal characteristic impedance of 5Ω. Both kits are produced in a.5µm standard epitaxial CMOS process with 6 Fig.. Calibration kit with a nominal 7Ω characteristic impedance. O denotes an open, T a thru (µm), S a short, R a reference impedance (nominal 5Ω), and L and L are lines (µm and 69µm, respectively). A. Line Modelling A simple model is formed of the employed lines, partly to give a coarse estimate of significant effects, and partly to see if it is possible to estimate the characteristic impedance from simple considerations. First the characteristics impedance Zo is estimated under the assumption of zero loss. Next, conductivity data from process specification, are used to derive a set of R [Ω/m], L [H/m], and C [F/m], assuming [S/m] is negligible. The result is compared to Momentum simulated data and to measured data ( calibrated) - see Fig.. The differences on db(s) are less than.db to 5Hz. However, the complex structure of the lines are not correctly represented in Momentum, giving discrepancies, which becomes even more evident when comparing estimated Zo s. A. Estimating Zo In the present work three different methods are used to estimate Zo. The first uses the above simple model, the second the gamma times length bi product of the calibration, and the third uses results from Momentum simulations. The results are shown in Fig. 5. As expected, the Zo is highly reactive at the low-gigahertz frequency range. The simple model and the gamma method agree well on the real part, whereas, compared to the other methods, the Momentum based Zo overestimates the real part. B. 5Ω Calibration Kit With the second calibration kit (see Fig. 6) another approach is taken. The target is here to have a nominal characteristic

3 impedance of 5Ω, leading to smaller directivity errors and thus less errorprone calibrations. Line (7ohm) S [db] (S) [deg] Meas Mom Mod 6 Meas Mom Mod 6 Fig.. Comparison of S for simple model (Mod), Momentum simulations (Mom), and Measured data (Meas). The length 57µm. is considered valid when the insertion phase difference between the thru and the line is between and 6 degrees. This limitation makes this kit applicable from approximately Hz and above 5Hz. Real(Zo) Imag(Zo) 5 Zo estimates Model 5 amma Momentum Model amma Momentum Fig. 5. Comparison of Zo estimates based on the simple model derived (Model), the gammal times lenght biproduct of the calibration, and (Momentum) using a mathematical estimate directly available from Momentum. Fig. 6. Calibration kit with a nominal characteristic impedance of 5Ω. O is an open, S is a short, T is a thru (6µm) and L is a line (5µm). This kit utilizes only two metal layers for the upper strip (M6,M5). The width is determined assuming lowloss lines and using commonly used and proven microstrip formulas. The result is a line width of µm. The length of the line extends this calibration kit to have a -6 degree insertion phase range from approximately.6hz to 6Hz. Unfortunately, this kit was not available in due time for measurements and benchmarking. IV. POSTPROCESSIN Before comparing calibration coefficients a common reference plane and impedance must be sought. The employed calibration routine tries to establish a reference impedance of 5Ω and a reference plane at the probe tips. The employed calibration routine tries to establish a reference impedance equal to the characteristic impedance of the microstrip lines and a reference plane in the middle of the thru. To shift reference plane of the calibration the RF pad and half the length of the thru are de-embedded. The RF pads to be de-embedded are modeled by (from probe heads to DUT): a resistor of 8mΩ, an impedance to ground and an impedance towards the DUT. Measuring the open and short structures, see Fig., it is possible to determine the two unknown impedances, and the RF pad and offset line are deembedded into the calibration coefficients. The calibration coefficients are read from the network analyzer in -term format, and must be converted to 8-term. This mapping is in general destructive, but if isolation terms and switching errors are negligible it is considered acceptable. The mapping used was proposed in [9]» X = ERF E DF E SF E DF () E SF Y = E» TF( E DR Γ ) ERR E DF E SR E DR () E RR E SR E Γ = LF E SR (5) E RR + E DR (E LF E SR ) X is the wave cascading parameters of the left-side error box, and Y is the wave cascading parameters of the right side error box, both determined during calibration. V. RENORMALIZIN Even the 5Ω calibration kit displays a characteristic impedances with a significant imaginary part, due to losses. After calibration the results must therefore be renormalized to 5Ω. Renormalization can be employed on the calibrated S- parameters, e.g. using the techniques proposed in [] or [].

4 However, for the current work the error boxes are used for benchmarking the calibration, and these must be corrected instead. This is accomplished by using the technique suggested in [] leading to p Γ Xren = Rren X Rren =» Γ Γ (7) Yren = Y Rren (8) Here Γ is given by Z o;n Z o Z o;n+z o,wherez o is the original reference impedance, and Z o;n is the new reference impedance. Y denotes an operator which change direction. Subscript "ren" denotes the renormalized error boxes. VI. CALIBRATION RESULTS The NIST calibration comparison method ([]) effectively calculates the following absolute maximum errors e ij = max(js ij s ij;rj) (9) where s ij;r is the S-parameter obtained for the reference calibration, and s ij is the S-parameter obtained from the calibration under test. To verify the calibration routine a SOLT calibration was implemented and used as a reference. Calibration standards, were embedded with a RLC circuit and a transmission line (different on each port). The two calibration methods were applied to data and the NIST calibration comparison method was used to compare the and SOLT calibration coefficients - see Fig x e 5 x e 5 x e 5 x e Fig. 7. NIST error for simulated data. The lines are formed using a lossy model and should thus be realistic. An ideal SOLT calibration is used as reference. To quantify the sensitivity towards errors in the Zo estimate, Zo was swept around a Zo estimate. The result at.8hz is shown in Fig. 8. Clearly, the result is highly sensitive to errors in the Zo estimate. Next, the calibration is compared to the ISS calibration. This is done by comparing S- parameters of an open and a short (Fig. 9), a line (Fig. ), (6) and a CMOS resistor (Fig. ). Finally, the worst case absolute errors on S-parameters are shown in Fig.. The results display periodicity, which is typically seen when inaccurate calibration is applied to a system with long cables. The calibrated data are mostly centered around the ISS calibrated data, but the accuracy is not acceptable..... e 5 e... 5 Re(Zo) e 8 e... 8 Im(Zo) Fig. 8. This graph illustrates the sensitivity of the calibration quality towards an error in the Zo estimate. The correct Zo is : j :68. The left column sweeps the real part of Zo with Im(Zo)= :68. The right column sweeps the imaginary part of Zo with Re(Z)=:. Frequency is.8hz. VII. CONCLUSIONS Two On-Wafer CMOS calibration kits were designed, layouted and implemented. Software routines for performing SOLT and calibrations were implemented and tested. The calibration routine was extended with renormalization routines to enable a shift from the characteristic impedance of the employed lines to 5Ω. In its current implementation the calibration routine is not sufficiently accurate. Based on the presented results it cannot be concluded if the switching error is causing the large error alone, and further study is needed. VIII. ACKNOWLEDMENTS The authors would like to thank Ole Kiel Jensen and Søren Laursen for their valuable comments and discussions, and Jan Mikkelsen for reviewing this manuscript. REFERENCES [] J. N. Burghartz, Silicon RF Technology The Two eneric Approaches, in Proceedings of European Solid-State Device Research Conference (ESSDERC), Stuttgart, ermany, September 997, pp. 5. [] R. illon, W. Van De Sype, D. Vanhoenacker, and L. Martens, Comparing High-Frequency De-Embedding Strategies: Immitance Correction and In-Situ Calibration, in Proceedings of IEEE International Conference on Microelectronic Test Structures (ICMTS), Monterey, California, USA, March, pp. 5.

5 S [db] S [db].5 Short.5 Open.5.5 Fig. 9. Open and Short S-parameters calibrated with and. S [db] S [deg] Match Fig.. CMOS resistor calibrated with and. S [db] S [deg] Line e e e e Fig.. db(s) of line calibrated with and. Fig.. NIST calibration comparison applied to versus. [] D. F. Williams, R. B. Marks, and A. Davidson, Comparison of On- Wafer Calibrations, in Automatic RF Techniques roup (ARFT) Conference Digest, San Diego, California, USA, December 99, pp []. F. Engen and C. A. Hoer, Thru-Reflect-Line: An Improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer, IEEE Transactions on Microwave Theory and Techniques, vol. 7, no., pp , December 979. [5] T. E. Kolding, O. K. Jensen, and T. Larsen, round-shielded Measuring Technique for Accurate On-Wafer Characterization of RF CMOS Devices, in Proceedings of IEEE International Conference on Microelectronic Test Structures (ICMTS), Monterey, California, USA, March, pp. 6. [6] T. E. Kolding, Shield-Based Microwave On-Wafer Device Measurements, Accepted for publication in IEEE Transactions on Microwave Theory and Techniques, August. [7] T. E. Kolding, On-Wafer Measuring Techniques for Characterizing RF CMOS Devices, Ph.D. thesis, RF Integrated Systems & Circuits (RISC) roup, Aalborg University, Niels Jernes Vej, 9 Aalborg Øst, Denmark, August 999. [8] Hewlett Packard Company, USA, HP Part no , HP 85B Network Analyzer 5MHz-Hz: Reaching New Levels of Performance and Versatility, May 987. [9] R. B. Marks, J. A. Jargon, and J. R. Juroshek, Calibration Comparison Method for Vector Network Analyzers, in Automatic RF Techniques roup (ARFT) Conference Digest, Clearwater, Florida, USA, December 996, pp [] J. C. Rautio, Techniques for Correcting Scattering Parameter Data of an Imperfectly Terminated Multiport when Measured with a Two-Port Network Analyzer, IEEE Transactions on Microwave Theory and Techniques, vol., no. 5, pp. 7, May 98. [] H. Dropkin, Comments on A Rigorous Technique for Measuring the Scattering Matrix of a Multiport Device with a Two-Port Network Analyzer, IEEE Transactions on Microwave Theory and Techniques, vol., no., pp. 79 8, January 98. [] R. B. Marks and D. F. Williams, A eneral Waveguide Circuit Theory, Journal of Research of the National Institute of Standards and Technology, vol. 97, no. 5, pp. 5 56, September-October 99.