FO-WLP, Embedded Die, and Alternatives: Market Trends and Drivers

Transcription

1 FO-WLP, Ebedded Die, and Alternatives: Market Trends and Drivers

2 Many Package Choices: Which One is the Correct Choice? FO-WLP (chip-last, chip-first, face-up, face-down) Traditional flip chip on lainate substrate, new versions with coreless substrates or thin core substrates Ebedded die

3 Fan-Out WLP and Ebedded Die Technologies Source: Steffen Kroehnert, NANIUM

4 Why FO-WLP? Saller for factor, lower profile package: siilar to conventional WLP in profile (can be 0.4 ) Thinner than flip chip package (no substrate) Can enable a low-profile PoP solution as large as 15 x 15 body or greater Support increased I/O density Fine L/S (10/10µ) Roadaps for <5/5µ L/S, future 2/2µ L/S Allows use of WLP with advanced seiconductor technology nodes with die shrinks With increased I/O and saller die can t fan-in using conventional WLP Saller diaeter balls and ball pitch 0.3 board level reliability issues (Qualco studies) Split die package or ulti-die package/sip Multiple die in package possible Die fabricated fro different technology nodes can be assebled in a single package Can integrate passives Excellent electrical and theral perforance Source: STATS ChipPAC.

5 Process Flows for the Various FO-WLP Approaches Traditional WL-FO Die First HD-FO Die Last HD-FO Face Down Die Placeent RDL and Cu Pillar on Carrier RDL on Carrier Metal Carrier Molding and Carrier Reoval RDL and BGA Attach Singulation Glass Carrier Face Up Die Placeent Glass Carrier Molding, Thinning/Cu Via Exposure Glass Carrier RDL and BGA Attach Silicon Carrier Face Down Die Placeent Silicon Carrier Molding Silicon Carrier Carrier Reoval, RDL and BGA Attach Glass Carrier Carrier Reoval Singulation Source: GlobalFoundries, adapted fro Akor, ASE, SPIL, STATS ChipPAC, TechSearch International, Inc., IFTLE, TSMC websites.

6 Thinner package and saller footprint Today 1.0 height requireent Future 0.8 3D IC with TSV provides the ultiate in package height reduction, but continues to be pushed out (theral, cost, business issues) Silicon interposers too expensive for any obile products PoP in high-end sartphones Option 1: Continue with FC on thin substrate Option 2: Ebedded AP in botto lainate substrate Option 3: Fan-out WLP with application processor as botto package Option 4: Soe new forat (RDL first/chip last, SWIFT, etc.) Apple selects InFO for AP in botto PoP Low profile High routing density Iproved electrical and theral perforance Syste integration with copetitive cost Co-design is key Application Processor: A Case Study Today s PoP (1.0) FO-WLP as Botto PoP (<0.8)

7 RF, PMIC, CODEC and AP, Migrating to FO-WLP Mode FCBGA-333 Qualco MDM9625M A-CPU PoP-1155 Apple/TSMC APQL- * M8 Co-pro. WLP-40 NXP LPC18B1UK PMIC WLP-94 Qualco PM8019 * * RFIC WLP-164 Qualco WTR1625L * RFIC WLP-66 Qualco WFR1620 * Audio codec WLP-42 Cirrus 338S1201 WiFi/BT/FM FLGA-58 Murata 343S0694 PMIC FCBGA-267 Dialog 338S1251 Source: TPSS. PMIC WLP-28 Qualco QFE1100 *

8 Reconstituted Wafer FO Alternatives to Reconstituted Wafer FO-WLP: Select the Right Solution for Your Application Akor s SWIFT ASE s FOCLP Akor s LCCSP Source: Akor. Source: Infineon. Conventional flip chip Molded Interconnect Substrate (MIS) Ebedded die solutions Source: ASE. IC IC Source: TDK. Source: SPIL.

9 ASE s FOCLP Uses low-cost coreless substrate Fine pitch capable (15µ L/S, 12µ L/S in developent) Manufactured in double panel forat Assebled in strip forat Multi-die and passives possible Can be botto PoP Thin package (<375 µ) MLS-1 Passed TCT 1,000 cycles, PCT 168 hours, HAST 168 hours, Drop test 150 (still going) High current and theral handling capabilities Due to thicker Cu (15-20 µ) Uses existing FC infrastructure FC with Cu pillar (direct die on pad, no RDL) ounted on coreless substrate Mass reflow and olded underfill Multi-Die Coreless Chip Last Package Source: ASE.

10 Akor s LCCSP Source: Akor.

11 Molded Interconnect Substrate External Terinal Top View Wire bond Terinal Bo o View Carrier Inner Lead for WB or FC Outer Lead with NiPdAu or OSP Outer Lead with NiPdAu or OSP Source: JCET. MIS-BGA offered by JCET (owns APS), Carse, SPIL and others Versions offered by other OSATs such as Akor and UTAC with routable QFNs

12 MIS Process Flow Providing a carrier Foring a trace layer Foring a via layer Foring a dielectric layer over the trace and via layer Reoving part of the dielectric layer to expose the via layer Reoving the carrier to expose the trace layer Leadfrae supplied by leadfrae aker using special process Liited nuber of leadfrae suppliers capable of supplying Source: APS.

13 SPIL FC-MISBGA Introduction SPIL s FC-MISBGA Package (Flip Chip Molded Interconnect Syste BGA) Flip Chip Molded Interconnection Syste BGA Top view of the substrate 1Layer FC-MISBGA 2Layer FC-MISBGA Features: Coreless substrate (no copper clad lainate core) Coreless Ebedded substrate trace technology: Copper better Clad trace Lainate adhesion to substrate core dielectric Ebedded layer trace technology better trace adhesion to substrate Fine trace: L/S=20/20µ, 15/15µ trace fored by ebedded trace dielectric technology, layer not SAP Fine Molding trace copound L/S=20/20,15/15u replaces prepreg trace are fored by ebedded trace Trace technology routability rather than SAP Material Little warpage innovation olding copound to replace prepreg Trace-routability Excellent electrical perforance Super Good warpage/theral/electrical/ and reliability perforance perforance Good theral and reliability perforance Source: SPIL.

14 MIS-BGA in Production MediaTek RF transceiver MediaTek PMIC MediaTek uses for RF transceiver Power anageent IC (PMIC) China obile phones such as OPPO Joy MediaTek RF transceiver Wire bonded die Body size 4.6 x 4.6 x solder balls Ball pitch 0.4 MediaTek PMIC Wire bonded die Body size 6 x 6 x solder balls Ball pitch 0.4 Considered low-cost package Source: TPSS and TechSearch International, Inc.

15 Ebedded Active Package Solutions ASE Ebedded Electronics (including new JV copany with TDK) AT&S DNP General Electric Infineon Source: Chipworks Microsei Schweizer Shinko Electric Taiyo Yuden TDK Source: TDK. Texas Instruents Uniicron Source: TI.

16 Qualco Snapdragon with Ebedded Die Snapdragon series Many sartphones

17 AT&S Ebedded Coponent (ECP ) Current High Volue Production Near Future High Volue Production In Developent Higher Power >500W Power Manageent 3D SiP and Modules Ebedding passives and ICs Advantages Reduced for factor X,Y & Z Lower Loop Inductance Iproved theral Iproved reliability Experience - 5 years volue production in a lainate panel process Increased 3D Coplexity All in One Package

18 TDK s SESUB Technology for SiP SESUB = Seiconductor Ebedded in SUBstrate IC wafer is thinned to 50µ and IC is ebedded in resin substrate Total substrate thickness is 300µ Source: ASE, TDK.

19 TDK Ebedded Die Applications Apple TV uses µdcdc odules in the reote controller (two per board) Low-energy Bluetooth odule Ultra sall package 4.6 x 5.6 x 1.0 TI s CC2541 IC inside substrate Bluetooth odule Dialog s DA ebedded in substrate TI s CC2541 IC inside substrate Typical uses and applications Healthcare/Sports & fitness equipent Wearables such as wristband, watch, ring glasses, shoes, hat, shirt Hoe entertainent equipent (reote control, sensor tag, toys, lighting) PC peripherals (ouse, key board, stylus, presentation pointer) Source: ifixit..

20 TDK s Tiny Bluetooth Low Energy Module for Sart Watches and Other Wearables Source: TDK. Bluetooth low-energy odule with IC ebedded into thin substrate, peripheral circuitry includes quartz resonator, bandpass filter, and capacitors on the top Package size of 4.6 x 5.6 x % saller than individual discrete coponents

21 Microsei Ebedded Die Module for ICD Qualified to MIL standard for iplantable devices Applicable in other high-rel spaces such as wearables, security, ilitary, and industrial sensing Evolution toward ultra-thin ebedded die, enabling laination thickness of 0.5 ; overall odule height typically 1.0 (discrete coponent liit) Integrated passives on the horizon New ebedded die design reduces area 400% 12.7 x 8.1 x 1.5 Die ebedded in the PCB Source: Microsei. 5.6

22 Conclusions Mobile devices drive thinner packages No single package eets all needs, ultiple choices for sae application FO-WLP Flip chip on thin core or coreless Ebedded die Copanies want to use the lowest cost package Must calculation trade-off in perforance vs. cost Copanies want to avoid confusion about package choices

23 Thank you! TechSearch International, Inc Spicewood Springs Road, Suite 150 Austin, Texas USA