Strategies for High Density and High Speed Packaging. Ride the Wave Workshop
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1 Strategies for High Density and High Speed Packaging Ride the Wave Workshop
2 Topics! Trends in Packaging! Common Design Challenges! Design through Software! Supply Plane Analysis with SIwave! Non-ideal Power/Ground Planes! Plane Impedance vs. Frequency! Package Design Automation with TPA 4.0! Broadband BGA Characterization! Bit-Error Rate (BER) Testing for BGA! Design Rule Generation from Simulation! Demonstration SIwave and TPA 4.0! Summary
3 Trends in Packaging Intel Microprocessor Product Advancement Freq: GHz Bus: 100 MHz (400 MTS) Wire bond Technology Freq: 800 MHz GHz Bus: 200 MHz (400 MTS) Speed/Complexity PIV OLGA2/INT PIII - Celeron FCPGA1 Freq: MHz Bus: 66/100 MHz Mobile OLGA1/INT Freq: MHz Bus: 100/133 MHz IA64 - Itanium OLGA2/INT PIII SECC Slot 1 Freq: 500 MHz GHz Bus: 100/133 MHz Freq: MHz Bus: 100/133 MHz PIII - Xeon SECC Slot Package Area (mm 2 ) [1]
4 Trends in Packaging Speed and Topology Issues! Broadband Behavior Critical! Clock Frequencies Continue to Increase! Edge Rates in the Tens of ps Range! Package structures more tightly coupled! Minimum Line Width decreasing! Solderball and Wirebond Pitch decreasing! Wide Range of Packaging Choices to understand! Chip-Scale Packaging (CSP)! Microball Grid Array (µbga)! Flip Chip! Stacked Bare IC s
5 Trends in Packaging Packaging and its Effects on Circuits VCO design with package effects neglected! VCO in Ansoft Serenade! Oscillation Freq. of 520 MHz
6 Trends in Packaging Packaging and its Effects on Circuits VCO design with package effects included! VCO in Ansoft Serenade! Extracted Package Parasitics included from Q3D Extractor! Oscillation Disappears Oscillation disappears!!
7 Trends in Packaging Design Flow of the 90s IC Designer Package Designer Final Component! IC Design and Package Design are Critically Linked! Packaging Effects MUST be Considered During Design Process
8 Trends in Packaging Design Flow for the this Century IC Designer Final Component Package Designer! IC Designer and Package Designer need to work together for success! Packaging has become its own discipline
9 Common Design Challenges! Reflection Noise! Impedance Mismatch, Vias, Other Discontinuities! Crosstalk Noise! Electromagnetic coupling between traces and vias! Power/Ground Noise! Non-ideal planes cause parasitic effects! Commonly referred to as Ground Bounce, Delta- I Noise or Simultaneous Switching Noise (SSN)! High Frequency Effects! Radiation, Resonances, Dispersion
10 Common Design Challenges Understanding Through Simulation Packaging structures and their PCB s contain complex signal paths with many types of 2D and 3D discontinuities. Successful designs require a good understanding of the signal path and the power delivery system. Signal Path Landmines:! Connectors, Split Planes, Vias! Multiple Substrates, Dispersive Substrates! Solder Balls, Bond Pads, Bondwires, Solderbumps! Parallel Plate Modes
11 Common Design Challenges Understanding Through Simulation Effective designs for advanced packaging evolve from an understanding of the fundamental Electromagetics. A total package analysis solution consists of:! Industry Standard Layout/Design Tools! Effective Quasi-Static Simulation/Extraction for low speed characterization! Full-Wave Analysis for critical high bandwidth applications! Circuit and System level analysis to integrate the results of simulations. These tools will help reduce design cycle time and save money in prototyping costs.
12 Common Design Challenges Methods Available for Simulation! Packaging simulation requires careful consideration of application needs.! Tools available across the spectrum of operating frequencies and electrical sizes 0 λ/100 λ/10! Quasi-Static! Spicelink Use a Quasi-Static Solver (OVERLAP)! TPA! Full-Wave! Ensemble w/full-wave Spice! HFSS w/full-wave Spice! SIwave! Circuit and System! Serenade! Symphony S21 First order Spicelink Lumped model is valid up to 2GHz! Problem Scale Use a FEM Full-Wave Solver HFSS Result First order Spicelink Result
13 Common Design Challenges Strategies Needed to Overcome Challenges Incorporate simulation in design flow: CAD Layout Data for Design Rule Generation or Validation AnsoftLinks TPA (3D BEM/NFM) RLC Spicelink (2D/3D FEM/BEM) Optimetrics /Modeling HFSS (3D FEM) Ensemble (2.5D MoM) RLC S-Parameters Modeling SIwave (FEM) S-Parameters RLC Distributed Model (PEEC) Lumped Model (RLC) Full-Wave Spice Full-Wave Spice SPICE Sub-Circuit PSpice HSpice Maxwell Spice PN Spice Harmonica
14 Common Design Challenges Strategies Needed to Overcome Challenges Design rules are needed for complex signal structures along with effective verification! Power Integrity! Parasitic Coupling! Package Resonances! Substrate Coupling! Dispersion! Circuit/Package Interaction
15 Power/Ground Resonances SIwave for Full-Wave Package and Board Analysis
16 Power/Ground Resonances
17 Power/Ground Resonances! Decoupling Capacitors are added to the board! Simulation is a quick way to develop design guidelines
18 Power/Ground Resonances
19 Plane Impedance vs. Frequency Structure! 50mm x 50mm! 0.8mm FR4 substrate! Two metal planes Simulation! Compute first twelve resonant modes! Compute S, Y, Z Parameters! Correlate Z11 with resonances Port 1 Port 2
20 Plane Impedance vs. Frequency ! First twelve resonant modes listed! Degenerate modes are grouped (these exist due to square planes)! Seven distinct frequencies are labeled and correlated with Z11 in the plot
21 Design Automation with TPA 4.0! New GUI with native Windows and UNIX versions! Interface to APD, Encore, Zuken CR5000! Lumped Extraction using Multipole technology from Q3D! Distributed Models using Multipole Accelerated PEEC! Automatic Partitioning for full package analysis! Support for all BGA style packages (i.e. CSP, Flip-Chip)
22 Design Automation with TPA 4.0! Easily select critical nets for analysis! Quickly define size and shape of supply planes to be included in analysis! Extract the parasitics for the entire package using Auto-Partitioning! Package data provided in matrix form and as Spice subcircuits
23 3D model of 4 Layer BGA Package for Broadband Simulation Net in green is connected to p-substrate contact. Net in gray is power trace. Net in red is differential trace. Net in deep blue is ground trace. To to make a good noise return path! Vss2 plane Assumed Chip_GND VDD2 plane Package s Vdd1 plane PCB_GND VDD3 plane Package s Vss1 plane Vss2 plane
24 Current Distribution with Single-ended 10GHz (single tone)
25 Rough Calculation of Signal Bandwidth For PRBS (Psuedo Random Bit Sequence) signal with the rate of 10Gbps, what will the signal bandwidth will be?? Amp db T 1 T b = 0. 1ns = Rule of Thumb for Signal Bandwidth = rise time T 0.35 b Let' s assume, T = Signal BW = = time 10 Tb 10 rise 35 10GHz 20GHz 30GHz 0.35 t rise time GHz Package is a kind of Low Pass Filter and signal distortion may come from large group delay near the high ripple frequency range of LPF. Therefore, designer need broadband accurate result to predict waveform distortion. Frequency selective channel due to package!!! Signal spectrum! freq 10GHz 20GHz 30GHz
26 Broadband Accurate S 31, S 42 for 4 Layer BGA (I.L. of TxD+) (I.L. of TxD-)
27 Broadband Accurate S 21, S 41 for 4 Layer BGA
28 Broadband Accurate S 11, S 22, S 33, S 44 for 4 Layer BGA
29 Broadband Accurate S 77, S 88, S 78 for 4 Layer BGA
30 Broadband Accurate S 55, S 66 for 4 Layer BGA
31 Bit Error Rate (BER) Testing for a Low Voltage Differential Signal (LVDS) with 4 layer BGA package as a Communication Channel Single-ended Waveform Testing in Symphony
32 Symphony s Waveform Check against Full-Wave SPICE Waveform Full Wave SPICE
33 BER Testing Setup in Symphony Data for DC Offset Calibration DC Offset Calibration Creation for LVDS Clock Recovery Section With Early/Late Gate Implementation
34 Post Channel Waveform for High SNR 10 Gbps DC Calibration Eye open ~360mv 20 Gbps Eye open ~275mv
35 BER Testing Result in Symphony 20Gbps 10Gbps
36 CORPORATE OVERVIEW ConnectCom MicroSystems Inc. is a Venture Capital backed Internet Chip Company. It designs and manufactures ultralow power, very high-speed analog and mixed-signal integrated circuits (ICs). These ICs enable and support terabit optical switching equipment and networks that form the new backbone infrastructure for the exploding Internet traffic. ConnectCom employs innovative and patented designs techniques that are technology independent; to achieve power savings of up to 70% over traditional solutions for standards compliant SONET and SDH based applications. This will allow the company to offer superior, predictable economies, reliability and flexibility to the system designers of switch fabrics, DWDM equipment and optical modules. Flip-Chip BGA Package design courtesy of ConnectCom MicroSystems Inc.
37 BGA: Design Example AnsoftLinks IGES, STEP, GDSII, ACIS, DXF, AutoCAD APD Allegro Encore Zuken 3D Physical Model
38 BGA: Design Example How do we figure out what matters?! Dissect a pair of critical nets and a victim net! Initial design Gb/s Flip-Chip BGA, that was routed using Cadence Advanced Package Designer(APD).! 3D Solid Model is extracted from APD using AnsoftLinks.! Goal: Use Strategic Simulation for improving package performance at higher data rates (25 GHz Bandwidth) Critical Nets Power Net Ground Net Victim Net Return Path Power Signal Net Ground Net Via Solder Balls
39 BGA: Design Example! For initial analysis, create an equivalent circuit model using Ansoft Serenade, assuming:! Nets are on the top layer(trace layer)! Infinite ground/dielectrics and zero thickness traces! The via pads and solder mask are ignored! Approximate trace dimensions and spacing! Demonstrate correlation between tools and show the benefit of first-order design iterations HFSS Model A B C t-line models Ensemble Model Multi-Coupled Line Models (MCPL)
40 BGA: Design Example! Serenade is acceptable comparing with 3D HFSS model S11! Variations in the cross-talk can be attributed to the assumption of uniform spacing, used in the Serenade model, for Section B(See previous slide). Serenade Model! The approximate dimensions used in the Serenade model can be shown to account for the frequency shift. S11! By replacing the transmission line models in Section A with multicoupled lines, the accuracy of the Serenade model can be improved to capture the resonance frequencies that occur above 30GHz. Since this is above the frequency band of interest, we will continue to use the current model. HFSS Model
41 BGA: Design Example! The size of the return path does not appear to have a major impact on the performance. S11! This is further validation that the infinite ground assumption used for the Serenade and Ensemble models is valid.! If we look closer, the finite return path does appear to influence the crosstalk. We will need to investigate and develop guidelines for trace placement relative to the edge of the return path. HFSS Model (Large Return Path ) S11 HFSS Model (Finite Return Path )
42 BGA: Design Example! We see good correlation between Ensemble and HFSS.! In the Ensemble model we used probe ports and assume an infinite ground plane.! Unlike Ensemble, HFSS does not explicitly define ground planes. This will be important as we proceed with the BGA analysis. S11 S11 Ensemble Model (Infinite Ground )! Since Ensemble is only solving for the currents on the conductors, it is considerably faster than HFSS for this problem. HFSS Model (Large Return Path )
43 BGA: Design Example Viewing the Complex Magnitude of the E-Field in HFSS or Magnitude of J in Ensemble reveals that the guard trace(ground Net) is causing some problems. Ansoft HFSS Ground Net Guard trace is ~λ/2 ~ at 24GHz Ground Net Ansoft Ensemble The Fast Frequency Sweep capabilities in Ansoft HFSS computes S- Parameters and field solutions, swept over frequency, in a single simulation. This allows the engineer to quickly identify, using the Fields Post Processor, any anomalies in the S-Parameters without re-solving.
44 BGA: Design Example It is interesting to note, that if the multi-coupled line models are replaced with a simple microstrip model, the resonance problem that was caused by the guard trace would not have been identified using a circuit tool.! There is no substitute for accurate broad-band models in a circuit simulator! microstrip MCPL
45 BGA: Design Example Since we are getting good agreement between the circuit and field simulator, lets continue to investigate several iterations of the design using only the circuit tool.! First, lets remove the guard trace.! We fixed the resonance, but the system does not appear to be 50Ω S11
46 BGA: Design Example There are several possibilities that could account for the impedance of the transmission lines! We made assumptions about the trace thickness, took liberties with the stack-up, and failed to make adjustments to the trace width.! The Ansoft Serenade Transmission Line Designer reveals that the line impedance is ~100Ω Renormalized to 100 Ω
47 BGA: Design Example! To investigate the stack-up, trace thickness, trace spacing, and trace to edge spacing, we will utilize Spicelink 2D
48 BGA: Design Example Characteristic Impedance vs. Trace Width W d Backward(Near-End) Crosstalk vs. Trace Separation
49 BGA: Design Example Impedance vs. Trace to Ground Edge Spacing l
50 BGA: Design Example! Based on the design rules we generated using Ansoft Spicelink 2D lets pick some guidelines for improving the layout we currently have.! Design Rule: maintain 0.2mm Trace to Ground! Expectation: less then a 0.5Ω impedance variation compared to a trace centered on the return path.! As the rise-times increase, re-routing non-critical nets will become essential to the performance of the the critical nets. The victim net (a non-critical net) may have to be moved. Trace to Edge keep out
51 BGA: Design Example! Design Rule: maintain 0.5mm trace to trace! Note: It is impossible to maintain this spacing with the pin-to-pin spacing at the Die. Removing the victim net could become necessary if the the coupling is determined to be unacceptable.! Before we physically change the routing, lets update our Ansoft Serenade model and quickly verify the design guidelines we have chosen. Trace to Trace Separation
52 BGA: Design Example Renormalized to 100 Ω No Via Pads S11! The Ansoft Serenade model was modified to simulate our new layout design rules.! In addition, the via pads were added to the model. It is obvious from the simulation that something will have to be done to improve the match between the via pad and the transmission lines. Investigation of the via in more detail is recommended.! Ansoft Ensemble was used to verify the circuit model. S11 S11 Renormalized to 100 Ω Via Pads Renormalized to 100 Ω Ansoft Ensemble
53 Summary! Feature Sizes are Decreasing! Clock Frequencies/Edge Rates are Increasing! Digital Design is faced with RF issues! Wide Range of Packaging Choices! Good Design Rules can be Generated with the Appropriate Simulation Tools! Simulation tools can be used to dissect Packages to understand the signal path! Full Packages can be simulated for verification! Successful designs with reduced costs and design cycle time are possible with IC and Package Designers working together through Simulation
54 References [1] David C. Wittwer, William P. Pinello, Intel Corporation, Investigation of Power and Ground Plane Resonance, National Radio Science Meeting, Boulder, CO, Jan. 8-11, 2001
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