Five Emerging Technologies that will Revolutionize High Speed Systems

Transcription

1 lide - 1 Five Emerging Technologies that will Revolutionize High peed ystems Dr. Eric Bogatin, CTO eric@gigatest.com GigaTest Labs 134 Wolfe Rd unnyvale, CA Presented at the High-peed Communications Alliance, June 26, 2003 lide - 2 Overview ituation analysis Three significant challenges in high speed systems Five important solutions

2 lide - 3 High-speed is when the interconnects are no longer transparent to signals Rise times < 1 nsec Clock frequencies > 100 MHz rf frequency components > 100 MHz lide - 4 Three Trends Drive the Industry Globally competitive market time to market shrinking cost major driving force maller transistor feature sizes rise times decreasing clock frequencies increasing Higher yield for larger die bus widths increasing larger percentage of nets are critical nets

3 lide - 5 High-peed Will Dominate Digital products horter rise time Higher clock frequency Higher bandwidth Higher data rate Voltage -V Time (ns) RF/wireless products Higher carrier frequency Narrower bandwidths Higher channel isolation Higher frequency spectrum 0.1 GHz Digital TV PC, satellite radio, WC 1 GHz Ultra wide band DB (direct broadcast satellite) 10 GHz ACR (anti collision radar) LMD (local multipoint distribution system) 100 GHz lide - 6 The Treadmill of Higher On-Chip Clock Frequency BW ~ 5 x F clock Clock Frequency, MHz Intel Processors IA Roadmap 1 doubling every 2 years Year

4 lide - 7 High peed erial Link Applications Drive High Frequency Hypertransport AGP8x 3GIO Infiniband OC-48 OC-192 RapidIO16 OC Gbps (400 MHz- 1.6 GHz) 2.1 Gbps (533 MHz) 2.5 Gbps (2 x 1.25 GHz) 2.5 Gbps (2.5 GHz) Gbps ( 2.5 GHz) Gbps ( 10 GHz) 32 Gbps (1 GHz, 16 bit mode) Gbps ( 40 GHz) lide - 8 Three Important Challenges for High peed ystems Rise time degradation, II, collapse of the eye diagram Rail collapse in the power distribution system (PD) Reduced design cycle times

5 lide - 9 The Problem: Rise Time Degradation 1. Rise time degradation 2. Intersymbol interference (II) 50 psec rise time input 2 nsec/div (time offset) Output signal after 36 microstrip in FR4 Measured with Agilent 83480A Mainframe TDR/TDT 3. Collapse of the eye diagram, deterministic jitter lide - 10 The Root Cause The problem: rise time degradation The cause: Losses in the conductor Losses in the dielectric Impedance discontinuities from vias, connectors, termination components, packages

6 lide - 11 Enabling Technology olutions 1. Low loss laminates 2. Integrated passives 3. CPs (adaptive pre-emphasis and equalization!) lide - 12 Laminate Dissipation Factor 30 inches long 50 Ohm line 10 mil wide tan(δ) = 0 α = 2.3 x f x tan( δ)x εr α = the attenuation in db/inch f = the sine wave frequency component in GHz tan(δ) = the material dissipation factor ε r = the dielectric constant db / inch 30 inches long 50 Ohm line 10 mil wide tan(δ) = psec rise time initial signal 50 psec/div imulated with Mentor Graphics Hyperlynx 30 inches long 50 Ohm line 10 mil wide tan(δ) = 0.02

7 lide - 13 Enabling Technology: 1. Low Loss Laminates Minimize cost premium by only using low loss material on selected layers Example: Rogers RO4350B, tan(δ) = Cross section of RO4350B multilayer with FR4 layers Courtesy of Greg Bull, Rogers Corp lide - 14 Problem: Any parasitics cause rise time degradation Parasitics: any structure that is not a uniform transmission line Vias Termination resistors Packages Connectors 30 inches long 50 Ohm line 10 mil wide tan(δ) = 0 30 inches long 50 Ohm line 10 mil wide tan(δ) = inches long 50 Ohm line 10 mil wide tan(δ) = with 4 vias

8 lide - 15 maller ize Resistors Will Have Lower Parasitics Axial lead resistor Measured impedance of terminating resistors axial lead resistor MT resistor MT resistor IPD resistor 20 mils IPD resistor L,C depends on specific mounting features of the component, and the board stack up MT Axial IPD R 51 Ohms 51 Ohms 50 Ohms L 1.85 nh 8.0 nh < 0.05 nh C pf 0.4 pf < 0.02 pf lide - 16 Conventional Enabling Technology: 2. Integrated Passives Example: Omega-Ply LTCC IPOC: integrated passives on chip

9 lide - 17 Example: Xilinix Xcite technology- Digitally Controlled Impedance (DCI), on-chip termination lide - 18 Enabling Technology: 3. mall Package Parasitics- chip scale packages (CP) National emiconductor Tessera µbga

10 lide - 19 Enabling Technology: CP with Integrated Passives Example: Tessera Pyxis Packaging technology (for Rs, Cs) lide - 20 The Problem: Rail Collapse A voltage drop between V cc and V ss or V dd and V ss V dd V ss rail collapse at various locations in vicinity of 300 MHz processor chip 50 mv/div 2 µsec Clock period is 3 nsec Hi activity start

11 lide - 21 The Root Cause The root cause: voltage drops in the PD because of a di/dt through the impedance of the PD interconnects To regulator C decoupling lide - 22 The olution: Lower Impedance of the PD Power supply voltages will decrease Current draw will increase PD impedance requirements will decrease 1 Maximum PD Impedance, Ohms Projected PD impedance requirements for high end server mother boards ub milliω Year ource: un Microsystems

12 lide inch x 10 inch board with 5, 2 mil thick dielectric between power and ground plane pairs Only 2 plane pairs connected to the vias Board courtesy of Istvan Novak, un Micro) lide - 24 Measured Impedance of the Planes Impedance, Ohms 1 1E-1 1E-2 No caps With 4 IDC caps, 20 µf Nothing we add to the planes will impact their impedance above 200 MHz (1/2 λ for 10 inch board) Planes shorted at capacitor pads 1E-3 1E7 1E8 Frequency, Hz 1E9 6E9

13 lide - 25 Enabling Technology: 4. Thin Laminates Loop inductance per square of the power/ground planes: len Dielectric thickness, h len len L loop = µ 0 h = h x 33pH / mil w w If len = w, i.e., a square, then: L loop = h x 33 ph/mil Thinner dielectric means lower inductance lower impedance w Z 0 ~ h ε r Design goal: thin laminate, high dielectric constant lide - 26 Rail Collapse Noise Reduction by Ultra Thin Dielectric Examples of various buried capacitor layers 0.5v/div 5 nsec/div C-Ply from 3M: 8 micron thick dielectric Dielectric constant of ~ 20 No decoupling caps! Courtesy of Lee Patch, National Center for Manufacturing cience

14 lide - 27 Example: anmina ZBC 2000: 50 µ thick, ε r ~ 4 8 layer board stack up lide M C-Ply: 8 µ thick, ε r ~ 20 ource: 3M, Joel Peiffer

15 lide - 29 Problem: High peed Product Design will only get Harder Frequencies are going up Design cycle times are going down time lide - 30 The olution: More efficient tools Key ingredient to the new high speed design methodology: predictability (analysis) Measurement (characterization) is essential to reduce risk

16 lide - 31 Enabling Technology: 5a. 3D full wave field solvers Example: Ansoft s High Frequency tructure imulator (HF) Optimizing via design for minimal impedance discontinuity Courtesy Ansoft Corp lide - 32 imulating Return Loss From Vias Return Loss (db) Courtesy Ansoft Corp

17 lide - 33 Enabling Technology: 5b. 4 Port Vector Network Analyzer Example: GigaTest Probe tation, Agilent PLT, lide Port VNA Differential Pair Backplane Analysis

18 lide - 35 Everything you every wanted to know about the differential channel is in the 4 port differential parameter matrix Diff pair port 1 Differential ignal Port 1 DD11 DD21 CD11 CD21 (and their return paths!) timulus Port 2 DD12 DD22 CD12 CD22 Common ignal Port 1 DC11 DC21 CC11 CC21 Diff pair port 2 Port 2 DC12 DC22 CC12 CC22 DD11 DD21 CC11 CC21 CD11 CD21 differential impedance profile ignal quality of differential signal, time delay of differential signal Common impedance profile ignal quality of the common signal, time delay of common signal Conversion of differential signal to common signal in reflection Conversion of differential signal to common signal in transmission lide - 36 Backplane Differential Pair Analysis Unbalanced Parameters Balanced Parameters

19 lide - 37 Balanced Time Domain Response DD11 DD21 CC11 CC21 CD11 differential impedance profile ignal quality of differential signal, time delay of differential signal Common impedance profile ignal quality of the common signal, time delay of common signal Conversion of differential signal to common signal in reflection CD21 Conversion of differential signal to common signal in transmission lide - 38 ummary Challenges Rise time degradation, II, collapse of the eye diagram olutions Minimize dissipation factor Minimize parasitics Enabling Technologies 1. Low loss laminates 2. Integrated passives 3. Chip scale packages Rail collapse Minimize PD impedance 4. Thin laminates High speed design gets harder More efficient tools 5a. 3D full wave solvers 5b. Four port VNAs

20 lide - 39 For more information Published by Prentice Hall Available ept 1, 2003 Pre-order from Amazon.com