The Challenges of Differential Bus Design
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1 The Challenges of Differential Bus Design February 20, 2002 presented by: Arthur Fraser TechKnowledge Page 1
2 Introduction Background Historically, differential interconnects were often twisted wire pairs the desired differential signal propagated well, & common mode noise propagated poorly. Current designs use stripline, with many ground planes. Common mode signals now propagate very well. Differential signaling has mystic if same thing is done to both traces, the differential signal will always get through. This is a bad assumption Page 2
3 Introduction Silicon to Silicon Signal Channel Die Trace Package Card Typical system may have differential pairs Examples include clock distribution; serial links; data bus. PCB Trace Backplane Die Package Card Connector Page 3
4 Introduction Typical Project Deliverables Silicon to Silicon Model Circuit Board Design Rules Circuit Board Stackup, Size, Thickness Trace Widths and Spacings Driver and Receiver Requirements Rise Time Impedance, differential and common mode Common mode range Package Requirements Page 4
5 Introduction Why Use Differential Signaling? Advantages: Reduced ground return currents Greater tolerance to simultaneous switching noise Lower EMI Disadvantages 2X more wires Greater Design complexity Modes Cross Talk Page 5
6 Agenda Choosing a Simulator Choosing Differential Topology Managing Reflections Modeling Multiple Grounds Measuring Via Capacitance Measuring Differential Impedance Page 6
7 Choosing a Simulator Tightly edge coupled electric fields Differential Mode Common Mode Lo Hi Page 7
8 Choosing a Simulator Loosely Edge Coupled electric field Differential Mode Common Mode Lo Hi Page 8
9 Choosing a Simulator Differential Mode Current density Loosely Coupled End view of traces Top view of traces Tightly Coupled Lo Hi Page 9
10 Choosing a Simulator Transmission Line Models Complex field behavior affects impedance, cross talk and dielectric loss. Current crowding impacts skin effect loss. Requires an accurate transmission line models that predict this behavior. Multilayer Suite (ADS 2001) provides field solver accuracy at near circuit simulator speeds. Page 10
11 Choosing a Simulator How is ADS different than SPICE Able to transform any kind of frequency domain response into the time domain (red traces). SPICE simulators use more idealized models, giving optimistic results (blue traces). ADS Convolution Transient Simulator Page 11
12 Choosing Differential Topology Many differential trace layout options Edge Coupled Edge tightly coupled Side View Ground Plane Trace Broadside Broadside-Offset Edge-Offset Page 12
13 Choosing Differential Topology How to model differential traces in ADS 4 Layer Substrate 2-Trace Tline Model MLSUBSTRATE4 Up to 40 layers ML2CTL_V Er[1]=3.5 Subst1 H[1]=5.7 mil TanD[1]=0.04 T[1]=1.4 mil Cond[1]=5.7e7 Layer 2 Parms Layer 3 Parms Layer 4 Parms LayerType[1]=ground LayerType[2]=signal LayerType[3]=signal LayerType[4]=ground Up to 16 traces Substrate ID "power" "ground" "signal" or "blank" Sets trace to layer # Subst="Subst1" Length=10 in W[1]=7.0 mil S[1]=10 mil W[2]=7.0 mil Layer[1]=2 Layer[2]=3 Page 13
14 Choosing Differential Topology Simulating Differential Impedance VtPuls e vtdr_pos Vlo w=0 V 50 Ohm TLIN Vhig h=1v Z=50.0 Ohm Rise=100 psec vtdr_neg VtPuls e 50 Ohm Vlo w=0 V Vhig h= -1V Rise=100 psec TLIN Page 14 ML2CTL_C vtdt_pos vtdt_neg Subst="Subst1" Le ngth=10 in W=6 mil S=spacing mil Laye r=2 50 Ohm TDR Step Generator Tline under test Node names in red edge-coupled spacing is edge-to edge
15 Choosing Differential Topology Edge coupled TDR Results Parameter Sweep clearly shows performance trade-offs 100 Ohm reference Tline 250 ps long Slope due to series R Width=6 mils Impedance equations: Eqn diff_imped=100*(1+diff_tdr) /(1-diff_tdr) Eqn diff_tdr=vtdr_pos-vtdr_neg-1.0 spacing W=6 mils 6 mils 0.7 mils 6 mils Page 15
16 Choosing Differential Topology Broadside Coupled Impedance Broadside Z increases as offset increases Z sensitivity is minimal when traces overlap. ML2CTL_V Subst="Subst1" Length=10 in W[1]=6.0 mil S[1]=spacing mil W[2]=6.0 mil Layer[1]=2 Layer[2]=3 Page 16 W=6 mils Offset 6 mils 0.7 mils 8 mils 0.7 mils 6 mils
17 Managing Reflections Block Diagram The differential driver voltage in previous slide illustrates how reflected energy can cause serious problems. If driver voltage range is exceeded, its impedance will change in unexpected ways. Because multiple reflections can occur, a good simulator is mandatory. Page 17 Driver Reflected Energy Connector Transmitted Energy Receiver
18 Managing Reflections Reflected signals from Via Capacitance vdriver_pos SRC1 50 VtBitSeq vdriver_neg 50 SRC2 VtBitSeq TLIN 250ps TLIN 250ps C=viacap1 pf C1 C2 ML2CTL_V CLin1 vout_pos vout_neg C=viacap2 pf Driver Package Via Cap and Diff Tline Viacap 1=1 pf; ViaCap2 swept 0.5,0.75,1.0,1.25,1.5 pf. 50 Page 18
19 Managing Reflections Output Signal One via capacitance swept, 0.5,0.75,1.0,1.25,1.5 pf; other via=1.0 pf The unbalanced capacitive load to ground generates common mode signals. Page 19
20 Managing Reflections Driver Signal Note how reflections from via capacitance cause driver voltage to exceed it normal range. Other variables can be swept: loss tan, trace width, rise time, termination R, etc. ADS can import silicon models for increased accuracy. Page 20
21 Referencing the correct ground Block Diagram Two different ground plane references Grounds connected by an inductor How to model this situation correctly? Connector Ground Inductance GND 1 GND 2 Circuit Board 1 Circuit Board 2 Connector Page 21
22 Referencing the correct ground Simulation with two grounds: node 0 & com 50 Driver Z=50 vdriver_pos vdriver_neg Z=50 ML2CTL_V L=0.1 nh L=0.1 nh ML2CTL_V com Skew L=1.0 nh Delay Tline1 Connector Tline2 vout_pos com vout_neg Page 22
23 Referencing the correct ground Simulated Results Data is wrong, but looks good. Compare with plots 3 slides ahead Tline2 implicitly references Node 0 Solution is to use a data set which allows referencing any node. Page 23
24 Referencing the correct ground Schematic to make a data set S-parm ports 1 & 3 Tline S-parm ports 2 & 4 Term1 Num=1 Z=50 Term3 Num=3 Z=50 ML2CTL_V CLin2 Term4 Num=4 Z=50 Term2 Num=2 Z=50 Tline is the transmission line model that needs to reference an alternate ground. Page 24
25 Referencing the correct ground Block Diagram with data set for Tline 2 50 vdriver_pos L=0.1 nh vdriver_neg L=0.1 nh ML2CTL_V 1.0 nh File="gnd_float_ dataset.ds" Ref S4P vout_pos vout_neg com Driver Skew Delay Tline1 Connector Tline2 as a Data set Page 25
26 Referencing the correct ground Block Diagram Data looks much different than plots 3 slides back. Use data sets to reference Tlines to other nodes. Page 26
27 Measuring Via Capacitance Via Capacitance origin Vias can be modeled with L s and C s The via C usually most important in 50 Ohm systems Via C difficult to algorithmically predict due to complex electric fields Best to directly measure Page 27
28 Measuring Via Capacitance Measurement Setup 8720ES Network Analyzer Coax Connector Ground Contact Signal Contact Via Under Test Page 28
29 Measuring Via Capacitance Layout Rules for Probing Typical probe pitch is 450um; can go as large as 1200um. Probes require ground nearby. Optional test trace used for impedance measurements, etc. Many other structures can be measured. Microprobe tip contacting signal & ground. Top View optional test trace Gap~10 mils. Ground Via (~20 mil dia, is connected to all ground planes.) Page 29
30 Measuring Via Capacitance Calibration Network analyzer uses calibration to remove response of cables, probes. Takes about 5 min. Expect < 1% overall error. Expect < 1% probe repeatability error After Calibration, what is measured is only what is beyond the probe tips. Micro Probe Tip Calibration Substrate Short Open Load Thru Page 30
31 Measuring Via Capacitance Modeling Via C Measured data obtained from ADS Instrument Server; stored as data set in ADS Top circuit re-generates measured data; bottom excites RC model. Adjust C to match phase response; R to match loss S-parm ports; Term1 Num=1 Z=50 Ohm Term2 Num=2 Z=50 Ohm Port1 is measured data; Port2 modeled Measured data from data set 1 S1P Ref SNP1 File="via_ measured2.ds" R1 R=1.5 Ohm C1 C=1.25 pf Via Model Page 31
32 Measuring Via Capacitance Measured vs. Modeled Top plot is phase response vs. frequency in GHz. Measured is Red, and modeled is Blue Bottom plot is db(s11), which indicates loss, Via C = 1.25 pf, for this example. Page 32
33 Measuring Differential Impedance Measurement Setup PC running ADS with GPIB link 86100A/ 54754A TDR MicroProbe Connection to Traces Same probes as used for via cap measurements Same probe launch requirements ADS instrument server acquires data through GPIB Page 33
34 Measuring Differential Impedance Measurement Setup Probe are placed using a positioner Typically takes 5 min to position test board for first measurement Typically takes 1 min to move probe to new site Page 34
35 Measuring Differential Impedance Measurement Calibration Agilent TDRs have two calibration modes Normalization Reference plane cal Reference plane cal sets the system impedance, and allows TDR displays in Ohms Normalization adds additional feature of removing the response of the probe and cables, and providing a known edge rise time at the probe tip. Page 35
36 Measuring Differential Impedance Traditional TDR Response, 200 mv step Via Discontinuity Transmission Line Slope due to series R Open circuit end of transmission line Page 36
37 Measuring Differential Impedance Measured vs. Modeled Differential impedance is with both channels connected. Multilayer Suite Models. Note measured matches modeled. Multiply by 2 to get differential impedance, because only 1 channel response plotted. Page 37
38 Conclusions & Recommendations High performance backplanes, packages, cannot be designed without a suitable simulator. ADS tools are outstanding for differential bus design because they: Accurately models virtually any differential trace configuration and layout. Includes dispersive effects due to skin effect and dielectric loss. Accurately models multiple ground references. Network Analyzer (8720ES) is the best instrument for highly accurate characterization measurements. Page 38
39 Conclusions & Recommendations TDR (86100A/54754A) is the best instrument for accurate differential impedance measurements. Designing high speed back planes is a complex and often difficult task requiring 1000 s of simulations. The next few steps in the design process include, modeling cross talk & common mode signals, importing silicon driver models, and optimizing signal trace density. Page 39
40 Resources Router & Switch design/test resources TechKnowledge specializes in high speed back plane and package design. GigaTest Labs specializes in probe stations, positioners. For more information on Multilayer Suite: nterconnect.pdf See Resource Page at end of presentation for more URLs TechKnowledge Page 40
41 Test & Measurement Updates Keep up to date with Agilent's free Test and Measurement Updates. As a subscriber, you will receive customized updates that match your subject and frequency interests. Your updates will include support, products and services, applications, promotions, events and other areas. Subscribe today: Our Privacy Statement at describes our commitment to you regarding your privacy. Please direct any questions about Agilent's privacy program to privacy_advocate@agilent.com. Page 41
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