Lecture Perspectives. Administrivia

Size: px
Start display at page:

Download "Lecture Perspectives. Administrivia"

Transcription

1 Lecture Perspectives Administrivia Final on Friday May 18 12:30-3:30 pm» Location: 251 Hearst Gym Topics all what was covered in class. Review Session Time and Location TBA Lab and hw scores to be posted on the web please check if correct or if something is missing Poster Session Phase III May 8, 3:30-6:30pm» Sign-up sheet posted HW8 posted; will not be graded. FEEDBACK ON COURSE EXTREMELY WELCOME! 1

2 Today s Design Methodologies Will Not Scale Much Further The Deep Sub-Micron (DSM) Effect ( 0.25µ) DSM Microscopic Problems Wiring Load Management Noise, Crosstalk Reliability, Manufacturability Complexity: LRC, ERC Accurate Power Prediction Accurate Delay Prediction etc. Everything Looks a Little Different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! The Productivity Gap Logic Transistors per Chip (K).10µ.35µ 2.5µ 10,000,000 1,000, ,000 10,000 1, Logic Transistors/Chip Transistor/Staff Month 58%/Yr. compound Complexity growth rate x x x x x x x %/Yr. compound Productivity growth rate ,000,000 10,000,000 1,000, ,000 10,000 1, Source: SEMATECH Productivity Trans./Staff - Month 2

3 Implementation Methodologies Digital Circuit Implementation Approaches Custom Semi-custom Cell-Based Array-Based Standard Cells Compiled Cells Macro Cells Pre-diffused Pre-wired (Gate Arrays) (FPGA) Custom Design Layout Editor Magic Layout Editor (UC Berkeley) 3

4 Cell-based Design (or standard cells) Feedthrough Cell Logic Cell Rows of Cells Functional Module (RAM, multiplier, ) Routing Channel Routing channel requirements are reduced by presence of more interconnect layers Standard Cell Example [Brodersen92] 4

5 Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies Gate Array Sea-of-gates polysilicon V DD rows of uncommitted cells GND metal possible contact Uncommited Cell In 1 In 2 In 3 In4 routing channel Committed Cell (4-input NOR) Out 5

6 Sea-of-gate Primitive Cells Oxide-isolation PMOS PMOS NMOS NMOS NMOS Using oxide-isolation Using gate-isolation Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 µm CMOS) 6

7 Prewired Arrays Categories of prewired arrays (or fieldprogrammable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based Programmable Logic Devices PLA PROM PAL 7

8 EPLD Block Diagram Primary inputs Macrocell Courtesy Altera Corp. Field-Programmable Gate Arrays Fuse-based I/O Buffers Program/Test/Diagnostics Vertical routes Standard-cell like floorplan I/O Buffers I/O Buffers Rows of logic modules Routing channels I/O Buffers 8

9 Interconnect Programmed interconnection Input/output pin Cell Antifuse Horizontal tracks Vertical tracks Programming interconnect using anti-fuses Field-Programmable Gate Arrays RAM-based CLB CLB Horizontal routing channel switching matrix Interconnect point CLB CLB Vertical routing channel 9

10 RAM-based FPGA Basic Cell (CLB) Combinational logic Storage elements R A B/Q1/Q2 C/Q1/Q2 D Any function of up to 4 variables F D in F G R D Q1 CE F A B/Q1/Q2 C/Q1/Q2 D Any function of up to 4 variables G F G R D Q2 CE G E Clock CE Courtesy of Xilinx RAM-based FPGA Xilinx XC

11 Addressing the Design Complexity Issue Architecture Reuse Reuse comes in generations Generation Reuse element Status 1 st Standard cells Well established 2 nd IP blocks Being introduced 3 rd Architecture Emerging 4 th IC Early research Source: Theo Claasen (Philips) DAC 00 Architecture ReUse Silicon System Platform» Flexible architecture for hardware and software» Specific (programmable) components» Network architecture» Software modules» Rules and guidelines for design of HW and SW Has been successful in PC s» Dominance of a few players who specify and control architecture Application-domain specific (difference in constraints)» Speed (compute power)» Dissipation» Costs» Real / non-real time data 11

12 Platform-Based Design Only the consumer gets freedom of choice; designers need freedom from choice (Orfali,, et al, 1996, p.522) A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer New platforms will be defined at the architecture-micro-architecture boundary They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations Key to such approaches is the representation of communication in the platform model Source:R.Newton Design at a crossroad System-on-a-Chip Multi- 500 k Gates FPGA Spectral RAM + 1 Gbit DRAM Imager Preprocessing 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS Analog µc system +2 Gbit DRAM Recognition Embedded applications where cost, performance, and energy are the real issues! DSP and control intensive Mixed-mode Combines programmable and application-specific modules Software plays crucial role 12

13 EE 141 Summary Digital CMOS Design is Kicking and Healthy Some major challenges down the road caused by Deep Sub-micron» Super GHz design» Power consumption!!!!» Reliability making it work Some new circuit solutions are bound to emerge Who can afford design in the years to come? Some major design methodology change in the making! 13

Lecture 30. Perspectives. Digital Integrated Circuits Perspectives

Lecture 30. Perspectives. Digital Integrated Circuits Perspectives Lecture 30 Perspectives Administrivia Final on Friday December 15 8 am Location: 251 Hearst Gym Topics all what was covered in class. Precise reading information will be posted on the web-site Review Session

More information

Digital Integrated Circuits Perspectives. Administrivia

Digital Integrated Circuits Perspectives. Administrivia Lecture 30 Perspectives Administrivia Final on Friday December 14, 2001 8 am Location: 180 Tan Hall Topics all what was covered in class. Review Session - TBA Lab and hw scores to be posted on the web

More information

18nm FinFET. Lecture 30. Perspectives. Administrivia. Power Density. Power will be a problem. Transistor Count

18nm FinFET. Lecture 30. Perspectives. Administrivia. Power Density. Power will be a problem. Transistor Count 18nm FinFET Double-gate structure + raised source/drain Lecture 30 Perspectives Gate Silicon Fin Source BOX Gate X. Huang, et al, 1999 IEDM, p.67~70 Drain Si fin - Body! I d [ua/um] 400-1.50 V 350 300-1.25

More information

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Design Methodologies December 10, 2002 L o g i c T r a n s i s t o r s p e r C h i p ( K ) 1 9 8 1 1

More information

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Design Methodologies December 10, 2002 L o g i c T r a n s i s t o r s p e r C h i p ( K ) 1 9 8 1 1

More information

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important! EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 12, 2016 VLSI Design and Variation Penn ESE 570 Spring 2016 Khanna Lecture Outline! Design Methodologies " Hierarchy, Modularity,

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell

More information

PROGRAMMABLE ASIC INTERCONNECT

PROGRAMMABLE ASIC INTERCONNECT PROGRAMMABLE ASIC INTERCONNECT The structure and complexity of the interconnect is largely determined by the programming technology and the architecture of the basic logic cell The first programmable ASICs

More information

ECE260B CSE241A Winter Design Styles Multi-Vdd/ Vth Designs. Website: / vlsicad.ucsd.edu/ courses/ ece260bw05

ECE260B CSE241A Winter Design Styles Multi-Vdd/ Vth Designs. Website:   / vlsicad.ucsd.edu/ courses/ ece260bw05 ECE260B CSE241A Winter 2005 Design Styles Multi-Vdd/ Vth Designs Website: / courses/ ece260bw05 ECE 260B CSE 241A Design Styles 1 The Design Problem Source: sematech97 A growing gap between design complexity

More information

PROGRAMMABLE ASICs. Antifuse SRAM EPROM

PROGRAMMABLE ASICs. Antifuse SRAM EPROM PROGRAMMABLE ASICs FPGAs hold array of basic logic cells Basic cells configured using Programming Technologies Programming Technology determines basic cell and interconnect scheme Programming Technologies

More information

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2) 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic

More information

FPGA Based System Design

FPGA Based System Design FPGA Based System Design Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 Why VLSI? Integration improves the design: higher speed; lower power; physically smaller. Integration reduces

More information

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

EC 1354-Principles of VLSI Design

EC 1354-Principles of VLSI Design EC 1354-Principles of VLSI Design UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY PART-A 1. What are the four generations of integrated circuits? 2. Give the advantages of IC. 3. Give the variety of

More information

Disseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor

Disseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor Disseny físic Disseny en Standard Cells Enric Pastor Rosa M. Badia Ramon Canal DM Tardor 2005 DM, Tardor 2005 1 Design domains (Gajski) Structural Processor, memory ALU, registers Cell Device, gate Transistor

More information

PROGRAMMABLE ASIC INTERCONNECT

PROGRAMMABLE ASIC INTERCONNECT ASICs...THE COURSE (1 WEEK) PROGRAMMABLE ASIC INTERCONNECT 7 Key concepts: programmable interconnect raw materials: aluminum-based metallization and a line capacitance of 0.2pFcm 1 7.1 Actel ACT Actel

More information

PE713 FPGA Based System Design

PE713 FPGA Based System Design PE713 FPGA Based System Design Why VLSI? Dept. of EEE, Amrita School of Engineering Why ICs? Dept. of EEE, Amrita School of Engineering IC Classification ANALOG (OR LINEAR) ICs produce, amplify, or respond

More information

CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology

CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology CMOS Digital Logic Design with Verilog Chapter1 Digital IC Design &Technology Chapter Overview: In this chapter we study the concept of digital hardware design & technology. This chapter deals the standard

More information

Lecture 9: Cell Design Issues

Lecture 9: Cell Design Issues Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE380 Digital Logic Implementation Technology: Standard Chips and Programmable Logic Devices Dr. D. J. Jackson Lecture 10-1 Standard chips A number of chips, each with a few logic gates, are commonly

More information

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design Harris Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture

More information

Technology Timeline. Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs. FPGAs. The Design Warrior s Guide to.

Technology Timeline. Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs. FPGAs. The Design Warrior s Guide to. FPGAs 1 CMPE 415 Technology Timeline 1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000 Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs FPGAs The Design Warrior s Guide

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: Digital Logic Circuits Chapter 3: Implementation Technology Curtis Nelson Chapter 3 Overview In this chapter you will learn about: How transistors are used as switches; Integrated circuit technology;

More information

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering FPGA Fabrics Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 CPLD / FPGA CPLD Interconnection of several PLD blocks with Programmable interconnect on a single chip Logic blocks executes

More information

Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques.

Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques. Introduction EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Techniques Cristian Grecu grecuc@ece.ubc.ca Course web site: http://courses.ece.ubc.ca/353/ What have you learned so far?

More information

BASICS: TECHNOLOGIES. EEC 116, B. Baas

BASICS: TECHNOLOGIES. EEC 116, B. Baas BASICS: TECHNOLOGIES EEC 116, B. Baas 97 Minimum Feature Size Fabrication technologies (often called just technologies) are named after their minimum feature size which is generally the minimum gate length

More information

Digital Systems Laboratory

Digital Systems Laboratory 2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD chk034@eng.ucsd.edu Lecture #2 1 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing

More information

CHAPTER III THE FPGA IMPLEMENTATION OF PULSE WIDTH MODULATION

CHAPTER III THE FPGA IMPLEMENTATION OF PULSE WIDTH MODULATION 34 CHAPTER III THE FPGA IMPLEMENTATION OF PULSE WIDTH MODULATION 3.1 Introduction A number of PWM schemes are used to obtain variable voltage and frequency supply. The Pulse width of PWM pulsevaries with

More information

Low-Power Digital CMOS Design: A Survey

Low-Power Digital CMOS Design: A Survey Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with

More information

Design Methodologies. Design Trade-offs. System Design to Hardware. Design Gap. Speed (throughput and clock frequency) Area and

Design Methodologies. Design Trade-offs. System Design to Hardware. Design Gap. Speed (throughput and clock frequency) Area and Design Trade-offs Design Methodologies Viktor Öwall Dept. of Electrical and Infomation Technology Lund University Parts of this material was adapted from the instructor material to Jan M. Rabaey, Digital

More information

1 Digital EE141 Integrated Circuits 2nd Introduction

1 Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits Introduction 1 What is this lecture about? Introduction to digital integrated circuits + low power circuits Issues in digital design The CMOS inverter Combinational logic structures

More information

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for

More information

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation

More information

1. Introduction. Institute of Microelectronic Systems. Status of Microelectronics Technology. (nm) Core voltage (V) Gate oxide thickness t OX

1. Introduction. Institute of Microelectronic Systems. Status of Microelectronics Technology. (nm) Core voltage (V) Gate oxide thickness t OX Threshold voltage Vt (V) and power supply (V) 1. Introduction Status of s Technology 10 5 2 1 0.5 0.2 0.1 V dd V t t OX 50 20 10 5 2 Gate oxide thickness t OX (nm) Future VLSI chip 2005 2011 CMOS feature

More information

EE141- Spring 2004 Digital Integrated Circuits

EE141- Spring 2004 Digital Integrated Circuits EE141- Spring 2004 Digital Integrated Circuits Lecture 27 Power distribution Resistive interconnect 1 Administrative Stuff Make-up lecture on Monday 4-5:30pm Special office hours of Prof. Rabaey today

More information

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM Semiconductor Memory Classification Lecture 12 Memory Circuits RWM NVRWM ROM Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Reading: Weste Ch 8.3.1-8.3.2, Rabaey

More information

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY

More information

Lecture Introduction

Lecture Introduction Lecture 1 6.012 Introduction 1. Overview of 6.012 Outline 2. Key conclusions of 6.012 Reading Assignment: Howe and Sodini, Chapter 1 6.012 Electronic Devices and Circuits-Fall 200 Lecture 1 1 Overview

More information

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203. DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING SUBJECT : EC6601 VLSI DESIGN QUESTION BANK SEM / YEAR: VI / IIIyear B.E. EC6601VLSI

More information

Field Programmable Gate Array

Field Programmable Gate Array 9 Field Programmable Gate Array This chapter introduces the principles, implementation and programming of configurable logic circuits, from the point of view of cell design and interconnection strategy.

More information

EECS 427 Lecture 21: Design for Test (DFT) Reminders

EECS 427 Lecture 21: Design for Test (DFT) Reminders EECS 427 Lecture 21: Design for Test (DFT) Readings: Insert H.3, CBF Ch 25 EECS 427 F09 Lecture 21 1 Reminders One more deadline Finish your project by Dec. 14 Schematic, layout, simulations, and final

More information

Academic Course Description

Academic Course Description BEC010- VLSI Design Academic Course Description BHARATH UNIVERSITY Faculty of Engineering and Technology Department of Electronics and Communication Engineering BEC010 VLSI Design Fifth Semester (Elective)

More information

EMT 251 Introduction to IC Design

EMT 251 Introduction to IC Design EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is

More information

Device Technology( Part 2 ): CMOS IC Technologies

Device Technology( Part 2 ): CMOS IC Technologies 1 Device Technology( Part 2 ): CMOS IC Technologies Chapter 3 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra, Department of Electronics and Telecommunication, Norwegian

More information

VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK VI SEMESTER EC6601 VLSI Design Regulation 2013 Academic Year 2017

More information

CS 6135 VLSI Physical Design Automation Fall 2003

CS 6135 VLSI Physical Design Automation Fall 2003 CS 6135 VLSI Physical Design Automation Fall 2003 1 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) 5742963 tcwang@cs.nthu.edu.tw Office hours: M56R5

More information

Leakage Power Minimization in Deep-Submicron CMOS circuits

Leakage Power Minimization in Deep-Submicron CMOS circuits Outline Leakage Power Minimization in Deep-Submicron circuits Politecnico di Torino Dip. di Automatica e Informatica 1019 Torino, Italy enrico.macii@polito.it Introduction. Design for low leakage: Basics.

More information

A Case Study of Nanoscale FPGA Programmable Switches with Low Power

A Case Study of Nanoscale FPGA Programmable Switches with Low Power A Case Study of Nanoscale FPGA Programmable Switches with Low Power V.Elamaran 1, Har Narayan Upadhyay 2 1 Assistant Professor, Department of ECE, School of EEE SASTRA University, Tamilnadu - 613401, India

More information

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.

More information

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

Academic Course Description

Academic Course Description BEC010- VLSI Design Academic Course Description BHARATH UNIVERSITY Faculty of Engineering and Technology Department of Electronics and Communication Engineering BEC010 VLSI Design Sixth Semester (Elective)

More information

Embedded System Hardware - Reconfigurable Hardware -

Embedded System Hardware - Reconfigurable Hardware - 2 Embedded System Hardware - Reconfigurable Hardware - Peter Marwedel Informatik 2 TU Dortmund Germany GOPs/J Courtesy: Philips Hugo De Man, IMEC, 27 Energy Efficiency of FPGAs 2, 28-2- Reconfigurable

More information

Lecture 1. Tinoosh Mohsenin

Lecture 1. Tinoosh Mohsenin Lecture 1 Tinoosh Mohsenin Today Administrative items Syllabus and course overview Digital systems and optimization overview 2 Course Communication Email Urgent announcements Web page http://www.csee.umbc.edu/~tinoosh/cmpe650/

More information

WHAT ARE FIELD PROGRAMMABLE. Audible plays called at the line of scrimmage? Signaling for a squeeze bunt in the ninth inning?

WHAT ARE FIELD PROGRAMMABLE. Audible plays called at the line of scrimmage? Signaling for a squeeze bunt in the ninth inning? WHAT ARE FIELD PROGRAMMABLE Audible plays called at the line of scrimmage? Signaling for a squeeze bunt in the ninth inning? They re none of the above! We re going to take a look at: Field Programmable

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 0 ELECTRONICS AND COMMUNICATION ENGINEERING TUTORIAL QUESTION BANK Name : VLSI Design Code : A0 Regulation : R5 Structure :

More information

Introduction to deep-submicron CMOS circuit design

Introduction to deep-submicron CMOS circuit design National Institute of Applied Sciences Department of Electrical & Computer Engineering Introduction to deep-submicron CMOS circuit design Etienne Sicard http:\\intrage.insa-tlse.fr\~etienne 1 08/09/00

More information

Learning Outcomes. Spiral 2 8. Digital Design Overview LAYOUT

Learning Outcomes. Spiral 2 8. Digital Design Overview LAYOUT 2-8.1 2-8.2 Spiral 2 8 Cell Mark Redekopp earning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as

More information

VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture- 05 VLSI Physical Design Automation (Part 1) Hello welcome

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 24: Peripheral Memory Circuits

CMPEN 411 VLSI Digital Circuits Spring Lecture 24: Peripheral Memory Circuits CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 24: Peripheral Memory Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11

More information

Computer Aided Design of Electronics

Computer Aided Design of Electronics Computer Aided Design of Electronics [Datorstödd Elektronikkonstruktion] Zebo Peng, Petru Eles, and Nima Aghaee Embedded Systems Laboratory IDA, Linköping University www.ida.liu.se/~tdts01 Electronic Systems

More information

Policy-Based RTL Design

Policy-Based RTL Design Policy-Based RTL Design Bhanu Kapoor and Bernard Murphy bkapoor@atrenta.com Atrenta, Inc., 2001 Gateway Pl. 440W San Jose, CA 95110 Abstract achieving the desired goals. We present a new methodology to

More information

Topics. Memory Reliability and Yield Control Logic. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Topics. Memory Reliability and Yield Control Logic. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut Topics Memory Reliability and Yield Control Logic Reliability and Yield Noise Sources in T DRam BL substrate Adjacent BL C WBL α-particles WL leakage C S electrode C cross Transposed-Bitline Architecture

More information

Digital Systems Design

Digital Systems Design Digital Systems Design Digital Systems Design and Test Dr. D. J. Jackson Lecture 1-1 Introduction Traditional digital design Manual process of designing and capturing circuits Schematic entry System-level

More information

EE 330 Lecture 44. Digital Circuits. Dynamic Logic Circuits. Course Evaluation Reminder - All Electronic

EE 330 Lecture 44. Digital Circuits. Dynamic Logic Circuits. Course Evaluation Reminder - All Electronic EE 330 Lecture 44 Digital Circuits Dynamic Logic Circuits Course Evaluation Reminder - All Electronic Digital Building Blocks Shift Registers Sequential Logic Shift Registers (stack) Array Logic Memory

More information

CMOS Technology for Computer Architects

CMOS Technology for Computer Architects CMOS Technology for Computer Architects Lecture 1: Introduction Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) Course Contents Implementation of high-performance digital

More information

Introduction to CMOS VLSI Design (E158) Lecture 5: Logic

Introduction to CMOS VLSI Design (E158) Lecture 5: Logic Harris Introduction to CMOS VLSI Design (E158) Lecture 5: Logic David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture 5 1

More information

Propagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012

Propagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012 Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis

More information

Propagation Delay, Circuit Timing & Adder Design

Propagation Delay, Circuit Timing & Adder Design Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis

More information

Programmable Interconnect. CPE/EE 428, CPE 528: Session #13. Actel Programmable Interconnect. Actel Programmable Interconnect

Programmable Interconnect. CPE/EE 428, CPE 528: Session #13. Actel Programmable Interconnect. Actel Programmable Interconnect Programmable Interconnect CPE/EE 428, CPE 528: Session #13 Department of Electrical and Computer Engineering University of Alabama in Huntsville In addition to programmable cells, programmable ASICs must

More information

Low Power VLSI Circuit Synthesis: Introduction and Course Outline

Low Power VLSI Circuit Synthesis: Introduction and Course Outline Low Power VLSI Circuit Synthesis: Introduction and Course Outline Ajit Pal Professor Department of Computer Science and Engineering Indian Institute of Technology Kharagpur INDIA -721302 Agenda Why Low

More information

Introduction to Electronic Design Automation

Introduction to Electronic Design Automation Introduction to Electronic Design Automation Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Spring 2014 1 Design Automation? 2 Course Info (1/4) Instructor Jie-Hong

More information

EEC 118 Lecture #12: Dynamic Logic

EEC 118 Lecture #12: Dynamic Logic EEC 118 Lecture #12: Dynamic Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Today: Alternative MOS Logic Styles Dynamic MOS Logic Circuits: Rabaey

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Low Power System-On-Chip-Design Chapter 12: Physical Libraries

Low Power System-On-Chip-Design Chapter 12: Physical Libraries 1 Low Power System-On-Chip-Design Chapter 12: Physical Libraries Friedemann Wesner 2 Outline Standard Cell Libraries Modeling of Standard Cell Libraries Isolation Cells Level Shifters Memories Power Gating

More information

Course Outcome of M.Tech (VLSI Design)

Course Outcome of M.Tech (VLSI Design) Course Outcome of M.Tech (VLSI Design) PVL108: Device Physics and Technology The students are able to: 1. Understand the basic physics of semiconductor devices and the basics theory of PN junction. 2.

More information

2 MARK QUESTIONS & ANSWERS UNIT1-MOS TRANSISTOR PRINCIPLE

2 MARK QUESTIONS & ANSWERS UNIT1-MOS TRANSISTOR PRINCIPLE 2 MARK QUESTIONS & ANSWERS UNIT1-MOS TRANSISTOR PRINCIPLE 1.What are four generations of Integration Circuits? _ SSI (Small Scale Integration) _ MSI (Medium Scale Integration) _ LSI (Large Scale Integration)

More information

EECS150 - Digital Design Lecture 2 - CMOS

EECS150 - Digital Design Lecture 2 - CMOS EECS150 - Digital Design Lecture 2 - CMOS August 29, 2002 John Wawrzynek Fall 2002 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor

More information

0 A. Review. Lecture #16. Pipeline big-delay CL for faster clock Finite State Machines extremely useful You!ll see them again in 150, 152 & 164

0 A. Review. Lecture #16. Pipeline big-delay CL for faster clock Finite State Machines extremely useful You!ll see them again in 150, 152 & 164 CS61C L15 Representations of Combinatorial Logic Circuits (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #16 Representations of Combinatorial Logic Circuits CPS today! 2005-10-26

More information

ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis

ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis Yasuhiko Sasaki Central Research Laboratory Hitachi, Ltd. Kokubunji, Tokyo, 185, Japan Kunihito Rikino Hitachi Device Engineering Kokubunji,

More information

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09 Study Number MA108-09 August 2009 Copyright Semico Research, 2009. All rights reserved. Reproduction in whole or part is prohibited without permission of Semico. The contents of this report represent

More information

Lecture #29. Moore s Law

Lecture #29. Moore s Law Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday

More information

Lecture 4&5 CMOS Circuits

Lecture 4&5 CMOS Circuits Lecture 4&5 CMOS Circuits Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese566/ Worst-Case V OL 2 3 Outline Combinational Logic (Delay Analysis) Sequential Circuits

More information

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy

More information

Micron MT9T Megapixel, ¼ Optical Format, 1.75 µm Pixel Size System-on-Chip (SOC) CMOS Image Sensor

Micron MT9T Megapixel, ¼ Optical Format, 1.75 µm Pixel Size System-on-Chip (SOC) CMOS Image Sensor Micron MT9T111 3.1 Megapixel, ¼ Optical Format, 1.75 µm Pixel Size System-on-Chip (SOC) CMOS Image Sensor Imager Process Review with Optional TEM Analysis of SRAM For comments, questions, or more information

More information

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University. EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL

More information

STM RH-ASIC capability

STM RH-ASIC capability STM RH-ASIC capability JAXA 24 th MicroElectronic Workshop 13 th 14 th October 2011 Prepared by STM Crolles and AeroSpace Unit Deep Sub Micron (DSM) is strategic for Europe Strategic importance of European

More information

Datorstödd Elektronikkonstruktion

Datorstödd Elektronikkonstruktion Datorstödd Elektronikkonstruktion [Computer Aided Design of Electronics] Zebo Peng, Petru Eles and Gert Jervan Embedded Systems Laboratory IDA, Linköping University http://www.ida.liu.se/~tdts80/~tdts80

More information

Interconnect. Physical Entities

Interconnect. Physical Entities Interconnect André DeHon Thursday, June 20, 2002 Physical Entities Idea: Computations take up space Bigger/smaller computations Size resources cost Size distance delay 1 Impact Consequence

More information

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

UNIT IV. Logic families can be classified broadly according to the technologies they are built with. The various technologies are listed below.

UNIT IV. Logic families can be classified broadly according to the technologies they are built with. The various technologies are listed below. UNIT IV Digital Logic Families Logic families can be classified broadly according to the technologies they are built with. The various technologies are listed below. DL : Diode Logic. RTL : Resistor Transistor

More information

Low Transistor Variability The Key to Energy Efficient ICs

Low Transistor Variability The Key to Energy Efficient ICs Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc.

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Jan Rabaey EECS 141 Spring 2010 LDPC Decoder Project Phase 3 Due Noon, Wednesday, May 5th, 2010

More information

nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect

nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect COURSE DELIVERY PLAN - THEORY Page! 1 of! 7 Department of Electronics and Communication Engineering B.E/B.Tech/M.E/M.Tech : EC Regulation: 2016(Autonomous) PG Specialization : Not Applicable Sub. Code

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

A Self-Contained Large-Scale FPAA Development Platform

A Self-Contained Large-Scale FPAA Development Platform A SelfContained LargeScale FPAA Development Platform Christopher M. Twigg, Paul E. Hasler, Faik Baskaya School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, Georgia 303320250

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

Microelectronics, BSc course

Microelectronics, BSc course Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT

More information

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1 Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar

More information