CMOS 65nm Process Monitor
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1 CMOS 65nm Process Monitor Advisors: Dr. Hugh Grinolds Mr. Brian Misek Allen Chen Ryan Hoppal Phillip Misek
2 What is Process Variation? The process parameters can vary from: Lot-to-Lot (interprocess variation) Wafer-to-wafer (interprocess variation) Die-to-die (intraprocess) Variations in process parameters include: Doping densities Oxide thickness Diffusion depths W and L of transistors These variations are strongly correlated so it s difficult to isolate individual parameters
3 I dsat PMOS Die-to-Die Variation SF FF Spec SS Typ. FS SkewTarget W1 Courtesy: Brian Misek I dsat NMOS
4 Variations on a Wafer Frequency Fast Failed Slow Mid
5 Design Flow Modeling Layout Extraction Final Design
6 Layout (Cadence) NAND
7 Our Process Monitor On-die 65nm process compatible Selector Block Inverter Delay Module Poly Resistance Module Future Expansion Output Register
8 Our Design Constraints Requirements: Size: < 100um x 100um per module Power-down mode Digital Output one 8-bit word Provided: MHz Precision clock 1V supply Access to off-chip memory
9 Inverter Delay Module Control Logic (On/Off) Ring Oscillator Approx stages Fast Counter Block Processing Block Output Digital Circuit
10 Main Test Structure: Ring Oscillator Simple (can be designed with INV, NAND, or NOR) Large number of stages in a RO provide statistical normalization frequency easily measured with counters Importance of propagation delay Minimize power consumption in digital circuits Provides a reference point for measuring other parameters On/Off RO Counter Processing Output
11 Ring Oscillator Operation f RO N( t PLH 1 t PHL ) RO has odd N stages Process variations affect delay time of each stage, reflecting frequency shifts in the freq. domain On/Off RO Counter Processing Output
12 Counter Fast Counter 3-input NAND-NAND logic Minimal stages Small size transistors On/Off RO Counter Processing Output
13 Polyresistance Module Use two different test structures Resistively loaded ring oscillator Second test structure still in research phase Non-linear oscillator PTAT driven structure
14 RO Test Structure - Resistance Control Logic (On/Off) Inverter Delay Module Resistively Loaded Ring Oscillator Fast Counter Block Processing Block Output Digital Circuit
15 Frequency (MHz) Resistively Loaded RO At 2KΩ, R = 7% f =.5% Frequency vs. Resistance (100 stage) Resistance (KΩ) On/Off RO Counter Processing Output
16 Frequency (MHz) f vs. R (Corner Simulation) TT FF SS Resistance (kilo-ohm) On/Off RO Counter Processing Output
17 Timeline Research Aug-08 Sep-08 Oct-08 Nov-08 Dec-08 Jan-09 Feb-09 Mar-09 Apr-09 May-09 Tools (Cadence and Mentor) Inverter Delay Module Polyresistance Module Digital Framework
18 Budget $160 $140 $120 $100 $80 $60 $40 $20 $0 August September October November December We have no expected expenditures for next semester
19 Thank You Mr. Brian Misek Avago Technologies Dr. Hugh Grinolds Charles Thangaraj
20 I dsat PMOS Wafer-to-Wafer Variation Selected Die from Skew Spec SkewTarget W1 W3 W4 W5 W6 W7 W8 W9 W10 Courtesy: Brian Misek I dsat NMOS
21 Process Geometry Rules Provided by Dr. Hugh Grinolds
22 Next Steps Finish 2 nd test structure for resistance module Finish control logic Layout Documentation Preliminary work on threshold voltage module
23 CMOS 65nm Process Monitor Advisors: Dr. Hugh Grinolds Mr. Brian Misek Allen Chen Ryan Hoppal Phillip Misek
24 What We ve Done This Semester Complete Counter (Layout, DRC/LVS, Extraction, Resimulation) Memory (Layout, DRC/LVS, Extraction, Resimulation) RO (Layout, DRC) RO w/ polyres (Layout) Adder/Subtractor (Layout) Near Completion RO (LVS, Extraction, Resimulation) Adder/subtractor (DRC/LVS)
25 Next Steps Finish Adder/subtractor, RO w/ polyres, and RO blocks Layout, DRC/LVS, Extract, Resimulate Combine all the blocks Complete simulation at all process corners Test overall performance and functionality Prepare for E-days Poster Presentation Paper Document the project
26 Counter
27 Memory Block
28 Ring Oscillator
29 RO w/ PolyRes
30 RO w/ PolyRes Shorted
31 Schematic Simulation of RO w/ Counter
32 Adder/Subtractor 1-bit Slice
33 End
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