Monolithic Pixel Detector in a 0.15µm SOI Technology

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1 Monolithic Pixel Detector in a 0.15µm SOI Technology 2006 IEEE Nuclear Science Symposium, San Diego, California, Nov. 1, 2006 Yasuo Arai (KEK) KEK Detector Technology Project : [SOIPIX Group] Y. Arai Y. Ikegami H. Ushiroda Y. Unno O. Tajima. Tsuboyama S. Terada M. Hazumi H. Ikeda A K. Hara B H. Ishino C T. Kawasaki D G. Varner E, E. Martin E, H. Tajima F, M. Ohno G, K. Fukuda G, H. Komatsubara G, J. Ida G, H.Hayashi G KEK JAXA A U. Tsukuba B TIT C Niigata U. D U. Hawaii E, SLAC F,OKI Elec. Ind. Co. G yasuo.arai@kek.jp (IEEE NSS) 1

Introduction Feature of SOI (Silicon-On-Insulator) Full Dielectric Isolation : Latchup Free, Small Area Low Junction Capacitance : High Speed, Low Power

2 Introduction Feature of SOI (Silicon-On-Insulator) Full Dielectric Isolation : Latchup Free, Small Area Low Junction Capacitance : High Speed, Low Power No Well junction, Thin Film : Low Leakage, Low Vth Shift (~300 ºC) Small Active Volume : High Soft Error Immunity yasuo.arai@kek.jp (IEEE NSS) 2

3 Feature of SOI Monolithic Pixel detector Bonded Wafer (High Resistive Substrate + Low Resistive Top Si). Standard CMOS Electronics (NMOS, PMOS, MIM Cap etc. can be used). Monolithic Detector, No Bump Bonds (Lower cost, Thin Device). High density (Smaller Pixel Size is possible). Small capacitance of the sense node (High gain V=Q/C) Industrial standard technology (Cost benefit and Scalability) Explore possibility of SOI detector for future experiments (ILC, SLHC, Super-Belle etc.) and other applications (Medical, Material etc.) yasuo.arai@kek.jp (IEEE NSS) 3

4 SOI Pixel Process Process SOI wafer Backside 0.15µm Fully-Depleted SOI CMOS process, 1 Poly, 5 Metal layers (OKI Electric Industry Co. Ltd.). Wafer Diameter: 150 mmφ, Top Si : Cz, ~18 Ω-cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz >1k Ω-cm (No type assignment by supplier), 650 µm thick (SOITEC) Thinned to 350 µm, and plated with Al (200 nm). p+/n+ Implant and Contact formation yasuo.arai@kek.jp (IEEE NSS) 4

5 Diode TEG Metal contact & p+ implant Al (IEEE NSS) 5

6 p-n junction I-V characteristics n+ - back p+ - back Good Diode Characteristic Substrate is n type. ~700 Ω-cm (~6 x cm -3) yasuo.arai@kek.jp (IEEE NSS) 6

7 Pixel TEG CMOS Active Pixel Sensor Type 20 µm x 20 µm 32 x 32 pixels yasuo.arai@kek.jp (IEEE NSS) 7

8 Pixel Layout Window for Light Illumination (5.4 x 5.4 um 2 ) 6"φ MPW wafer 20 µm (pixel) 2.5 mm (chip) 2.5 mm (chip) p+ junction Storage Capacitance (100 ff) yasuo.arai@kek.jp (IEEE NSS) 8

9 Pixel I-V characterisitic V break ~ 100 V Hot Spot observed with infrared camera I = 40 µa, T = 1 min Corner of the bias ring Smooth the corner at next submission. (only 45 o allowed by design rule in previous run. next +30 o and 60 o ) yasuo.arai@kek.jp (IEEE NSS) 9

10 Laser Image Plastic Mask 32x32 image view with 670nm Laser and plastic mask Vdet = 10 V Laser (670 nm) Exposure Time = 7 µs yasuo.arai@kek.jp (IEEE NSS) 10

11 Response to β-ray source 90 Sr Performance test as a particle detector Output of one channel is observed with oscilloscope. Pixel sensor 90 Sr source yasuo.arai@kek.jp (IEEE NSS) 11

12 The voltage jump corresponds to a particle hit. V sense = Q C " 0.6 fc 8 ff = 70mV V det = 10 V W depletion ~ 44 µm Q ~ 3500 e (0.6 fc) Expected signal amplitude was observed for β-ray yasuo.arai@kek.jp (IEEE NSS) 12

13 Back Gate Effect Threshold Variation Back Gate IO Buffer Substrate Voltage act as Back Gate, and change transistor threshold. Signal disappears at 16V Consistent with SPICE simulation (IEEE NSS) 13

14 Back Bias Simulation and p+ location ENEXSS : 3D TCAD Simulator Back Gate effect can be reduced by placing p+ implant near transistors. D = (80, 5, 2 µm) NMOS BOX (200 nm) (5 µm wide p+, 1 x cm -3 ) Bulk: n- (~6 x cm -3 ) 350µm Backbias (0-100 V) Diode Electric Field yasuo.arai@kek.jp (IEEE NSS) 14

15 Summary We have started generic R&D on SOI detector. (Sensor in high-r Si and CMOS circuit in low-r Si). A first SOI Pixel Detector (32 x 32 pixels with 20µm x 20µm size) was successfully fabricated and tested. The detector is fabricated in a commercial 0.15 µm SOI CMOS process with 3 additional masks. Good images KEK06 with red laser light are taken. Signals of β-ray from 90 Sr are observed. Break down voltage of present sensor is about 100V and hot spot is identified. Back gate effect was obserbed. It is consistent with SPICE simulation, and studied with ENEXSS simulator. Next submission is scheduled in beginning of December yasuo.arai@kek.jp (IEEE NSS) 15

First Results of 0.15μm CMOS SOI Pixel Detector

First Results of 0.15μm CMOS SOI Pixel Detector International Symposium on Detector Development SLAC, CA, April 5, 2006 KEK Detector Technology Project : [SOIPIX Group] Yasuo Arai (KEK) Y. Arai Y. Ikegami