FinFET vs. FD-SOI Key Advantages & Disadvantages

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1 FinFET vs. FD-SOI Key Advantages & Disadvantages Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr

2 Moore s Law The number of transistors on integrated circuits doubles every two years In 1965, Gordon Moore sketched out his prediction of the pace of silicon technology. Decades later, Moore s Law remains true, driven largely by Intel s unparalleled silicon expertise. (Source: Intel; Copyright 2005 Intel Corporation) How to maintain cost-performance? 2

3 Complying with Moore s Law Maintaining Cost-Performance Traditional: Shrink the feature size: ArF Immersion Double/Quad patterning EUV Increase wafer size: 200mm 300mm 450mm Unique/New Build vertically: 2D 3D 3

4 Cost Trends Source: Faster, Cooler, Simpler, could FD-SOI be Cheaper too? Semiwiki, 08/2013 Design cost exponentially increases coupled with reverse in cost per gate trend from 20nm 4 4

5 End Market Growth Outlook Units (B) Tablet Premium Tablet Utility/Basic Smartphone Premium Smartphone Utility/Basic PC Marginal Unit Growth Smart phones are the market fuel for both Logic AP & Memory 5

The leakage/power consumption problem Source: http://allthingsvlsi.wordpress.

6 The leakage/power consumption problem Source: Source: Challenges of 10nm and 7nm CMOS Technologies, IEDM 2013 Physical dimension scaling of ~10 3, Transistor # increased x10 6 in 30 years Cost is leakage, resulting in power consumption Limitations of bulk planar transistors Channel area underneath the gate is too deep and too much of the channel is too far away from the gate to be well-controlled The result is higher leakage power (static/stand-by power) Gate is never truly turned off Solution: Make the channel thinner so that it is well controlled by the gate 6

7 Possible Solutions FinFET FD-SOI Fin (shaped) Field Effect Transistor Fully Depleted Silicon on Insulator 7

8 What is a FinFET? Source: Intel Transistor with 2-3 gates which are wrapped around a Silicon fin Trigate has 3 gates [2 sidewall vertical gates and one planar/top gate] A version of a Trigate finfet is Double-Gate FinFET with only the 2 sidewall vertical gates with top gate being non-functional due to thicker gate oxide 8

Layer - Silicon 50-90 nm Si thickness Partially Depleted

advantages: Excellent electrostatic control of the

BOX is also thin Excellent VT variability Low DIBL

Limited Short Channel Effects Very good Sub-threshold

9 What is FD-SOI? SOI Silicon on Insulator stack of Silicon-Buried Oxide Layer - Silicon nm Si thickness Partially Depleted SOI 5-20 nm Si thickness Fully Depleted SOI FD-SOI advantages: Excellent electrostatic control of the channel No channel doping required Back bias ability if BOX is also thin Excellent VT variability Low DIBL (Drain Induced Barrier Lowering) especially at low VDD Limited Short Channel Effects Very good Sub-threshold Slope Minimum junction capacitance and diode leakage Simpler process: no halo doping, simpler STI (End Pointed Etch) 9

10 FD SOI vs. Bulk Planar Performance Comparison The power/performance characteristics of FD SOI with body biasing, and also without body biasing, are better than bulk CMOS at 20nm 10

11 FD SOI vs. Bulk HKMG Cost Comparison Source: ECONOMIC IMPACT OF THE TECHNOLOGY CHOICES AT 28nm/20nm, IBS Inc, Jun 2012 Despite SOI base wafer cost ~4X higher than bulk, market analysis estimations lead to lower die costs due to projected higher die yields 11

12 FD-SOI Vs FinFET Performance Comparison Source: Comparison study of FinFETs: SOI vs. Bulk/SOI Consortium Source: IEDM 2013 short 7/10 nm CMOS course At matched Wfin/Hfin, equivalent performance Better DIBL & SS for FinFET 12 12

TECHNOLOGY CHOICES AT 28nm/20nm, IBS Inc, Jun 2012 Source: FD=SOI Keeps Moor s Law on Track,

13 FD-SOI vs. FinFET - Cost vs. Performance Comparison 20nm Die Costs at 100mm 2 and 200mm 2 Source: ECONOMIC IMPACT OF THE TECHNOLOGY CHOICES AT 28nm/20nm, IBS Inc, Jun 2012 Source: FD=SOI Keeps Moor s Law on Track, Advanced Substrates, Feb 2014 Bulk FD SOI projected to have lower unit cost than FinFET due to higher FinFET process complexity and expected lower die yield 13

IEDM 2013 short 7/10 nm CMOS course Tsi & BOX thickness & uniformity,

14 Unique FD SOI Process Challenges [Wafer Vendor] Thin Si thickness & x-wafer uniformity Buried oxide thickness & x-wafer uniformity Source: IEDM 2013 short 7/10 nm CMOS course Tsi & BOX thickness & uniformity, critical parameters to performance, controlled by base wafer manufacturer 14 14

15 Unique FinFET Process Challenges [Fab] Spacer Complete spacer removal from fin area Gate Stack (high-k & metal gate) Material selectivity Material deposition thickness uniformity on vertical walls Metal gate composition uniformity/stability Fin Formation: Precision etch Structural integrity (collapse, erosion, thermal shock) Precise Recess to control fin height Channel materials to increase mobility Fin STI Oxide Fin Junctions: Conformal doping on sidewalls 15

16 FinFET Process Control Challenges [Fab] Lg Lg Lg Measurement of gate CD across the Fin height Detection & Review of defects on Fin sidewalls after gate etch Measurement of Fin sidewall angle to control the 3D transistor width 16

Bulk, SOI Industry Consortium Natural Isolation between adjacent transistors by

17 Process Differences - Example STI Module FinFET FD-SOI Vs FinFET Bulk Source: Comparison study of FinFETs: SOI vs. Bulk, SOI Industry Consortium Natural Isolation between adjacent transistors by BOX, STI etch end points on BOX, minimal need for trench depth control, with no requirement for implant to complete isolation 17

18 Process Possible Solutions Plasma doping (PLAD) for uniform sidewall doping Metrology & Inspection Tilt CD-SEM measurements Destructive technologies 18

19 Tilt CD-SEM Methodology & Case Study Applied Materials collaboration with GLOBALFOUNDRIES, proves excellent correlation between tilted CD-SEM height measurement and TEM 19

20 FinFET vs. FD-SOI Category FinFet FD-SOI Base Wafer Cost x4 Process Complexity Overall Wafer Cost to To Die Yields???????????? Unit Cost???????????? Process control & metrology challenges Active transistor area density Performance (Ion vs. Ioff) Similar Similar 20

21 What Next? Future Transistor Path 21

Width ~ 3 12 nm, Lengths: 280 nm Published in SPIE 2014: Applied

22 Gate All Around - Si Nanowires Source Buckling Drain SiNW buckling, may impact device performance SiNW sample dimensions: Width ~ 3 12 nm, Lengths: 280 nm Published in SPIE 2014: Applied Materials/IBM Collaboration to characterize the buckling effect of nano-wires 22

23 Summary FinFET first generation is in high volume production Key manufacturers are following the FinFET path for 14nm FinFET is a major inflection in terms of process and metrology challenges vs. FD- SOI which is a simpler path The long term winner between both approaches will depend on the device/process scalability, as the cost benefit of FD-SOI vs. FinFET is based on combination of: base wafer cost, process complexity/cost and die yield 23

24 Thank You 24

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