Sub-micron technology IC fabrication process trends SOI technology. Development of CMOS technology. Technology problems due to scaling

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1 Goodbye Microelectronics Welcome Nanoelectronics Sub-micron technology IC fabrication process trends SOI technology SiGe Tranzistor in 50nm process Virus The thickness of gate oxide= 1.2 nm!!! Today we move to 22 nm process - Gate oxide 0.8 nm Development of CMOS technology When will that ends??? The thickness of gate oxide = 1.2 nm Strained Silicon Why do we need smaller transistors? Scalilng of IC technology (180, 130, 90, 65, 45, 32 nm) Speed Less power dissipation and consumption on the functional block The density of transistors Less functional block cost Hlavní problémy Ultra-thin gate oxide - parasitic leakage current Very shallow S / D diffusion regions Interconnection: the problem of shrinking - grows RC Etc. A potential solution is a high dielectric material for gate insulation, metal gate, a new CMOS structure, etc.. Technology problems due to scaling V dd decreases with the new technological generation Maintain a dynamic power dissipation (C.V dd 2.f) V t remains relatively constant Keep low I off ==> keep the dynamic power dissipation at a reasonable level MOSFET (V dd -V t ), considerably reduced ==> hard to ensure the desired I on

2 Feature Size ( m) Technology problems due to scaling Solution: alternative technologies Potential solution: SOI Increase effective (V dd -V t ) Multi-V t, dynamic V t increase the acceptable I off reduce V t Reduce V dd more slowly Various power and speed for the individual blocks Use of new materials Long-term: new MOSFET structure SOI Dual gate SOI Vertical FETs SiGe, Strained Silicon, Etc. Speed never sufficient Scaling of transistors Clock frequencies grows exponentially Moore low 1 Billion K Transistors 1,000, ,000 10,000 1, i486 Pentium i Nahalem Pentium IV Pentium III Pentium II Pentium Pro Zdroj: Intel Year Scaling of transistors Transistor dimensions are reduced by 30% each 2-3 years Transistors are cheaper They are also faster Metallic connection speed, however, does not improve 10 Scale factor S Typical steps: S Scaling preconditions What changes moving to the new technology node? starting point: Preserving a constant electric field We customize all dimensions (x, y, z => W, L tox) Supply voltage (VDD) The values of diffusion fields of subsidies Metallization must be adapt Some materials do not comply with their properties Year

3 Transistor scaling with S factor Transistor scaling with S factor Parameter Reduction Channel length L 1/S Channel width W 1/S Thickness of gate oxide t ox 1/S Supply voltage V DD 1/S Transistor properties Parameter Reduction factor Note Current factor b S Current I DS 1/S b(v DD -V t ) 2 Resistance 1 V DD /I DS Threshold voltage Vt 1/S Wafer doping N A S Downsize 1/5 Gate capacitance 1/S W.L/C ox Delay 1/S RC Clocking frequency S 1/t dynamic losses 1/S 2 C.V 2 / f Chip area 1/S 2 Transistor scaling conclusion Transistors are faster (+) Dynamic consumption decreases (+) Current density is growing (-) Growing resistance of contacts (-) Metallization scaling Thickness of copper jumpers It remains constant distance connections Local / reduced by a factor of S Global - unchanged Sub-micron IC structure in real scale : Sub-micron IC structure in real scale : Copper Conductors (8 Levels) Passivation SiO 2 (500nm) + Si 3N 4 (200 nm) Metal #6 Metal #5 Low-k Dielectric Metal #4 Metal #3 Copper Plugs Metal #2 Metal #1 TRANZISTORS Trench izolation PolySi Gate

4 Interconnection resistivity Reciprocal capacity Reliability Decreasing Have an impact on performance Classification of parasitic effects Capacity Resistivity Inductance Ro = square resistance creates crosstalk Parametr Metallization scaling with S factor Reduction factor Metallization width W 1/S The distance 1/S Metallization thickness t 1/S Insulator thickness 1/S Metallization scaling Consequence of downsizing Delays reached a minimum at 180 to 90 nm, further the delay will only worsen But... Parametr Reduction factor The resistance per unit length S 2 1/W.t Capacity in the same layer 1 t/s Capacity between the layers 1 W/h Note Redukce 1/5 The total capacity 1 W.L/C ox RC constant per unit length S 2 [SIA97] ITRS Future? Development of MOSFET structures below 70 nm Intl. Technology Roadmap for Semiconductors Bulk MOSFET SOI/ MOSFET Dual-Gate MOSFET Vertical MOSFET

5 SOI Technology SOI - Silicon On Insulator SOI Technology Silicon On Insulator Jiří Jakovenko Struktury integrovaných systémů - Katedra mikroelektroniky ČVUT FEL SOI Benefits Latch-up effect Improved performance through elimination of parasitic capacities PN junctions and "Body Effect" % higher performance than Si CMOS SOI can operate at lower voltages with the same performance as Si CMOS % Better use of chip area - smaller surface insulation Reduced Body Effect Prevention of leakage currents into the substrate Increased integration density Preventing of latch-up effect Increased operating temperature (250 C) Resistance to radiation SOI disdadvantages SOI Types Very few disadvantages: Thermal properties More expensive substrates of 3 to 10% over CMOS Hysteresis of threshold voltage Partially-Depleted - Fully-Depleted

6 Floating - body effect Parasitic bipolar transistor Change of threshold voltage Application of SOI Suitable for circuits with low and very low power consumption Microprocessors with higher clock speeds Graphics processors Circuits for high-speed serial communication: 100 Gbps Ultra-low power systems on a chip: watch for solar energy RFID All technologies below 90 nm on SOI SOI wafer production technology SOS - silicon on sapphire (1978) SIMOX - separation by implantation of oxygen (1983) ZMR - zone melting and recrystallisation (1983) BESOI - bond and etch back SOI (1989) Smart-Cut SOI (1996) SIMOX wafer technology 1. implantation of oxygen ions implantation energy determines the depth and thickness of the burried oxide layer and the thickness of top Si layer 2. annealing - a gradual increase in temperature from 1050 to 1350 C formation of the oxide layer avoidance of dislocations in the top layer of silicon Smart Cut Technology SOI vs conventional CMOS comparison 30% faster 30% greater integration density 20% fewer manufacturing steps 50% power consumption

7 Strained silicon technology Strain It uses a different lattice constant of Si and Ge Strained Silicon Technology Jiří Jakovenko Struktury integrovaných systémů - Katedra mikroelektroniky ČVUT FEL Implementing to CMOS structure Tranzistor photo Advantages of strained silicon Only about 2% higher costs Higher speed - up to 35% Increase of the mobility of carriers by 50% Simplicity No need to shrink the thickness of oxide Possible combination with other technologies for the future SSOI Strained SOI Combination of SOI and strained silicon technology mpi-halle.de 25 nm FDSOI tranzistor, CEA-Léti,

8 Technology of High-k dielectrics, in combination with metal gates Development of HKMG took more than ten years Today it is used in 45 nm and 32 nm technologies node Transistors performance is up to 22% higher The leakage currents of 5-10 times lower SiGe HBT Technology SiGe Technology has been known for a long time, but no one could combine SiGe layer with a layer of Si without defects in the crystalline structure In the 90 years the development occurs in bipolar transistors caused by SiGe HBT technology 45 nm tranzistor HKMG, : Intel Intel The pros and cons of SiGe HBT 3D Tri-Gate CMOS Transistors - MuGFET Better performance than Si BiCMOS Lower price than the III-V Semiconductors (GaAs) Use for RF circuits Speed GHz Costs only about 2-3% higher Increased speed by 18-37% Year of Implementation:2012 Planar tranzistor 22 nm tri-gate transistor Full depletion region + Higher f T ~ 550GHz + Higher performance (efficiency) + Lower power consumption - Higher production costs - More challenging manufacturing Intel 3D Ics Full SOC SOC System On Chip 3D chip Technology Jiří Jakovenko Struktury integrovaných systémů - Katedra mikroelektroniky ČVUT FEL

9 3-D ICs : Several active Si layers New design architecture necessary Advantages: Reducing the length of interconnection Better chip performance Smaller chip area Heterogeneous integration: digital, analog, optical Replacement of horizontal connections in the vertical The problem with cooling 3-D Technology Today surface SOC GaAs Technology Increased electron mobility

10 carriers mobility for common semiconductors Material properties of GaAs Max. electron velocity = 2 x Silicon = 2 x 10 7 cm/sec Hole mobility of GaAs (= 400) < Si (489 cm 2 V/sec) No complementary logic possible!!! Electron mobility of GaAs ( ) >> Si ( ) Max. El. field (max. speed) GaAs (0.3 V/ m) < Si (1 V/ m) Low voltage supply Fragile Materials 3 to 4 inch wafers The high density of defects High Q SS and Q ox No MOS structure possible! The best component: MESFET I-V Characteristic Large changes in threshold voltage on one wafer ( mv) High Electron Mobility Transistor (HEMT) MEMS technologies Pohyblivost v nedopovaném GaAs > 8500 cm 2 /Vsec (4500 cm 2 Vsec v dopov. GaAs) Až do 50,000 cm 2 /Vsec v kapalném dusíku

11 f max, f T, GHz f max Pohyblivost Velocity, 10 7 cm/s Cutoff frequency, GHz Electrostatic micromirrors Radiofrequency electronics Commercial electronics Mikroprocesor, memory, sensors systems Transistors types MOSFET (98 % of applications) Bipolar: BJT RF electronics Transistors types Bipolar: - BJT - HBT (Heterojunction Bipolar Transistor) FET - MESFET (Metal Semiconductor FET) - HEMT (High Electron Mobility Transistor) - MOSFET (Metal Oxide Semiconductor FET) Semiconductor materials Si Semiconductor materials III-V's (GaAs, InP AlGaAs, InGaAs, InAlAs, ) Si SiGe Wideband semiconductors (SiC, GaN, AlGaN) Evolution of microwave technologies Trends in RF technology: Transistor Cutoff frequency Increasing f T a f max (III-V) Growth of output power (semiconductors with wide band gap) Low cost silicon technology (CMOS and SiGe technology) GaAs phemt AlGaAs/GaAs HEMT GaAs MESFET InP HEMT AlGaAs/GaAs HEMT * InP HBT InP HEMT InP HBT 3 2 GaAs In 0.53 Ga 0.47 As InP Si Growth of frequency limit of MOS transistors Rapid increase of CMOS technologies for applications of microwave circuits Thanks to new CMOS technology, transistors reached almost the same speed as a special RF technology Upper limit nmosfet Exp. data nmosfet Exp. data pmosfet 10 Ge BJT Si BJT 1 1 f T * Transferred substrate Year Rok Elektrické Electric pole field, kv/cm Gate length, µm CMOS 32 nm f T / f MAx GHz/440 GHz