CMOS Technology. 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates. Handouts: Lecture Slides. metal ndiff.

Transcription

1 CMOS Technology 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates poly pdiff metal ndiff Handouts: Lecture Slides L03 - CMOS Technology 1

2 Building Bits from Atoms V in V out We Need Three Things: 1. Represent and communicate bits 2. Transform bits (Invert, AND, OR, ) 3. Remember bits (storage) V out V OH Non-linear gain V OL V IL V IH V in subject to the fundamentals of physics: Uncertainty, Noise, c, Thermodynamics, L03 - CMOS Technology 2

3 Wish List Small, simple, repeatable and stable non-linear devices with gain using readily-available materials Can mass produce very large quantities of devices and wires Consistently improves performance and density (scales) with ongoing R&D investment L03 - CMOS Technology 3

4 Wishes Fulfilled Small, simple, repeatable and stable non-linear devices with gain using readily-available materials Silicon + Aluminum/Copper + Can mass produce very large quantities of devices and wires Literally print billions at a time Consistently improves performance and density (scales) with ongoing R&D investment Moore s Law: 2x density every 1.5 to 2 years $1T in cumulative investment L03 - CMOS Technology 4

5 MOSFETS: Gain & non-linearity source gate Polysilicon wire Heavily doped (n-type or p-type) diffusions W Inter-layer SiO 2 insulation Very thin (<20Å) high-quality SiO 2 insulating layer isolates gate from channel region. L drain Channel region: electric field from charges on gate locally inverts type of substrate to create a conducting channel between source and drain. bulk Doped (p-type or n-type) silicon substrate MOSFETs (metal-oxide-semiconductor field-effect transistors) are four-terminal voltage-controlled switches. Current flows between the diffusion terminals if the voltage on the gate terminal is large enough to create a conducting channel, otherwise the mosfet is off and the diffusion terminals are not connected. Why are MOS devices King? L03 - CMOS Technology 5

6 FETs as switches The four terminals of a Field Effect Transistor (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal. gate inversion happens here n source E h drain n p E v bulk INVERSION: A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. CONDUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. L03 - CMOS Technology 6

7 Linear operating region V S V GS > V TH 0 < V DS < V Dsat I DS L Why is this bigger here than on other side? Larger V GS creates deeper channel which increases I DS I DS I DS proportional to µ 0 (W/L) Increasing V GS Larger V DS increases drift current but also reduces vertical field component which in turn makes channel less deep. At some point, electrons are traveling as fast as possible through the channel ( velocity saturation ) and the current stops growing linearly. V DS L03 - CMOS Technology 7

8 Saturated operating region V S V GS > V TH V Dsat < V DS I DS L = L - δl δl V Dsat V GS -V TH This looks just like a fet with a channel length of L < L. Shorter L implies greater I DS. As V DS increases, δl gets larger. V I DS = V GS -V TH DS When V DS = V GS -V TH the vertical field component is reduced and the channel is pinched-off. Electrons just keep traveling across depletion region Increasing VGS V DS L03 - CMOS Technology 8

9 NFET Summary D D + S n G p D n G G + V DS 0 Operating regions: S V GS - S - cut-off: V GS < V TH linear: V GS V TH V DS < V Dsat 0.8V S S D D I DS linear saturation V GS V GS -V TH saturation: V GS V TH V DS V Dsat S D V DS L03 - CMOS Technology 9

10 FETs come in two flavors By embedding p-type source and drain in a n-type substrate, we can fabricate a complement to the N-FET: G S D B S D n p n p n p D S G G S D The use of both NFETs and PFETs complimentary transistor types is a key to CMOS (complementary MOS) logic families. L03 - CMOS Technology 10

11 PFET Summary D D - B S p G n D p G G + V DS 0 Operating regions: S V GS - S + cut-off: V GS > V TH 0.8V S D -V DS linear: V GS V TH V DS > V Dsat S D -V GS saturation: V GS V TH V DS V Dsat V GS -V TH S D saturation linear -I DS L03 - CMOS Technology 11

12 CMOS Inverter = 0v I PU = 1v V in G S = power supply I PU D V out D = 2v = 3v = 4v I PU vs V OUT for PULLUP V OUT G I PD S = 0V I PD = 5v = 4v = 3v = 2v = 1v I PD vs V OUT for PULLDOWN V OUT L03 - CMOS Technology 12

13 CMOS Inverter VTC I pd V in = 0.5V I pu I pd Steady state reached when V out reaches value where I pu = I pd. I pu Vout V out V OH V in = 3.5V I pd V in = 1.5V I pu I pd V out I pu V out V in = 4.5V V OL I pu V in = 2.5V V IL V IH V in I pd V out I pd I pu V out When both fets are saturated, small changes in V in produce large changes in V out L03 - CMOS Technology 13

14 Think Switches V DD pullup: make this connection when near 0 so that V OUT = V DD V OUT pulldown: make this connection when near V DD so that V OUT = 0 L H H L V IL V OUT V IH V IH V OUT V IL L03 - CMOS Technology 14

15 Let s build a MOSFET Start with a 500µ slice of a silicon ingot that has been doped with an acceptor (typically boron) to increase the concentration of holes to /cm /cm 3. At room temperature, all the dopants in this p-type material are ionized, turning the silicon into a semiconductor. We ll build many copies of the same circuit onto a single wafer. Only a certain percentage of the chips will work; those that work will run at different speeds. The yield decreases as the size of the chips increases and the feature size decreases. Wafers are processed by automated fabrication lines. To minimize the chance of contaminants ruining a process step, great care is taken to maintain a meticulously clean environment. So put on your bunny suits and let s begin L03 - CMOS Technology 15

16 Creating patterns on the wafer A thick (0.4u) layer of SiO 2 is formed by oxidizing the surface of the wafer with wet oxygen (we rust it!). The SiO 2 will serve as insulation between the conductive substrate and subsequent conductive layers we ll build on top of the oxide. Now we ll form a pattern in the SiO 2 using a mask & etch process. First the wafer is coated with a layer of photoresist. Photoresist becomes soluble when exposed to ultraviolet light Using a mask to protect parts of the wafer, we ll expose those portions of the wafer where we want to remove the photoresist. We ll use different masks when creating each of the different structures on the wafer. L03 - CMOS Technology 16

17 The etching process The exposed photoresist is removed with a solvent. The unexposed photoresist remains, masking portions of the underlying SiO 2 layer. A chemical etch is then used to remove the revealed silicon dioxide. Finally, the remaining photoresist is removed with a different solvent and we re left with pattern of insulating SiO 2 on top of exposed p-type substrate. L03 - CMOS Technology 17

18 Gate oxide & polysilicon Now a thin (20 Å) layer of SiO 2, called gate oxide, is grown on the surface. The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the oxide, the more oomph the FET will have (we ll see why soon) but the harder it is to make it defect-free. Coming soon to a fab near you: 12 Å gate oxide... On top of the thin oxide a 0.7u thick layer of polycrystalline silicon, called polysilicon or poly for short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and drain junctions will be formed. Poly has a high sheet resistance of 20 Ω/sq which can be reduced by adding a layer of a silicided refractory metal such titanium (TiSi 2 ), tantalum (TaSi 2 ) or molybdenum (MoSi 2 ) => 1, 3 or 5 Ω/sq. L03 - CMOS Technology 18

19 Source/drain diffusions Donor implants are used to create self-aligned MOSFET source/drain diffusions and substrate contacts. Usually As is preferred to obtain shallow N-type diffusions and minimal lateral diffusion. High doses are needed to make low resistance (25 Ω/sq) diffusion wires. Afterwards a short thermal annealing step is performed to repair surface damage caused by the implantation. This completes the construction of the MOSFET itself. Now we ll add the metal wiring layers L03 - CMOS Technology 19

20 Wires: metal interconnect Deposit SiO 2 insulation Etch openings for vias/contacts Deposit Al/Cu conductor Etch away Al/Cu leaving wires After a layer of SiO 2 insulation has been deposited, aluminum or copper is deposited, patterned, then etched to form low-resistance (.07 Ω/sq) interconnect. With planarization of the SiO 2 (a mechanical polishing step that creates a flat surface), multiple levels of metal interconnect are possible -- 3 to 6 layers are common in today s processes. L03 - CMOS Technology 20

21 Standard Cell Layout for Inverter SW: scaled width used in Process-independent design m1/nwell contact m1 power bus m1/pdiff contact pfet Use two narrow mosfets in parallel instead of one wide mosfet m2/m1 via m1/poly contact poly wire m1 wire nfet m1/ndiff contact m1 ground bus m1/substrate contact Physical design of a CMOS gate is represented by a mask layout showing where material on each layer (ndiff, pdiff, poly, m1, m2, ) should be placed on the silicon wafer. Each manufacturing process has a set of design rules that determine minimum widths, spacings, overlaps, etc. L03 - CMOS Technology 21

22 Beyond Inverters: Complementary pullups and pulldowns Now you know what the C in CMOS stands for! We want complementary pullup and pulldown logic, i.e., the pulldown should be on when the pullup is off and vice versa. pullup pulldown F(A 1,,An) on off driven 1 off on driven 0 on on driven X off off no connection Since there s plenty of capacitance on the output node, when the output becomes disconnected it remembers its previous voltage -- at least for a while. The memory is the load capacitor s charge. Leakage currents will cause eventual decay of the charge (that s why DRAMs need to be refreshed!). L03 - CMOS Technology 22

23 What a nice V OH you have... CMOS complements Thanks. It runs in the family... conducts when V GS is high conducts when V GS is low A B A B conducts when A is high and B is high: A. B conducts when A is low or B is low: A+B = A. B A B A B conducts when A is high or B is high: A+B conducts when A is low and B is low: A. B = A+B L03 - CMOS Technology 23

24 A pop quiz! What function does this gate compute? A B A B C NAND 1 0 L03 - CMOS Technology 24

25 Here s another B A What function does this gate compute? A B C NOR 0 0 L03 - CMOS Technology 25

26 General CMOS gate recipe Step 1. Figure out pulldown network that does what you want, e.g., F = A*(B+C) (What combination of inputs generates a low output) B A C Step 2. Walk the hierarchy replacing nfets with pfets, series subnets with parallel subnets, and parallel subnets with series subnets Step 3. Combine pfet pullup network from Step 2 with nfet pulldown network from Step 1 to form fullycomplementary CMOS gate. A A B A B C B C C But isn t it hard to wire it all up? L03 - CMOS Technology 26

27 Emerging Big Issue: Power moves from L to H to L V DD V OUT moves from H to L to H C V OUT Energy dissipated = C V DD 2 per gate Power consumed = f n C V DD 2 per chip C discharges and then recharges where f = frequency of charge/discharge n = number of gates /chip L03 - CMOS Technology 27

28 Unfortunately Modern chip (UltraSparc III, Power4, Itanium 2) dissipates from 80W to 150W with a Vdd 1.2V (Power supply current chip is 100 Amps) Ampacity is similar to a big double oven! Cooling challenge is like making the filament of a 100W incandescent lamp cool to the touch! Worse yet Little room left to reduce Vdd nc and f continue to grow L03 - CMOS Technology 28

29 Emerging Big Issue: Wires V out R C Today (i.e., 100nm): τ RC 50ps/mm Implies 2ns to traverse a 20mm x 20mm chip This is a long time in a 2GHz processor L03 - CMOS Technology 29

30 MOSFET features Summary PN junctions provide electrical isolation Switch-like behavior controlled by V GS Shrinking geometries improves performance CMOS features CMOS logic is naturally inverting: 1 inputs lead to 0 outputs Good noise margins because V OL = 0, V OH = V DD complementary logic has high gain No static power dissipation Next time: timing, converting functionality to logic L03 - CMOS Technology 30