PAPER SOLUTION_DECEMBER_2014_VLSI_DESIGN_ETRX_SEM_VII Prepared by Girish Gidaye

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1 Q1a) The MOS System under External Bias Depending on the polarity and the magnitude of V G, three different operating regions can be observed for the MOS system: 1) Accumulation 2) Depletion 3) Inversion Accumulation: If a negative voltage VG is applied to the gate electrode, the holes in the p-type substrate are attracted to the semiconductor-oxide interface. The majority carrier concentration near the surface becomes larger than the equilibrium hole concentration in the substrate; hence, this condition is called carrier accumulation on the surface Figure : The cross-sectional view and the energy band diagram of the MOS structure operating in accumulation region. Depletion: In this mode a small positive gate bias VG is applied to the gate electrode. Since the substrate bias is zero, the oxide electric field will be directed towards the substrate in this case. The positive surface potential causes the energy bands to bend downward near the surface, as shown in Fig The majority carriers, i.e., the holes in the substrate, will be repelled back into the substrate as a result of the positive gate bias, and these holes will leave negatively charged fixed acceptor ions behind. Thus, a depletion region is created near the surface. Figure : The cross-sectional view and the energy band diagram of the MOS structure operating in depletion mode, under small gate bias.

2 Inversion: In this mode a large positive voltage is applied at gate with respect to bulk. As a result of the increasing surface potential, the downward bending of the energy bands will increase as well. Eventually, the mid-gap energy level Ei becomes smaller than the Fermi level E FP on the surface, which means that the substrate semiconductor in this region becomes n-type. Within this thin layer, the electron density is larger than the majority hole density, since the positive gate potential attracts additional minority carriers (electrons) from the bulk substrate to the surface. The n-type region created near the surface by the positive gate bias is called the inversion layer, and this condition is called surface inversion. It will be seen that the thin inversion layer on the surface with a large mobile electron concentration can be utilized for conducting current between two terminals of the MOS transistor. Figure : The cross-sectional view and the energy band diagram of the MOS structure in surface inversion, under larger gate bias voltage. Q1 b) Sr. Burried Contact Butting Contact No. 1 More reliable than the butting contact Suffers from reliability problems 2 This is complex since metal cap needed This is simple to make 3 Metal can cross over a buried contact, which can ease routing requirements considerably 4 The major disadvantages are that selfregistration may be lost, and that an extra mask level is required It can easily short circuit the contacts to the substrate It is smaller than two separate contacts 5 Extra masking step required It involves no extra masking steps 6 No metal cap is needed Requires a metal cap

3 Q1c) Q1d)

4 Q2a) The threshold voltage is a function of following parameters:-- 1) Gate conductor material. 2) Gate Insulator material. 3) Gate Insulator thickness 4) Channel doping. 5) Impurities at the silicon insulator interface. 6) Voltage between the source and substrate (bulk). So if we try to change the above parameters, it possible to change to the value of threshold voltage. We will consider the components of the V TH :-- 1) ø GC (Work function difference) :-- If you change the gate conductor material,the value of øf(gate) will change and that leads to change in value of work function potential difference(ø GC ),thus we can we can adjust the threshold voltage. 2)ø F (substrate) :-- We can change this value by changing doping density(n D or N A ) and hence we can adjust the value of V TH. 3)Cox:--The value of oxide capacitance per unit area can be changed by (i) changing the thickness of oxide layer(tox). (ii)changing the gate insulator material(i.e εox). For gate insulation we have choice of SiO 2, Al 2 O 3 and Si 3 N 4. Many times the combination of SiO 2 and Si 3 N 4 is used so that the dielectric constant increased and the value of Cox get increased and that leads to change in value of Vth. Thus if we change the value of oxide capacitance the value of V TH can adjusted. In most MOS fabrication processes, the threshold voltage can be adjusted by selective dopant ion implantation into the channel region of the MOSFET. For n-channel MOSFETs, the threshold voltage is increased (made more positive) by adding extra p-type impurities (acceptor ions). Alternatively, the threshold voltage of the n-channel MOSFET can be decreased (made more negative) by implanting n-type impurities (dopant ions) into the channel region. Q2b)

5

6 Q3a)

7 Q3b) The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology requires that the packing density of MOSFETs used in the circuits is as high as possible and, consequently, that the sizes of the transistors are as small as possible. The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as scaling. It is expected that the operational characteristics of the MOS transistor will change with the reduction of its dimensions. Scaling of MOS transistors is concerned with systematic reduction of overall dimensions of the devices as allowed by the available technology, while preserving the geometric ratios found in the larger devices. The proportional scaling of all devices in a circuit would certainly result in a reduction of the total silicon area occupied by the circuit, thereby increasing the overall functional density of the chip. To describe device scaling, we introduce a constant scaling factor S > 1.

8 PARAMETERS BEFORE SCALING FULL SCALING Channel length L L = L / s Channel width W W = W / s Gate oxide thickness T OX T OX = T OX / s Junction depth X J X J = X J / s Power supply voltage Threshold voltage AFTER SCALING CONSTANT VOLTAGE SCALING L = L / s W = W / s T OX = T OX / s X J = X J / s V DD V DD = V DD / s V DD = V DD V TO V TO = V TO / s V TO = V TO Doping densities N A, N D N A, N D = s.n A, s.n D N A, N D = s 2.N A, s 2.N D Oxide capacitance C OX C OX = C OX / s C OX = C OX / s Drain current I D I D = I D / s I D = s.i D Power dissipation P D P D = P D / s 2 P D = s.p D Power density P D / Area P D / Area = P D / Area P D / Area = s 3. P D / Area Q4a)

9 Q4b) CMOS inverter consists of an enhancement-type nmos transistor and an enhancement-type pmos transistor, operating in complementary mode (Fig.a). This configuration is called Complementary MOS (CMOS). The circuit topology is complementary push-pull in the sense that for high input, the nmos transistor drives (pulls down) the output node while the pmos transistor acts as the load, and for low input the pmos transistor drives (pulls up) the output node while the nmos transistor acts as the load. Consequently, both devices contribute. Figure (a) CMOS inverter circuit. (b) Simplified view of the CMOS inverter, consisting of two complementary nonideal switches. V GS,n = Vin V DS,n = Vout V GS,p = -(V DD - Vin) V DS,p= -(V DD -Vout) When the input voltage is smaller than the nmos threshold voltage, i.e., when Vin < Vto,n the nmos transistor is cut-off. At the same time, the pmos transistor is on, operating in the linear region. Since the drain currents of both transistors are approximately equal to zero I D,n = I D,p= 0 the drain-to-source voltage of the pmos transistor is also equal to zero, and the output voltage VOH is equal to the power supply voltage. Vout = V OH = V DD On the other hand, when the input voltage exceeds (VDD + Vto,p ) the pmos transistor is turned off. In this case, the nmos transistor is operating in the linear region, but its drain to-source voltage is equal to zero. Consequently, the output voltage of the circuit is

10 Vout = V OL = 0 Next, we examine the operating modes of the nmos and the pmos transistors as functions of the input and output voltages. The nmos transistor operates in saturation if Vin > Vto,n and if the following condition is satisfied. V DS,n V GS,n-V TO,n Vout Vin-V TO,n The pmos transistor operates in saturation if Vin < (V DD + Vto,p), and if: V DS,p < V GS,p V TO,p V out < Vin-V TO,p Both of these conditions for device saturation are illustrated graphically as shaded areas on the Vout -Vin plane in above Fig. A typical CMOS inverter voltage transfer characteristic is also superimposed for easy reference. Here, we identify five distinct regions, labelled A through E, each corresponding to a different set of operating conditions. The table below lists these regions and the corresponding critical input and output voltage levels. Region Vin Vout nmos pmos A <V TO,n V OH Cut-off Linear B V IL High V OH saturation Linear C Vth Vth saturation saturation D V IH Low V OL Linear saturation E >(V DD + V TO,P ) V OL Linear Cut-off

11 Q5a) 1st module: module DFF(d,q,reset,clk); input d,reset,clk; output reg q; reset, posedge clk) begin if(reset) begin q=0; end if(d) q=d; else q=q; end endmodule second module: module RippleCounter(d,clk,reset,out); input [3:0] d; input clk, reset; output [3:0] out; // 4bit DFF a(d[0],out[0],reset,clk); DFF b(d[1],out[1],reset,out[0]); DFF c(d[2],out[2],reset,out[1]); DFF dx(d[3],out[3],reset,out[2]); endmodule 3rd module: module RippleCounterTOP; reg [3:0] d; reg clk, reset; wire [3:0] out; RippleCounter r(d,clk,reset,out); initial begin d=0;clk=0;reset=1; end always begin

12 #5 d=d+1; clk=~clk; end endmodule Q5b) Q6a)

13 Q6b) Latch-up is defined as the generation of a low-impedance path in CMOS chips between the power supply rail and the ground rail due to interaction of parasitic pnp and npn bipolar transistors. These BJTs form a silicon-controlled rectifier (SCR) with positive feedback and virtually short circuit the power rail to-ground, thus causing excessive current flows and even permanent device damage. In the equivalent circuit, Q1 is a pnp transistor whose base is formed by the n-well with its base-to-collector current gain as high as several hundreds. Q2 is a lateral npn transistor with its base formed by the p-type substrate with its base-to-collector current gain a few tenths to tens. Rwell represents the base-to-collector current gain of this lateral transistor may parasitic resistance in the n-well structure with its value ranging from 1 k to 20 kohm. The substrate resistance Rsub strongly depends on the substrate structure, whether it is a simple p- or p- epitaxial layer grown on top of the p+ substrate which acts as a ground plane. In the former case Rsub can be as high as several hundred ohms, whereas in the latter case the resistance can be as low as a few ohms. To examine the latch-up event, first assume that the parasitic resistances Rwell and Rsub are sufficiently large so that they can be neglected (open circuit).

14 Unless the SCR is triggered by an external disturbance, the collector currents of both transistors consist of the reverse leakage currents of the collector-base junctions and therefore, their current gains are very low. If the collector current of one of the transistors is temporarily increased by an external disturbance, however, the resulting feedback loop causes this current perturbation to be multiplied by (β1β2). This event is called the triggering of the SCR. Once triggered, each transistor drives the other transistor with positive feedback, eventually creating and sustaining a low-impedance path between the power and the ground rails, resulting in latch-up. Q7a) HOT ELECTRON:- This is an reliability problem caused by high electric fields within the device. We have seen that advances in VLSI fabrication technologies are primarily based on the reduction of device dimensions, such as the channel length, the junction depth, and the gate oxide thickness, without proportional scaling of the power supply voltage (constant-voltage scaling). This decrease in critical device dimensions to submicron ranges, accompanied by increasing substrate doping densities, results in a significant increase of the horizontal and vertical electric fields in the channel region. Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may, however, be injected into the gate oxide, and cause permanent changes in the oxide interface charge distribution, degrading the current-voltage characteristics of the MOSFET. Since the likelihood of hot-carrier induced degradation increases with shrinking device dimensions, this problem was identified as one of the important factors that may impose strict limitations on maximum achievable device densities in VLSI circuits. Figure: Hot-carrier injection into the gate oxide and resulting oxide damage. The channel hot-electron (CHE) effect is caused by electrons flowing in the channel region, from the source to the drain. This effect is more pronounced at large drain-to source voltages, at which the lateral electric field in the drain end of the channel accelerates the electrons. The electrons arriving at the Si-SiO2 interface with enough kinetic energy to surmount the surface potential barrier are injected into the oxide. Electrons and holes generated by impact

15 ionization also contribute to the charge injection. Note that the channel hot-electron current and the subsequent damage in the ate oxide are localized near the drain junction.. The hotcarrier induced damage in nmos transistors has been found to result in either trapping of carriers on defect sites in the oxide or the creation of interface states at the silicon-oxide interface, or both. The damage caused by hot-carrier injection affects the transistor characteristics by causing degradation in transconductance, a shift in the threshold voltage, and a general decrease in the drain current capability (Fig. 3.28). This performance degradation in the devices leads to the degradation of circuit performance over time. Hence, new MOSFET technologies based on smaller device dimensions must carefully account for the hot-carrier effects and also ensure reliable long-term operation of the devices. Q7b) Y-chart

16 Q7c) Design Rules Classification: Minimum width Minimum spacing Surround Extension Types of Design Rules: 1) Scalable Design Rules Lambda rules, which specify the layout constraints in terms of a single parameter (λ) and, thus, allow linear, proportional scaling of all geometrical constraints Based on scalable coarse grid -λ(lambda) The unit of lambda is micrometer Idea: reduce λ value for each new process, but keep rules the same Key advantage: portable layout Key disadvantage: not everything scales the same Not used in real life 2) Absolute Design Rules(Non-scalable or Micron Rules)

17 Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometres Based on absolute distances (e.g. 0.75μm) Tuned to a specific process (details usually proprietary) Complex, especially for deep submicron Layouts not portable We can specify the design rules using some convenient units, e.g., microns but what happens if we want to manufacture the chip using different manufacturers? Each piece of fabrication equipment used in the IC manufacturing process has limited accuracy. So, we need rules to ensure that the inaccuracy in the fabrication will not result in malfunction IC. Used to preserve topological features on a chip Prevents shorting, opens, contacts from slipping out of area to be contacted Interface between designer and process engineer Guidelines for constructing process masks Q7d) Formation of oxide of silicon on surface of silicon is termed as an oxidation USES: i) Surface passivation ii) Gate insulator iii) Diffusion masks When Si wafer is kept in air,on surface of Si wafer native oxidation take place which results in oxide of thickness A. maximum limit is 40 A. but for formation of thinox & thickox we requires 0.1µm and 1 µm respectively. METHODS OF OXIDATION: Thin film processes grown films typically converted from original substrate material example: SiO2 formed on Si substrate by thermal oxidation deposited films electro-deposition not standard IC process liquid phase deposition not standard IC process vapor phase deposition PVD: physical vapor deposition CVD: chemical vapor deposition Thermal Oxidation of Silicon Thermal Oxidation is characterized by high temperatures ( C).

18 Two main processes : Dry Oxidation Si(s) + O2 --> SiO2 Wet Oxidation Si (s) + 2H2O --->SiO2 + 2H2 Dry oxidation produces a better (more dense) oxide as Compared to wet oxidation

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