EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already

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1 EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements Sign up for Piazza if you haven t already 2 1

2 Assigned Reading R.H. Dennard et al, Design of ion-implanted MOSFET's with very small physical dimensions IEEE Journal of Solid-State Circuits, April Just the scaling principles C.G. Sodini, P.-K. Ko, J.L. Moll, "The effect of high fields on MOS device and circuit performance," IEEE Trans. on Electron Devices, vol. 31, no., pp , Oct K.-Y. Toh, P.-K. Ko, R.G. Meyer, "An engineering model for short-channel MOS devices" IEEE Journal of Solid-State Circuits, vol. 23, no. 4, pp , Aug T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp , April Outline Scaling issues Technology scaling trends Features of modern technologies Lithography Process technologies 4 2

3 Part 1: Technology A. Scaling Trends 3

4 Transistor Counts Doubles every 2 years 7 Frequency Frequency Trends in Intel's Microprocessors Frequency [MHz] Has been doubling every 2 years Itanium II Itanium Pentium Pro Pentium II Pentium 486DX Pentium MMX 486DX4 386DX Pentium III Pentium 4 Core2 i7 Nearly flat

5 Power Dissipation Power Trends in Intel's Microprocessors 00 0 Has been > doubling every 2 years ItaniumItanium II Core 2 i7 Power [W] Pentium Pro Pentium 486DX Pentium III Pentium 4 Pentium II DX Has to stay ~constant B. Scaling Issues 5

6 CMOS Scaling Rules Voltage, V / tox/ GATE WIRING W/ n+ source n+ drain L/ p substrate, doping *NA xd/ 11Å SCALING: Voltage: V/ Oxide: t ox / Wire width: W/ Gate width: L/ Diffusion: x d / Substrate: *N A RESULTS: Higher Density: ~ 2 Higher Speed: ~ Power/ckt: ~1/ 2 Power Density: ~Constant R. H. Dennard et al., IEEE J. Solid State Circuits, (1974). 11 CMOS Scaling Two 30nm transistors (then and now) 12 6

7 Transistor Scaling Shrink by 30% 28nm C. Auth, VLSI 12 Contacted gate pitch Shrink by 30% Gate pitch scales 0.7x every node Intel 22nm: contacted gate pitch 90nm 13 Ideal vs. Real Scaling I DSAT [µa/µm] Ideal I DSAT 0 V DD [xv] 1 Ideal T inv Ideal V DD T inv [ps] V Th [V] 0.1 Ideal V Th 0 00 Lg [nm] Leakage slows down V Th, V DD scaling 14 7

8 Technology Flavors LP keeps drain leakage constant 15 32nm Technology Flavors (Intel) 16 8

9 Lg, R, C scaling 000 Nominal feature size m 1 Gate Length 250nm 180nm 130nm 90nm 65nm 0.7X every 2 years 00 nm nm 50nm 45nm 32nm 22nm 0 35nm ~30nm With scaling L, need to scale up doping - scale junction depth (control leakage) S/D resistance goes up External resistance limits current I V / R R D DS channel ext 17 Parasitic Capacitance Scaling S. Thompson, Materials Today, Reality: Overlap + fringe can be 50% of C channel in 32nm 18 9

10 C. 32/28nm Technology Features Technology Features Lithography implications (this lecture) Restrictions on design Implications on design variability FEOL features (next lecture) Models 20

11 EE 141 Technology vs. 32/28nm FEOL 0.25 m features Lg ~ 240nm 248nm lithography No OPC, liberal design rules SiO 2 oxide, 3.5nm 6 dopant atoms LOCOS Nobody knew what strain is Velocity saturated No SD leakage No gate leakage One transistor flavor BEOL Al interconnect SiO 2 ILD 4-5 M layers No CMP, no density rules FEOL 32nm technology Lg = 30-35nm 193nm immersion lithography OPC, restricted design rules Hf-based dielectric ~ 2 dopant atoms STI Strained silicon in channel Velocity saturated I DS,off ~ 0nA/µm Low gate leakage Many transistor flavors BEOL Cu interconnect Lo-k ILD 8-11 M layers CMP, density rules 21 Step-and-Scan Lithography 22 11

12 Lithography Scaling 000 Nominal feature size scaling 1 00 m 365nm 248nm 193nm 250nm nm 180nm nm 90nm 0 65nm 45nm 32nm 22nm EUV 13nm EUV Technology of the future (forever)? 23 Sub-Wavelength Lithography Light projected through a gap 193nm light Mask Light intensity Light intensity 24 12

13 Sub-Wavelength Lithography CD k NA 1 Decrease Presently: 193 nm (ArF excimer laser) (Distant?) future: EUV Increase NA = nsinα Maximum n is 1 in air 193nm CDmin k nm Presently: ~ NA 0.92 Immersion Result: Shrinking k1 45nm technology beyond resolution limit Presently: Theoretical limit: