Reliability and Energy Dissipation in Ultra Deep Submicron Designs
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1 Reliability and Energy Dissipation in Ultra Deep Submicron Designs 5/19/2005 page 1
2 Reliability and Energy Dissipation in Ultra Deep Submicron Designs Frank Sill 31 th March /19/2005 page 2
3 Outline 1) Introduction 2) Trends 3) Reasons for Energy Dissipation and Variability 4) Solutions 5) Summary 5/19/2005 page 3
4 Why thinking about Energy and Reliability? increasing complexity increasing defect rate? increasing energy dissipation 5/19/2005 page 4
5 Why is Variability critical? Variability = variation of process / technology parameters Variability result in: Increasing delay of logic elements / wires Defect logic elements / wires Failed chips (defect Yield) Failed chips while run time (Reliability) Chips failed desired performance ( = delay) (parametric Yield) 5/19/2005 page 5
6 Variability in critical paths Variability 5/19/2005 page 6
7 Trends: ITRS Roadmap from: S. Brokar, VLSI 05 5/19/2005 page 7
8 Power Trends from: S. Brokar, VLSI 05 5/19/2005 page 8
9 Outline 1) Introduction 2) Trends 3) Reasons - Sources of Energy Dissipation - Sources of Variability 4) Solutions 5) Summary 5/19/2005 page 9
10 Sources of Energy Dissipation Energy = E switching + E leakage Energy = (C L V DD2 f t sc V DD I peak f V DD I leakage )*t VDD I gate Gate I sub I sc I dyn Source I gate Drain GND C L n+ SiO 2 I sub n+ L p - well 5/19/2005 page 10
11 Sources of Variability (1) Temperature Variations + Hot spots Power4 Server Chip from: Devgan, ICCAD 03 5/19/2005 page 11
12 Sources of Variability (2) Supply Voltage Drop from: S.Trester,2005 5/19/2005 page 12
13 Sources of Variability (3) Random dopant fluctuations Gate Gate Drain uniform Source Drain Source random # dopant atoms from: S. Brokar, VLSI 05 5/19/2005 page 13
14 More sources Electromigration Varying line width Soft errors (alpha particles, cosmic rays) 5/19/2005 page 14
15 Outline 1) Introduction 2) Trends 3) Reasons 4) Solutions - Goals - Triple Module Redundancy - Self adaptive design - Critical paths - Redundant Transistor Insertion 5) Summary 5/19/2005 page 15
16 Solutions: Goals 1) Increase defect and parametric Yield # Good Chips on Wafer Y = 100% Total # Chips 2) Increase Reliability 3) Decrease Energy nearly constant Reliability and Yield 5/19/2005 page 16
17 Triple Module Redundancy (TMR) - Implementation of three copies of the same circuit - Majority Voter decides (bit-wise) - Reliability R TMR R 3 +3R 2 (1-R), Energy x3 A B C OUT LOGIC copy of LOGIC A B C Majority Voter OUT copy of LOGIC : : 5/19/2005 page 17
18 Self adaptive design Extend idea of clock domains to Adaptive Power Domains Tackle static process and slowly varying timing variations Control VDD, V th (indirectly by body bias), T clock by Power On Test inputs and responses V dd T clock Test Module Module V bb 5/19/2005 page 18
19 Critical Paths from: S. Brokar, VLSI 05 - Problem: variations of gate properties in critical paths directly determine variation of clock frequency - Solution: Reduce count of critical paths 5/19/2005 page 19
20 Critical Paths and MVT Idea of MVT approach: use different types of Gates: LVT: fast, high leakage MVT: medium speed, medium leakage HVT: slow, low leakage Leakage reduced but count of critical paths increased! 5/19/2005 page 20
21 Critical Paths and MVT cont d Problem: Leakage reduced but count of critical paths increased! Solution: Use of HVT or MVT gates only if reliability does not fall below desired value Result: MVT allows adapted reliability User can decide between weighting of reducing leaking or increasing reliability 5/19/2005 page 21
22 Redundant Transistor Insertion Random insertion of redundant transistors Trade-off between Yield and Power Dissipation, Area, and Delay For constant delay: redundant transistors only in noncritical paths 5/19/2005 page 22
23 Redundant Transistor Insertion cont d Siristana, IEEE D&T,2004 5/19/2005 page 23
24 Summary Energy dissipation and variations top issues in deep submicron designs Improvement of yield and reliability only as tradeoff with energy dissipation and delay Redundant design and reduction of critical path count increases reliability 5/19/2005 page 24
25 Thank you! 5/19/2005 page 25
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