Design of Robust CMOS Circuits for Soft Error Tolerance

Transcription

1 Design of Robust CMOS Circuits for Soft Error Tolerance Debopriyo Chowdhury, Mohammad Amin Arbabian Department of EECS, Univ. of California, Berkeley, CA 9472 Abstract- With the continuous downscaling of technology, lowering of supply voltage and increase of operating frequency, integrated circuits become increasingly susceptible to single event effects (SEE) caused by high energy particles like alpha particles, neutrons from cosmic rays etc. A SEU may cause a bit flip in some latch or memory element, thereby altering the state of the system, leading to a soft error. Soft errors in memory have traditionally been a much greater concern than soft errors in logic circuits. However, as process technology scales below 1 nanometers, voltage levels go down and noise margins reduce, soft errors in logic circuits seem to be a potential threat too. In this work, we propose to analyze the effect of various circuit parameters on soft error susceptibility of logic circuits. Also, we plan to design a robust latch that has simultaneous SET and SEU tolerance. Index Terms- Soft Errors, SET, SEU Hardened Latch I. INTRODUCTION The continuous down-scaling of technology over the past decade has brought about tremendous boost in performance and levels of integration of CMOS VLSI circuits. However, drastic device shrinking, increased complexity, lowering of power supply, and increased frequency of operation that accompany the technological evolution to the nanometer regime have reduced dramatically the reliability of deeply scaled ICs. A significant problem is related to soft errors induced by alpha particles and atmospheric neutrons [1]. There are of course many other sources of error in ICs (gate-oxide breakdowns, electromigration etc) but it is reported that whilst the total failure rate of other effects comes to -2 FIT (failure in 1 9 device hours), that of SER can easily exceed, FIT/chip if no mitigation mechanism is employed [4]. Soft error phenomenon in memory circuits was known to exist as early as 197 [2], also radiation effects on spacecraft and airplane electronics have been known for long [3]. Memory designers have been traditionally using error correcting codes (ECC) to mitigate the effects of soft errors in memory. However, in today s deep submicron world, soft errors pose a threat to combinational and sequential circuits also. Thus, soft-error tolerant logic design has been an area of active research during the past few years; however the problem still defies an elegant and universal solution. In this work, we aim to investigate the effect of soft errors on circuits as they are scaled into the nanometer regime. We want to investigate the various methods that have been proposed till date to take care of the problems and analyze the merits and demerits. Finally, we want to design robust latches and combinational blocks that have good soft-error tolerance. The report is organized into four sections; section II covers the background, origin and effect of soft error on nanometer circuits. Section III is a literature review with an analytical flavor, while section IV outlines the proposed work for the rest of the semester as well as shows some initial simulation results. II. SOFT ERRORS: ORIGIN AND EFFECT ON INTEGRATED CIRCUITS A soft error occurs when a radiation event causes enough of a charge distribution to reverse or flip the data state of a memory cell, latch, flip-flop or even a node in a combinational block. The error is soft because the circuit or the device is not permanently damaged by the radiation. Soft error is also referred to as single event effect. If the radiation is of a very high energy, more than a single bit may be affected, creating a mutibit upset (MBU). However, MBUs are only a very small fraction of the total observed soft error upset rate. At this time, it is very important to make a distinction between single event transients (SET) and single event upset (SEU). When a sensitive node, typically the drain of an off transistor, is in the proximity of the ionization track of an electrically charged particle, it collects a significant part of the generated charge carriers (holes or electrons), resulting in a transient current pulse on this node. Depending upon the energy of the particle, the transient pulse may reverse the state of that node and the error might propagate through a sensitized path till it reaches the flip-flop. Thus, a transient generated by a combinational block remains a transient till it is captured by the flip-flop. This is referred to as SET. If the transient reaches the flip-flop at a time it is active, then the transient will be captured by the sequential element and lead to an erroneous value being stored in the flip-flop. In this case, an SET has been transformed to an SEU. In addition, a particle strike may also change the state of a flip-flop when it is in the hold mode and directly cause a single event upset. SEU have received a lot of attention over the last few years; however with the shrinking of device sizes and increase of clock frequency, SETs have also become a threat to the reliability of digital circuits. In this work, we aim to build circuits that provide combined resilience against SET and SEU. 1

2 The terrestrial environment is dominated by different mechanisms that generate (either directly or as secondary reaction products) energetic ions that are responsible for inducing soft errors. The magnitude of the disturbance an ion causes depends on the linear energy transfer (LET) of that ion (usually measured in MeV/sq-cm/mg) [4]. Alpha particles emitted by trace uranium and thorium impurities in packaging materials have been shown to be one of the dominant causes of soft error in integrated circuits. The second significant source of SER is related to cosmic rays. Primary cosmic rays react with the earth s atmosphere to produce complex cascades of secondary and tertiary particles. At terrestrial altitudes, 1% of the primary flux reaches the sea-level, where the flux is composed of protons, neutrons, pions etc []. Neutrons are one of the higher flux components, and since neutrons have higher LETs, they are the most likely cosmic radiation to cause upsets in devices at terrestrial altitudes. Since neutrons themselves do not generate ionization in silicon, the neutron flux alone does not define the cosmic ray component of SER. Neutrons interact with chip materials elastically and inelastically, producing ions that cause soft errors. The effect of a particle striking a node in a circuit can be modeled as a narrow current pulse of a given magnitude and duration being injected into a node. For example, a transient pulse caused by an alpha-particle can be modeled as a double exponential injection current given by [19], I inj (t) = I o ( e -t/t1 - e -t/t2 ), where I o is the maximum current, T1 is the collection time constant for a junction and T2 is the ion track establishment time constant. There is a Q critical for every node, which is the minimum amount of charge necessary to flip the state of the node. With the continuous downscaling of technology, the capacitance values are decreasing. Hence, for a given amount of charge transferred by an energized particle, the voltage change caused at a node is much greater (Q= CV). Hence, nanometer circuits are getting more susceptible to such transient errors. A simulation result is presented in Section IV to demonstrate this trend. As noted earlier, a transient pulse generated at a node of a combinational circuit can cause error if it propagates and gets captured by a flip-flop. There are three mechanisms in combinational logic circuits which mask the glitches generated by particle strikes [6]: Because of logical masking, a glitch might not propagate to a latch because of a gate on the path not being sensitized to facilitate such glitch propagation, e.g. one of the inputs of a nand gate being at zero. Because of electrical masking, a generated glitch might get attenuated because of the delays of the gates on the path to the output Because of latching-window masking, a glitch that reaches the primary output might not cause an error because of the latch not being open. However, because of the decreasing number of gates in a pipeline stage, logical masking as well as electrical masking has been decreasing for new technology generations. Electrical masking has also been decreasing because of the reduction in node capacitance and supply voltages in every generation. Furthermore, increasing clock frequencies have reduced the time window in which latches are not transparent, thereby reducing latching-window masking. Thus it is clear that soft errors are really important in today s era of nanometer circuits. Even though the soft error rate (SER) in combinational circuits is currently smaller than that of sequential and memory elements, it is expected to rise 9 orders of magnitude between 1992 to 211, when it will equal the SER of unprotected memory elements [6]. Figure 1: Comparison of SRAM SER with that of logic [4] III. SOFT ERROR MITIGATION TECHNIQUES Research in the field of soft error has various directions: Studying the origin of soft errors from a physics standpoint and model their exact effect on semiconductor devices [4] [7] [8] Development of CAD tools for soft error rate analysis in integrated circuits like SERA [9], ASERTA [1], SERTOPT [1] Introducing circuit techniques and new topologies to combat soft-errors in nanometer circuits In this project, our focus is in the third direction and hence this section deals with circuit techniques to make circuits more robust and reliable. The simplest way to take care of soft errors in logic circuits is Triple-Modular Redundancy (TMR). It s the simplest error masking scheme that uses three functionally equivalent copies of the logic circuit and a 2-out-of-3 majority voter. Errors are masked and hence tolerated. Figure 2 shows the structure of a circuit that has error masking based on TMR. However, the hardware and power overhead of conventional TMR, that targets all modeled faults in logic circuits, exceeds 2%. Thus simple TMR cannot definitely be a choice in modern ultra-dense integrated circuits. 2

3 Mohanram [11] proposed a method for partial error masking, which uses a combination of two reduction techniques, cluster sharing reduction and dominant value reduction, to reduce the overhead costs associated with TMR, while minimizing soft error rate. Cluster sharing is based upon two observations. If in addition to t 3, we sample u s output at t 1 and t 2 too, where t 1 <t 2 < t 3, and we then perform majority voting among the three sampled values, we will be able to obtain the correct value of u s output whenever an SET pulse does not overlap more than one sampling instant. This type of timing slack utilization has also been used in other works like RAZOR [13]. Nikolaidis [14] has also proposed transient fault detection based on time redundancy. The basic principle is shown in Figure 3. The circuit feeds both the signal and its delayed version to the latch and then some mechanism need to be designed that will prevent the latch to respond to transient perturbations. CLK Figure 2. Block Diagram for TMR-based error masking Combinational Circuit Output Latch Comparator The first is that in the presence of the three masking mechanisms described earlier, the soft error susceptibility of certain nodes in the logic can be orders of magnitude higher than that of other nodes in the design. The second is that these nodes tend to be clustered together, with low observability and controllability values. Cluster sharing reduction heuristic selects clusters of nodes that have high susceptibility and triplicates them like in conventional TMR. However, it also identifies clusters that have low susceptibility and does not replicate them; but shares them. Dominant value reduction differentiates between the logic and logic 1 soft error susceptibility of a primary output. It exploits the fact that the logic and logic 1 soft error susceptibility of certain primary outputs is highly skewed, i.e. the soft error failure rate at an output when it is at logic (logic 1) is close to an order of magnitude higher than when it is at logic 1 (logic ). The work in [11] combines this technique with cluster sharing mechanism, to further reduce hardware redundancy in the system. The advantage of this technique is reduced area overhead as compared to simple TMR. Also, the method can easily be implemented using standard design automation tools. However, if a particle strike occurs in a non-triplicated portion of the design and has sufficient strength, it will (in the presence of a sensitized path) propagate to the outputs of all three copies and thus go undetected. The area/power overhead (including majority voters) may still be intolerable in many applications. Also this work does not address the issue of particle striking a latch and directly causing a single event upset. Time redundancy is another approach that has been used to combat soft errors in integrated circuits. Krishnamohan [12] has proposed one such methodology. Since the effect of an SET is only temporary, it is possible to prevent a soft error by exploiting timing slack available at the primary output (PO) gate u preceding the latch. Let t 1 denote the worst-case propagation delay from the primary inputs to the output of u. The slack for u is then t s =t 3 t 1 (t 3 is the sampling instant) i.e., in the absence of an SET, u s output will be stable at its correct value in the rime interval [t 1,t 3 ]. CLK+δ Combinationa l Circuit CLK Latch 1 δ Latch 1 Output Latch CLK Comparator Figure 3: Two time-redundancy based approaches in [14] Research efforts to modify latch and logic structures to make them more immune have also been carried out. Arima [1] proposed a cosmic ray immune latch structure shown in Figure 4. Figure 4: Cosmic Ray Immune Latch reported in [1] The basic principle of the proposed cosmic-ray immune latch is as follows. It keeps its state on the three storage nodes, PDH, NDH, and DH. When a neutron impact destroys one of their values, the value can be restored by the values on the other two nodes so that the correct value is kept on the output node. The point is that the two 3

4 unharmed nodes are not affected even if the charge inflow continues to a failure node. Suppose that a soft error occurs on PDH when the latch keeps, as is shown in Fig. 4. The error turns off P1, after which DH loses its drive, but the output Q is kept at. It keeps N3 off, which to ensure the value on NDH is conserved even though the error on PDH turned on N2. Because these two unchanged s on Q and NDH keep P2 and P3 on, the correct value,, is restored on PDH. An upset on PDH does not affect NDH and DH, and this recovery mechanism works unless the noise charge continues to inflow longer than the decay time of DH. Recovery after a soft error on NDH works in the same way. The topology of the latch is indeed very robust; however it does not take any protection if a glitch has been generated by a combinational block and is captured by the latch. The latch is thus not SET hardened. Similar efforts have also been carried out to modify gates like inverters, nand gates etc to make them inherently soft error immune [16]. An example of a modified inverter is shown in Figure. Similar such topologies have been proposed for other gates too and they have been combined to build a new logic family. The problem with this logic family is that it requires some sizing to operate correctly i.e. it is ratioed logic. IV. INITIAL SIMULATION RESULTS AND PROPOSED WORK In order to demonstrate the importance of soft errors with the shrinking of device sizes, we have calculated the critical charge (Q critical ) required to cause a flip in the state of a node in an inverter chain. The effect of an energized particle hitting a diffusion area has been modeled by injecting a current pulse at a node and measuring the magnitude of current required to invert the state of the node. The actual magnitude of the charge is given by the following equation. Q critical = I d is the drain current induced by the charged particle and T f is the flipping time, which for logic circuits is just the time of the pulse. Figure 6 shows a plot of the simulated results. These were generated using the Berkeley Predictive Models [17]. From here, its evident that soft errors become a threat for sub 1nm technology nodes. 2 T f I d dt 2 18 Qcritical (fc) Technology Node (nm) Figure 6. Reduction in Q critical with Technology Scaling Figure. Soft Error Immune Inverter proposed in [16] Also, the area is doubled and this means increase in the requirement for capacitance drive and also power. It is easily seen that full swing is sacrificed on some nodes which causes static power dissipation which is a large problem. In general although this scheme provides hardening for logic, it may not scale well with technology. Some other techniques involve adaptive control of Vdd or capacitance at nodes to reduce SER [6]; however it incurs speed penalty at every node and thus slows down the circuit considerably. There are two characteristics of interest for a single gate in terms of error tolerance, the glitch generation and glitch propagation characteristics. Glitch generation characteristic determines the shape and magnitude of a pulse generated at the output of a gate because of an energized particle hitting the output of the gate. On the other hand, glitch propagation characteristics determine the electrical masking properties of the gate, i.e. how the gate attenuates a glitch that is generated at some prior circuit node as it passes through the logic gate. We have investigated the variation in generated and propagated glitch width with varying C L and V dd in an inverter chain in 9nm technology. As shown in Figure 7, the glitch width goes up with reduction in supply voltage because of reduced drive strength. The effect of node capacitance on transient pulse 4

5 generation is more subtle; if the capacitance is low then with the fixed amount of charge the voltage wants to be large. However, the voltage at the node of interest cannot be too large because the junction diode of the transistors will clip the voltage to a certain value depending on relative potential levels. So initially, with increase of the capacitance the voltage will not rise (for small values of C) and therefore the generated pulse width will increase with slowing the node down. Generated Glitch Width (ps) CL Variations Vdd Variations 1.2fF 9nm CMOS Vdd/CL Vdd(.V-1.4V) CL(.fF-1fF) Figure 7. Variation in Generated Width with Varying Capacitance and Vdd Propagated Glitch Width (ps) CL Variations Vdd Variations Vdd(.V-1.4V) Cl(.fF-1fF) Figure 8. Variation in Propagated Width with Varying Capacitance and Vdd We intend to employ both space and time redundancy techniques concurrently to meet the reliability criteria with the least possible area and power overhead. In addition, we want to analyze the effect of circuit parameters like threshold voltage variation on combinational circuit SER. Finally, we want to build a data path like a ripple adder to test and compare the merits of our design. After a certain point where the voltage (V=Q/C) is not large to be clipped, the effect changes trend. Here with increasing the capacitance the voltage gets smaller and therefore the generated pulse width or in general the effect of the strike is mitigated. From this analysis it becomes evident that for each gate structure, induced charge and technology node, there exists a critical capacitance that will introduce the worst effect on that node in terms of glitch generation. Reducing Vdd or increasing C L slows down a gate, which obviously attenuates a glitch propagating through it, as shown in the simulation result in Figure 8. If t pulse < t delay then the glitch dies down, where t delay is the propagation delay of the gate. If t pulse > 2t delay then the glitch goes through un-attenuated and anywhere in between means that the glitch will be attenuated while it is passed thorough. Thus slow gates have better glitch propagation characteristics. These studies have motivated us to consider the use of soft-error filtering techniques to handle transient glitches. The concept of error filtering has been introduced in mid- 8 s [18], however the techniques outlined there are not compatible with modern integrated circuits. We propose to design latch structures that have combined SEU and SET tolerance. This means that the latch should be immune to transient pulses coming in from the combinational block, even if it coincides with the sampling window; at the same time, the latch should be hardened against any particle strikes inside it. V. REFERENCES [1] R.C. Baumann, Soft errors in advanced computer systems, IEEE Des. Test. Computer., vol.22, no. 3, pp , May/Jun. 2 [2] T.C. May and M.H. Woods Alpha-Particle Induced Soft Errors in Dynamic Memories, IEEE Transactions in Electronic Devices, VOL ED-26, No. 1, 1979, Page(s): 2-9 [3] K. Johansson, et al., n-flight and ground testing of single event upset sensitivity in static RAMs, IEEE Transactions on Nuclear Science, June 1998 [4] R.C. Baumann, Radiation-Induced Soft Errors in Advanced Semiconductor Technologies, IEEE Transactions on Device and Materials Reliability, Vol., No. 3, September 2 [] J.F. Ziegler and W.A. Lanford The effect of sea level cosmic rays electronic devices, Journal of Applied Physics, vol. 2, no. 6, pp , 1981 [6] Abdulkadir Utku Diril, Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic, PhD Dissertation, Department of Electrical and Computer Engineering, Georgia Institute of Technology, May 2 [7] P.E.Dodd and L.W.Massengill, Basic mechanisms and modeling of single-event upset in digital microelectronics, IEEE Trans. Nucl. Sci., vol., no. 3, pp 83-62, Jun. 23 [8] F.W. Sexton, Destructive single-event effects in semiconductor devices and ICs, IEEE Trans. Nucl. Sci., vol., no. 3, pp , Jun. 23 [9] Ming Zhang and Naresh Shanbhag A Soft Error Rate Analysis (SERA) Methodology, in Proc. of IEEE International Conference on Computer-Aided Design, ICCAD 24, pp

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