Accurate and computer efficient modelling of single event transients in CMOS circuits

Transcription

1 Accurate and computer efficient modelling of single event transients in CMOS circuits G.I. Wirth, M.G. Vieira and F.G. Lima Kastensmidt Abstract: A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate. 1 Introduction When an ionising particle strikes a sensitive region in a semiconductor device, the resulting electron-hole pair generation can cause a transient pulse that may alter the logical state of the struck circuit node. In digital circuits, this temporary voltage or current disturbance at a circuit node is called a single event transient (SET). A SET may change the results of a computation, if it propagates to a latch or other memory element. With decreasing device dimensions in modern technologies, SETs become a concern not only in space environment, but also at sea level. This makes computer-efficient techniques to analyse the sensitivity of circuits composed by millions of transistors mandatory. At sea level there are two major radiation sources that can cause SET [1]. The first set of sources is composed by atmospheric neutrons and protons, which may create secondary ions when interacting with the nucleus of the atoms in the target device. The second type of sources is alpha particles emitted by radioactive impurities present in the device itself or in the packaging materials. At aircraft altitude or space environment cosmic rays (heavy ions) are # The Institution of Engineering and Technology 2007 doi: /iet-cds: Paper first received 25th July 2005 and in revised form 7th June 2006 G.I. Wirth and M.G. Vieira are with the State University of Rio Grande do Sul - UERGS, Estrada de Santa Maria 2300, Guaiba RS 92500, Brazil G.I. Wirth is also with the Federal University of Rio Grande do Sul - UFRGS F.G. Lima Kastensmidt is with the Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, RS, Brazil wirth@inf.ufrgs.br also a concern. The effect of a particle strike at a given circuit node is a charge deposition at that node. Different radiation sources show different charge deposition waveforms. The transient pulse generated by the charge deposition mechanism might not be captured by a memory circuit because it could be logically, electrically or latchingwindow masked [2, 3]. Logical masking occurs when a particle strikes a circuit node that is blocked out from affecting the output due to a subsequent gate the output of which is determined solely by its other inputs. Electrical masking occurs when the transient pulse generated by the particle hit is attenuated as it propagates through the logical gates and filtered out before it reaches a memory element. Strong pulses may propagate through more logical gates than weaker ones. Narrow pulses can more easily be attenuated as they propagate along a sensitised path to primary outputs or memory elements [4]. Latching-window masking occurs when the transient pulse reaches a latch outside the latching window, that is, not at the clock transition when the latch captures its input values. Narrow pulses have a smaller latching probability than wider ones, since the wider the pulse the higher the probability, it reaches a memory element at the latching window [4]. Hence, the waveform shape can be the decisive factor for a SET to be captured by a memory element and cause a computation error. As a consequence the soft-error susceptibility of internal nodes in a logic circuit may vary by orders of magnitude. This makes possible to significantly reduce the soft error rate with a reduced cost overhead. Once the nodes with the greatest soft-error susceptibility are identified, soft-error hardening techniques may be applied to decrease the susceptibility of these nodes. In IET Circuits Devices Syst., 2007, 1, (2), pp

2 this work, the transient pulse generation mechanism in combinatorial logic gates is studied and modelled, helping to implement a simple methodology for identifying the logic circuit nodes most susceptible to transient faults. The SET phenomenon may be analysed at different (hierarchical) levels of abstraction. An important point to be considered is at what level transient faults should be injected to properly model the response of the struck circuit. Higher level fault models, such as logic or system level models, increase simulation speed. Transient faults may be injected at different levels of abstraction by either altering the logic values or momentarily changing the voltage levels and charging states of the struck nodes. Lower level models may be obtained via device-level simulation of the effect of an ionising particle penetrating a device, leading to transient currents at the struck node. At circuit level, models may be obtained for the Spice simulation of the resulting transient currents. At the logic level, transients may be modelled as momentary bit-flips in the logic state of the struck node, simulating its propagation to a memory element. At the system level, transient faults can be approximately emulated by altering the logic state of the target system. The possibility to evaluate the system at different levels of abstraction is important to allow the designer to choose the proper balance between speed and accuracy. A key point is the availability of models that properly link the effects from lower abstraction levels up through the higher levels. A number of different methodologies for the evaluation of the sensitivity of digital circuits to SETs have been proposed [5 11]. There are different methodologies, which range from hardware prototyping and its exposure to radiation sources, to device level, circuit level and system level simulation. Hardware prototyping is very expensive and time-consuming and is neither justified nor practical for early design development stages. Full transient simulation, either at device or circuit level, is not practical for a comprehensive evaluation of the sensitivity of complex circuits to all the different radiation sources. The availability of a simple analytical model, which links the transistor level effects to the logic level without requiring circuit simulation, would greatly simplify the evaluation of circuit sensitivity to SET. This work is aimed at providing such a simple model. In addition, this model will help the evaluation of SET induced failure rate. The failure rate is a statistical quantity that requires modelling of hundreds of thousands of charge collection events in order to obtain a statistically meaningful picture [12]. The statistical running of a conventional circuit simulator, taking into account all possible particle induced transient current waveforms, is a computationally prohibitive task, which enforce the need for a simple analytical model. The goal of this work is to help in improving the computational efficiency of the evaluation of the sensitivity of digital circuits to SETs. The model describes the behaviour of the ionising particle strike phenomenon at the logic level and avoids running costly circuit level simulations. This allows one to rapidly determine the range of particle charge depositions for which the circuit is SET robust. charge is conducted away via open current paths to V DD or ground, returning the logic node to its original state. If pulse amplitude is high enough and the duration is long enough, the pulse may propagate through subsequent circuit stages and change the results of a computation. Hence, pulse amplitude and duration are key parameters for the evaluation of circuit sensitivity to soft errors. The sensitive sites are the surroundings of the reversebiased drain junctions of a transistor biased in the off state [13], as, for instance, the drain junction of the p-channel transistor in Fig. 1. As current flows through the pn-junction of the struck transistor, the transistor in the on-state (n-channel transistor in Fig. 1) conducts a current that attempts to balance the current induced by the particle strike. If the current induced by the particle strike is high enough the on-transistor cannot balance the current and a voltage change at the node will occur. This voltage change lasts until the charge is conducted away by the current feed through the on-transistor. Through this work a SET that may propagate to the next stage is assumed to be generated by the particle hit, if the voltage at the struck node changes by more than V DD /2, that is, if the voltage change at node crosses the logical threshold. The transient pulse duration or width T D is defined as the time during which the voltage change (perturbation) at the node is greater than V DD /2. In circuit analysis, the charge collection mechanism is represented by introducing a transient current source with the appropriate characteristics at the circuit node where the particle hit occurs, as shown in Fig. 1, which depicts the situation for a particle hit at the drain junction of the p-channel transistor in the off state. For particle hits at drain junctions of n-channel transistors in the off state, the transient current is in the opposite direction. Device level simulations carried out by various groups demonstrated the validity of this approach for circuit level analysis of SET [6 10]. At the circuit level, the charge deposition mechanism can be modelled by a double exponential current pulse at the particle strike site [14] I P (t) ¼ I 0 e t=t a e t=t b (1) where I 0 is approximately the maximum charge collection current, t a is the collection time constant of the junction and t b is the time constant for initially establishing the ion track. The maximum charge collection current I 0 depends on the ionising particle linear energy transfer (LET) value, process and electrical parameters. Once the values of I 0, t a and t b are determined for a given technology and particles of interest, any circuit designed in that technology may be evaluated at the circuit level modelling the charge deposition mechanism by (1). The values of I 0, t a and t b for a given technology may be obtained by device simulation as well as from closed form expressions. See, for instance, [12 15]. In the following circuit simulations and 2 Modelling transient pulse generation If an ionising particle strikes a sensitive region in a semiconductor device, the resulting electron-hole pair generation can cause a transient current that may alter the logical state of the circuit. The charge deposition mechanism produces a transient pulse that lasts until the deposited 138 Fig. 1 At Spice level simulation the charge deposition mechanism is modelled by a transient current source IET Circuits Devices Syst., Vol. 1, No. 2, April 2007

3 modelling, t b is assumed to be much smaller than t a, whereas t a is used as a variable parameter, which is in line with the experimental findings [12 14]. Typically, t a increases almost linearly with increasing LET [15]. In the following, a simple analytical model that yields results equivalent to circuit simulation, if a current pulse as given by (1) is injected at the struck node, is derived. The model will provide information that is valuable for logic level analysis of SETs, namely, SET pulse duration (width) and amplitude, without the need to run circuit level (Spice-level) simulations. For transient fault analysis, the circuit is sub-divided into stages, in an approach similar to the one used in timing analysis, at the design logic level [16 17]. A stage is then a structure composed by a PMOS block and a NMOS block connected to the output node, as depicted in Fig. 2. The block is a set of series parallel connected transistors. A stage can be an inverter, a NAND, a NOR or a complex gate. A buffer, a SRAM-cell, an AND or an OR gate are then made up of two or more stages. For modelling purposes, a network model as depicted in Fig. 3 is used, where C is the effective capacitive loading lumped onto the output node, and R the effective resistance of the pull-up path (if the PMOS block is on ) or pull-down path (if the NMOS block is on ). I P (t) is the current induced by the particle strike, as given by (1). Once the effective resistance, R, for each transistor type (n or p) in a given technology has been determined, the effective resistance, R, of the transistors with different geometries can be determined by multiplying the W/L ratio of the actual transistor. The use of a linear resistor to model the pull-up or pull-down path is a method well known from switch-level simulators [17]. The differential equation describing the voltage V(t) at the struck node is C dv(t) þ V(t) dt R ¼ I P(t) (2) The solution of this differential equation leads to the voltage V(t) at the struck node. For t b much smaller than t a, the solution is V(t) ¼ I 0t a R t a RC e t=t a e t=rc The time t peak at which the node voltage reaches its maximum value can then be evaluated as being t peak ¼ ln(t a =RC)t a RC t a RC (3) (4) Inserting t peak back into (3) leads to the peak transient voltage V peak reached at the struck node V peak ¼ I 0t a R t RC=(RC ta ) a t ta =(RC t a a ) (5) t a RC RC RC The minimum injected charge Q C (Q C ¼ I 0 t a ) needed to cause a transient pulse of amplitude V peak is then V peak (t a RC) Q C ¼ R((t a =RC) RC=(RC t a ) (t a =RC) t a =(RC t a ) ) By exploring the asymptotic behaviour of (6), the model can be further simplified. From mathematical analysis, it is found that if t a is much smaller than RC, then Q C! V peak. C. If t a is much greater than RC, then Q C! (V peak /R)t a. This can be understood by observing that if t a is much smaller than the RC time constant, the charge amount that flows through R before V peak is reached is negligible. The term V peak. C corresponds to the charge stored in C. Ift a becomes large when compared to RC, the charge amount that flows through R becomes much greater than the charge stored in C. From this asymptotic behaviour a simpler equation can be proposed to model circuit behaviour (6) Q C ¼ Q N þ (V peak =R)t a (7) where Q N ¼ V peak. C. Now that a simple and computer efficient formulation for the minimum injected charge needed to cause a transient pulse of amplitude V peak has been obtained, the transient pulse duration (width) T D may be evaluated. Starting from (3) a simple equation for the transient pulse duration T D may be derived. The voltage V(t) at the struck node shows a double exponential behaviour. After the peak transient voltage V peak is reached at time t peak, the node voltage starts to decrease exponentially. Exploring the asymptotic behaviour of (3) in a similar way as done in the derivation of (7), the following equation may be proposed T D ¼ t peak RC ln V DD=2 V peak!! t a ln V DD=2 V peak where the sum of t peak to the second term on the right-hand side corresponds to the analytical solution, if RC is much greater than t a, and the sum of t peak to the third term to the analytical solution, if t a is much greater than RC. Mathematical analysis of (5) allows the determination of a simple and accurate fitting for the transient pulse amplitude V peak V peak ¼ I 0t a R t a þ RC (8) (9) Equation (9) is computationally more efficient than (5) and is used in Section 3, where model equation results are compared with Spice-level simulations. Fig. 2 Circuit stage is a structure composed by a NMOS block and a PMOS block Fig. 3 Equivalent circuit for calculating circuit response to an ionising particle hit IET Circuits Devices Syst., Vol. 1, No. 2, April

4 From (7) it can be seen that there are two major components that contribute to the minimum injected charge Q C needed to cause a transient pulse of amplitude V peak. The first is the charge Q N needed to charge or discharge the node capacitance C. The second component is the charge that is conducted away via open current paths to V DD or ground. For fast transients (t a smaller than the RC time constant) the first component dominates. For slow transients the second component dominates. This behaviour can be clearly seen in Figs. 4 and 5, where for small t a the charge needed to induce a SET with peak amplitude V peak ¼ V DD /2 is approximately constant. As t a increases, the charge needed to induce a SET of amplitude V DD /2 increases, due to the increase in charge flowing through the effective resistance R during the slower charge deposition process, represented by a greater t a. The behaviour of transient pulse duration T D is similar. For fast transients (t a smaller than the RC time constant), the particle hit induced current pulse first changes the charging state of the node capacitance and T D is dominated by the RC time constant, as given by the second term on the left-hand side of (8). For slow transients (t a greater than the RC time constant), the third term on the left-hand side of (8) dominates, and pulse duration is dominated by t a. This behaviour can be seen in Fig. 6. Transient fault modelling using an approach similar to (6) and (7) has already been proposed, as for instance in [6 10] for SRAM cells. But in these works, dynamic quantities inherent to the studied circuit, like the flipping time T F of the SRAM cell, are used in the model equations. Consequently, Spice simulations would need to be run to evaluate these dynamic quantities, for example, the flipping time T F corresponding to the different ionising particles of interest, incidence sites and angles. In this work, only static quantities are used. This makes the model more appropriate for integration into CAD tools. Earlier approaches to the problem did use an empirical approach and curve fitting, or did restrict the range of particle hits analysed, as for instance in [18]. To the best of our knowledge, this is the first time that a simple analytical model, based solely on the primary parameters of the injected current transient and basic circuit parameters, is proposed and validated for a broad range of particle strikes at various gates in different technology nodes. Fig. 5 Minimum charge Q c against collection time constant t a for the injected transient current just capable of inducing a SET at the output of a 2-input NAND gate with fan-out 1 in the 0.10 mm technology Circles are analytical model results after detailed equation (6) Triangles are analytical model results after simple equation (7) 3 Model validation The model is validated by comparing the results obtained using (6 8) to Spice-level circuit simulation in four different technology nodes: the commercially available AMS 0.35 mm technology node [19], as well as the models made publicly available by the device modelling group at the University of California at Berkeley for the 0.18, 0.13 and 0.10 mm technology nodes [20]. Spice transient analysis is performed injecting a double exponential current pulse as given by (1), with the values of I 0 and t a being used as the variable parameters to determine the minimum charge Q C corresponding to a given t a. The double exponential model as given by (1) is proven to be adequate to study the SET mechanism at the circuit simulation level [2 6, 1, 11, 14]. Supply voltages V DD are 3.3 V, 2.2 V, 1.5 V and 1.2 V, for the 0.35 mm, 0.18 mm, 0.13 mm and 0.10 mm technology nodes, respectively. Inverters, 2- and 4-input NAND Fig. 4 Minimum charge Q c against collection time constant t a for the injected transient current just capable of inducing a SET at the output of a 4-input NAND gate with fan-out 4 in the 0.10 mm technology Circles are analytical model results after detailed equation (6) Triangles are analytical model results after simple equation (7) 140 Fig. 6 Transient pulse duration (width) T D against collection time constant t a for the injected transient current capable of inducing a SET of amplitude V DD at the output of an inverter with fan-out 1 in the 0.13 mm technology Circles are results after analytical model equation (8) IET Circuits Devices Syst., Vol. 1, No. 2, April 2007

5 Fig. 7 Charge Q against collection time constant t a for the injected transient current capable of inducing a SET of amplitude V DD at the output of an inverter with fan-out 1 in the 0.13 mm technology Circles are analytical model results after detailed equation (6) Triangles are analytical model results after simple equation (7) gates, and 2- and 4-input NOR gates with different fan-out (loading) are simulated. At this point, only particle hits at the drains of the transistors connected to the output node of the logical gate are considered, that is, particle hits that cause direct charge injection at the output node of a stage (logical gate). Particle hits at internal nodes of a gate will necessarily cause a smaller SET at the output node. The main goal of the work is to provide a simple analytical model to evaluate the sensitivity of each gate in a complex circuit. It is the most critical node that determines the sensitivity of the gate. Nevertheless, it is important to note that the model may be used to analyse the sensitivity of internal nodes as well, since circuit analysis techniques may be used to reduce the circuit to one equivalent to the one in Fig. 3. First, the minimum charge needed to cause a SET, as a function of the primary particle hit parameters I 0 and t a, is evaluated. A SET is assumed to occur if the voltage at the struck node changes by more than V DD /2, that is, V peak is set equal to V DD /2 in (6) (8). If the logical threshold is not equal to V DD /2 the derived model equations are still valid. Values different from V DD /2 may be set for V peak in the model equations. Several simulations are performed in order to evaluate the minimum I 0 corresponding to each t a in the range of the collection time constants of the junction. Note that for the determination of the minimum required charge Q C corresponding to a given pulse duration a large number of Spice simulations needs to be performed. Here, some typical results obtained when comparing model and circuit simulation are presented. For all simulations performed in the four technologies studied, agreement between circuit simulation and analytical model equations was within 20% or better if simple model (7) is used. If detailed model (6) is used, agreement between model and simulation is better than 9%. Fig. 4 compares simulation results with model equations for a 4-input NAND gate with fan-out equal to 4 in the 0.10 mm technology node. All transistors are of minimum size. Three inputs are at logical 0 (ground) and the other one is at logical 1 (V DD ). The particle strike is assumed to occur at the drain of the n-transistor connected to the output node. The struck transistor is in the off-state. The effective resistance R of the pull-up path is 5.4 kv. The effective capacitive loading C lumped onto the output node is 2.7 ff. Good agreement between model and Spice simulation is found. Fig. 5 compares simulation results to model equations for a 2-input NAND gate with fan-out equal to 1 in the 0.10 mm technology node. Both inputs are at logical 0. The particle strike is assumed to occur at the drain of the n-transistor connected to the output node. The struck transistor is in the off-state. The effective resistance R of the pull-up path is 8.1 kv. The effective capacitive loading C lumped onto the output node is 0.45 ff. Again, good agreement is found between Spice simulation and model. For fast transients (t a much smaller than RC) at a given logical gate and fan-out, Q C depends weakly on the state of the gate inputs. In this case, Q C corresponds approximately to the charge amount needed to initially charge the node capacitance, and the parasitic capacitance of added drain or source junctions is usually small if compared with the other capacitances involved. However, for slower transients (t a much greater thanrc), Q C depends strongly on the state of gate inputs. This is because the change in current that flows through open paths to V DD or ground. For instance, for a particle strike with t a ¼ 80 ps at the same 2-input NAND gate shown in Fig. 5, if one of the gate inputs is at logical 1 instead of both of them at logical 0, Q C decreases from 5.9 to 3.2 fc. This happens because two conducting p-transistors in parallel show half the resistance R of a single one conducting. Please note that both amplitude and duration of the SET depend on the equivalent resistance R. Hence, amplitude and duration of the SET generated by the particle hit depend on the inputs of the struck gate. Next, the duration of a SET induced by a particle hit that deposits a charge greater than Q C is evaluated. The transient pulse duration or width T D is defined as the time during which the voltage change (perturbation) at the node is greater than V DD /2. Fig. 6 shows the comparison between model prediction as given by (8) and circuit simulation results for an inverter in the 130 nm technology node. Inverter input is at logical 0 and fan-out is 1. The particle strike is assumed to occur at the drain of the p-transistor in the off-state. The effective resistance R of the pull-down path is 8.2 kv. The effective capacitive loading C lumped onto the output node is 0.70 ff. All transistors are minimum size. Fig. 7 shows the corresponding charge Q deposited by the particle strike. Again, good agreement between model and Spice simulation is found. The effective capacitance C is the sum of all parasitic capacitances lumped at the node, including interconnect, drain junction and the capacitive loading due to the logic gates driven by the struck node. The effective resistance R is computed on a pre-characterisation step. For n-transistors, it was computed as the mean value of the channel dc resistance for gate voltage equal to V DD and a drain source voltage exponentially decaying from V DD to zero, with the source terminal connected to ground. For p-transistors, it was computed as the mean value of the channel dc resistance for the gate terminal connected to ground and a source drain voltage exponentially decaying from V DD to zero, with the source terminal connected to V DD. It has to be done only once for the fabrication process of interest. Once the effective resistance R for each transistor type (n or p) in the process technology of interest has been determined, the effective resistance R of transistors with different geometries is determined by multiplying the W/L ratio of the actual transistors. The effective resistance of the IET Circuits Devices Syst., Vol. 1, No. 2, April

6 pull-up and pull-down paths of the different gates is computed as a series-parallel resistance association. Concerning the validity of model equations, it is known that modelling the charge deposition mechanism by a double exponential current pulse as given by (1) can lead to unrealistic values for the peak transient voltage at the struck node. If unphysical values are chosen for the parameter pair I 0 and t a, it can lead to voltages well above V DD or well below ground. In this case, (5) and (9) will also lead to unrealistic values for the peak transient voltage. If physically consistent values for I 0 and t a are used, the analytical model equations will lead to results that conform to the ones obtained by circuit simulation. Future work, which is underway, includes the implementation of the model into a timing simulation tool, in which a SET generated by an ionising particle hit is propagated through the circuit logic stages until it reaches a latch or other memory element. 4 Conclusions An accurate and computationally efficient model for the evaluation of amplitude and duration of SET generated by ionising particle hits has been proposed. Equation (8) describes SET duration (width), and (5) and (9) describe SET amplitude. Equations are simple and computationally efficient. A simple equation for the minimum injected charge need to induce a SET is also provided (7). Only two circuit parameters are used in the model equations, namely, the effective capacitive loading C lumped onto the output node, and the effective resistance R of the pull-up or pull-down path. Model derivation is in strong relation with circuit electrical behaviour and is consistent with technology scaling. The model allows the evaluation of the critical charge Q C needed to induce a SET, as well as the duration of a SET induced by a particle hit that deposits a charge greater than Q C, without the need to run electrical simulations of the circuit response to the particle hit. This makes the model suitable for implementation into CAD tools for automated evaluation of MOS circuit sensitivity to SETs and failure rate. From the comparison between model and circuit simulation results, it can be concluded that the simple analytical model provides results equivalent to those obtained when the SET mechanism is evaluated using standard circuit simulation techniques, that is, modelling the charge deposition mechanism by a double exponential current pulse as given by (1). 5 References 1 Ziegler, J.F.: Terrestrial cosmic rays, IBM J. Res. Dev., 1996, 40, (1), pp Wirth, G.I., Vieira, M.G., and Kastensmidt, F.G.: Computer efficient modeling of SRAM cell sensitivity to SEU. Proc. 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