Single Event Transient Effects on Microsemi ProASIC Flash-based FPGAs: analysis and possible solutions

Transcription

1 Single Event Transient Effects on Microsemi ProASIC Flash-based FPGAs: analysis and possible solutions L. Sterpone Dipartimento di Automatica e Informatica Politecnico di Torino, Torino, ITALY 1

2 Motivations and Goals Evaluation of Single Even Transients (SETs) impact on complex designs is an increasing challenge Their analysis have to face several issues Simulation Model is intrinsically approximative, simulation campaigns take long time Effective analysis Laser and Radiation testing are expensive and not applicable at the design early stage A CAD tool able to analyze and reduce the impact of SETs affecting VLSI technology is very welcome Early stage design analysis Fast and effective analysis 2

3 Outline Introduction Single Event Transient phenomena Preliminary studies on Flash-based FPGAs Gates characterization PIPB effect SETA main flow Main routines SET generation SET propagation Experimental results Conclusions 3

4 Introduction Different scenarios may influence SET propagation Logical masking Electrical broadening or filtering Latching window Not all the SETs are transformed in circuit errors SET sensitivity is intrinsically related to the technology cell Different sensitivity figures 4

5 Source of SET effects Generation of SET effects is due to the injunction of charge collection When a charged particle crosses a junction area, it generates an amount of current, provoking a glitch Propagation of voltage glitches may be for notable distances SET may become indistinguishable from normal signal 5

6 Single Event Transient - info SET can be defined considering four main parameters: SET width SET amplitude Rise ΔV/ΔT Fall ΔV/ΔT Rise ΔV/ΔT Fall ΔV/ΔT 6

7 Single Even Transient Phenomena Two transitions are possible -1- or 1--1 SET is generated into the sensitive area of a logic gate It propagates until a sequential element is reached During the propagation the SET may pass through different gates: INV, NAND, OR, AND, 7

8 SET sampling The effect of an SET is mainly due to: Location Arrival time Pulse s width. Clk Infinite number of combinations Clk b FF b The sensitivity of a FF can be measured as the ratio between the SET s width and the CLK period 8

9 Flash-based FPGAs background The Flash-based FPGAs are composed of: Logic, I/O, Routing The basic element is the VersaTile logic block A Flash configuration memory controls all the resources Bitstream programs the desired circuit Flash-based FPGA array Switch Matrix FFs 3-in VersaTile AND Logic Function 9

10 Radiation effects in Flash-based FPGAs VersaTile may undergo to three possible effects due to radiation particle hits: 1. Induce a pulse propagated through the logic 2. Affect a logic cell configured as a latch 3. Affect a junction of the floating gate SEU No transient effects have been recorded AND SET pulse shape may be: - Broadened / filtered - Amplified / attenuated INV OR 1

11 SET propagation background SETs are generated into the sensitive area of a logic gate Two transitions are possible (-1- and 1--1) Propagation continues until a sequential Wirth et al, NSREC element 28 is Sterpone, Battezzati, Lima RADECS 21 reached Fist Region: If(τ n < k*tp ) then τ n+1 = Second Region: If (τ n > (k+3)*tp) then τ n+1 = τ n + tp Third During Region: If ((k+1)*tp the < propagation τ n < (k+3)*tp) then τ n+1 the = (τ 2 n - SET tp may pass through 2 )/ τ n + tp Fourth different Region: If (k*tp gates < τ n < (k+1)*tp) (i.e. then inverting τ n+1 = (k+1)*tp(1 - gates) e (k ( τn / tp )) ) + tp For a 1 1 transition tp is defined as: tp = tphl tplh For a 1 transition tp is defined as: tp = tplh tphl 11

12 Related works Fundamental concepts on SET sensitivity of Flashbased FPGAs (MicroSemi FPGAs) Methodologies and test circuits for measuring pulse widths of SETs Messengill et al, TNS 28 Insights SETs propagation into chains of gates and Propagation Induced Pulse Broadening (PIPB) effects V. Ferlet et al, TNS 27 Analysis of SEUs dependencies on high frequency and architectural implementation M. Berg et al, TNS 26 Transient pulses generalities in microcircuits S. Rezgui, several TNS R. D. Schrimpf et al, TNS 26 12

13 SETs on Actel Flash-based FPGAs Radiation tests have been executed: - Measurement of the pulse s width - Frequency impact on SEE on Flash-based FPGAs 13

14 SETs on Actel Flash-based FPGAs Experimental results

15 SETs on Actel Flash-based FPGAs Ni ions Ag ions 15

16 SETs on Actel Flash-based FPGAs Radiation tests performed at the HIF, Louvain- La-Neuve, Belgium Iodine beam LET 61.8 MeV cm 2 / mg DUT: pipelined multiplier 16

17 SETs on Actel Flash-based FPGAs Circuit FF tiles [#] Combinational Tiles[#] v1 2,484 3,45 126,84 v2 2,484 3,45 252,446 Routing resources [#] Circuit Observed events [#] Design Cross-section v E-4 v E-4 [TNS 9] 17

18 Existing CAD tools for SET analysis 2D and 3D device model simulation or technology CAD (TCAD) or SPICE are generally adopted effective only on a reduced portion of a circuit thousands of gates very low speed Cannot be realistically applied to an entire circuit PIPB effect is not modeled and characterized with respect to a given technology Dynamic PIPB model embedded in SPICE has proven and demonstrated to be effective Sterpone et al, TNS

19 The developed SETA tool HDL SETA flow Libero IDE post-layout Netlist to PDD bitstream PDC Circuit Allocated Graph Native implemenation flow starting from the VHDL/Verilog to the FPGA configuration bitstream FPGA gate library SETA Algorithm Post-layout HDL and the Physical SET sensitivity computation for SET sensitivity Design Constraints files are Logic gates and routing description each FF of the circuit report generated by the native flow including PIPB characterizations 19

20 Netlist to Physical Design Description The circuit netlist is loaded A directed graph structure is generated I/O element, FFs, RAM/ROM pins, are considered as terminal points Logic gates are considered as crossing points Interconnections are defined as direct edges between nodes 2

21 Circuit allocated graph The circuit graph is organized in a matrixbased graph Vertices placed on the same layout position Edges related to the FPGA routing model FF1 G 1 G 2 FF4 FF2 G 4 FF3 G 3 21

22 SETA algorithm a set of SET pulse shape is generated defined as a voltage spike voltage amplitude / width Defined as 1. points (resolution of 1ps) 1. Generate the list of SET pulse: SET GP 2. For each generated pulse p (SET GP ) 2. For each sensitive node i (SN) Apply pulse p to i Find destination node dn (SN, i) 3. For each dn Propagate p on (i, dn) 22

23 SETA algorithm The generated voltage pulse is applied to the selected sensitive node FF1 G1 G2 FF4 1. Generate the list of SET pulse: SET GP 2. For each generated pulse p (SET GP ) 2. For each sensitive node i (SN) Apply pulse p to i Find destination node dn (SN, i) 3. For each dn Propagate p on (i, dn) 23

24 SETA algorithm The list of destination node is created FF1 G1 G2 FF4 1. Generate the list of SET pulse: SET GP 2. For each generated pulse p (SET GP ) 2. For each sensitive node i (SN) Apply pulse p to i Find destination node dn (SN, i) 3. For each dn Propagate p on (i, dn) 24

25 SETA algorithm The voltage array p is propagated through the logic element G1 to the next destination node G2 The propagation is computed on the basis of the crossing-pipb Propagation is performed assuming no-logic masking [actual version of SETA] P G1 is propagated in P G2 Output Pulse Width (x) = Input Pulse Width (x) x K(x) broadening FF1 G1 G2 FF4 25

26 Experimental results The SETA tool has been developed in a prototypal version about 12, lines of C/C++ code Microsemi Actel ProASIC3 13 nm logic gate library Experimental analysis performed on an 851 and on ITC 99 benchmark circuits SETs have been generated with very narrow length 14 types of SET pulses ranging from 2ps to 1ns 26

27 Circuit characteristics Circuit Name Device Type Sensitive Nodes [#] FFs [#] Propagation Path [#] SETA elaboration time [min] B4 A3P , B5 A3P ,82 12 B12 A3P ,717 4 B13 A3P A3P1 3, ,772,

28 SETA analysis data Circuit Name SET pulses evaluated [#] SET pulse masked [#] SET pulse observed [#] SET pulse observed [%] B4 6,92 6, B5 5,81 5, B12 7,91 7, B13 2,268 2, ,796 47,

29 Average broadening Average broadening increases proportionally with the circuit complexity (number of propagation paths) Actel Microsemi A3P ProAsic family delay threshold is around 44 ps Very narrow SETs are intrinsically filtered by the device delay threshold 29

30 SET occurrences Narrow SETs may elongate up to 8 ns 3

31 Results validation Results have been validated through electrical fault injection Selective injection of SET pulses SETs counted by a sampler circuit on a Virtex-5 FPGA Injection is performed instrumenting the circuits 31

32 Results validation Results have been validated through electrical fault injection propagated pulse [ns] Electrical Injection Point input transient pulse [ns] 32

33 Conclusions A CAD tool SETA is available and able to automatically evaluate the SET sensitivity of complex circuits Applied on Flash-based FPGAs Embedding the PIPB effect characterization The SETA tool allows to Investigate the behavior of individual FFs Selectively apply mitigation solutions (guard-gates, selective TMR, others ) 33

34 Future works Extend the SETA analysis to industrial level processor cores LEON3 microprocessor is under investigation Compare the SETA analysis with laser and radiation testing Embedding SETA results into P&R flow Extend the SETA flow to ASIC gate library 34

35 Thank you.. For your attention Question and comments: Luca Sterpone 35

36 Spare slide 36

37 Crossing-PIPB calculation The crossing-pipb is calculated on the basis of the following routing parameter τ= RC (sum of all the fan-out and fan-in contributions) Logic gates manhattan distance Size weight associated to destination gates Output Pulse Width (x) = Input Pulse Width (x) x K(x) broadening 37

38 Computing K broadening 38

39 SET sensitivity report: an example -- D FF[#] P S[ns] P D[ns] Broad[ns] Sens[%] Gain[%] -- 23(81,48) (7,4) (57,31) (69,1) (35,15) (6,36) (86,37) (82,3) FF id and position (X,Y) Destination SET Destination SET / Clock period Source SET Broadening % filtering gain 39