Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques.

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1 Introduction EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Techniques Cristian Grecu Course web site: What have you learned so far? To describe a circuit in VHDL and then map it to the FPGA What will we study today? Different IC design methodologies ASICs, FPGAs Techniques References Digital Integrated Circuits (2 nd Edition) Rabaey et. al. VHDL Programming (?) by Example, Douglas Perry Lecture 3, Page 2 Implementing Logic Circuits IC Landscape Digital Circuit Implementation Approaches M6 Standard Cells Compiled Cells Custom Cell-based Macro Cells Semicustom Gate Arrays Array-based FPGA's Cu via M contact (W) silicon via5 M5 via4 M4 via3 M3 via2 M2 Lecture 3, Page 3 Lecture 3, Page 4 Custom Approach Transition to Automation and use of Regularity Intel 4004 Intel 4004 ( 7) Intel 8080 Intel 8085 Lecture 3, Page 5 Intel 8286 Intel 8486 Lecture 3, Page 6 Lecture 3, Handouts Page

2 Standard Cell Design Implementing Logic Circuits Behavioral Library of cells that implement different gates Structural Cells can have different width but all cells have same height (hence Standard Cells) Feedthrough cell Logic cell HDL HDL Pre-Layout Pre-Layout Logic LogicSynthesis Synthesis Floorplanning Floorplanning Post-Layout Post-Layout Circuit CircuitExtraction Extraction Cells are placed on rows on SI substrate Physical channel Rows of cells Design Iteration Design Capture Functional module (RAM, multiplier, ) Many variants of the same cell (small NAND, big NAND, bigger NAND, etc.) Tape-out Lecture 3, Page 7 Standard Cell Design Standard Cell Design: An Example Logic Synthesis Transform the HDL description into library cells Connect the placed cells. Feedthrough cell Logic cell channel Rows of cells Where to place a cell? Lecture 3, Page 8 Functional module (RAM, multiplier, ) Lecture 3, Page 9 Standard Cell Design Lecture 3, Page 0 Standard Cell Design: New Generation channel can be narrowed if more interconnect layers are available Rows of cells Feedthrough cell Logic cell channel Functional module (RAM, multiplier, ) Cell-structure hidden under interconnect layers Lecture 3, Page Lecture 3, Page 2 Lecture 3, Handouts Page 2

3 Standard Cell Design: Summary Used only for the high-speed or low-power applications Very expensive, and time consuming (> $2M just for the mask costs) Very high re-spin cost More economic than full custom FPGAs and CPLDs: FPGA: Field-Programmable Gate Array CPLD: Complex Programmable Logic Device With a full custom chip: Circuit Description Expensive Chip Manufacturing Gate Array Lecture 3, Page 3 Lecture 3, Page 4 FPGAs and CPLDs: Field-Programmable Gate Array (FPGA): can implement almost any digital circuit instantly just by reprogramming the FPGA! Circuit Description Advantages of FPGAs:. "Instant Manufacturability": reduces time to market 2. Cheaper for small volumes because you don t need to pay for fabrication - means you don t need to be a big company to make a chip 3. Relaxes Designers -> relaxed designers live longer! FPGA Configuration Program FPGA Lecture 3, Page 5 Disadvantages of FPGAs:. Slower than custom or standard cell based chips 2. Can not get as much circuitry on a single chip Today: ~ M gates is the best you can do ~ 200 MHz is about as fast as you can get 3. For large volumes, it can be more expensive than gate arrays and custom chips 4. Dissipates more power Important Thing to Remember: The FPGA does not execute the VHDL. It implements the gates. Lecture 3, Handouts Page 3

4 What is inside an FPGA? What s Inside an FPGA? Do we care? The tools shield us pretty well from the internals. But, it helps to understand what is going on under-the-hood: You can better optimize your design if you understand how it is being implemented (smaller, faster, less power more $$$) It can be helpful during debugging Important to understand how an FPGA is built when you are selecting an FPGA for a project Lecture 3, Page 9 Lecture 3, Page 20 What s Inside an FPGA? What s Inside an FPGA? Logic Blocks - used to implement logic - lookup tables and flip-flops I/O Blocks - interface off-chip - can usually support many I/O Standards Altera: LABs Xilinx: CLBs Lecture 3, Page 2 Lecture 3, Page 22 What s Inside an FPGA? Logic Block Connection Block Switch Block Track (Horizontal) Logic Blocks implement functionality of the circuit { Channel (Vertical) TILE Lecture 3, Page 23 Lecture 3, Handouts Page 4

5 Logic Block: Basic Logic Gate: Lookup-Table Inputs Bit-Stream Logic Block: Quick Question: What function would this implement? A B C 0 Function of each lookup table can be configured by shifting in bit-stream. F = A + B + C Lecture 3, Page 25 Lecture 3, Page 26 Logic Block: Xilinx Virtex II Logic Block Basic Logic Gate: Lookup-Table Inputs SOPIN SHIFTIN COUT SOPOUT YB D Q G4 G3 G2 G WG4 WG3 WG2 WG ALTDIG LUT/ RAM/ ROM SHIFTOUT Flip-Flop/ Latch Y DY Q CE CLK BY Function of each lookup table can be configured by shifting in bit-stream. X 2 CIN SR DIG Lecture 3, Page 27 Lecture 3, Page 28 Xilinx Virtex II Logic Block Stratix II Logic Block: SHIFTIN COUT SOPOUT SOPIN YB G4 G3 G2 G WG4 WG3 WG2 WG ALTDIG LUT/ RAM/ ROM SHIFTOUT Flip-Flop/ Latch Y DY Q CE CLK BY CIN SR DIG X 2 Lecture 3, Page 29 Lecture 3, Page 30 Source: Stratix II Handbook, 2005 Lecture 3, Handouts Page 5

6 Logic Clusters Several lookup tables are grouped into clusters Logic Blocks are grouped into Clusters Local Interconnect DQ DQ - Typically 8 to 0 lookup tables per cluster Connections between lookup tables in the same cluster are fast Connections between lookup tables in different clusters are slow DQ Lecture 3, Page 32 What s Inside an FPGA? Fabric Lecture 3, Page 34 Reconfigurable Logic: Reconfigurable Logic: Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches Lecture 3, Page 35 Lecture 3, Page 36 Lecture 3, Handouts Page 6

7 Switch Blocks Switch Blocks: Most of the FPGA area is due to routing - Fixed metal tracks arranged in horizontal and vertical channels - Connected to each other using switch blocks Switch Blocks connect horizontal and vertical channels Every possible connection? - Too big - Too slow Lecture 3, Page 37 Lecture 3, Page 38 Switch Blocks: Wiring Segments Switch Blocks connect horizontal and vertical channels Every possible connection? - Too big - Too slow Many Topologies possible Medium-length segments Long Line Segments Single length segments Short segments are good for local connections Long segments are good for global connections Most FPGA s have a variety of segment lengths Lecture 3, Page 39 Lecture 3, Page 40 Segmented Architecture At each switch block: some tracks end some tracks pass right through LB LB LB LB LB LB LB LB LB LB Segment Lengths Typically, an FPGA contains a mix of segment lengths: - Some wires that span only one logic block - Some wires that span more than one logic block - Some wires that span the whole chip If a segment is too short, must traverse many segments to reach your destination If a segment is too long, waste routing capacity, extra capacitance LB LB LB LB LB Lecture 3, Page 4 Lecture 3, Page 42 Lecture 3, Handouts Page 7

8 Implementing Logic Circuits Two types of :. Behaviour (simulates VHDL directly) 2. Timing (simulates gates) Timing simulation is more accurate, but behavioural simulation is faster Design Iteration Pre-Layout Post-Layout Design Capture HDL HDL Logic Logic Synthesis Floorplanning Behavioral Structural Physical Circuit Circuit Extraction Tape-out Lecture 3, Page 43 Lecture 3, Page 44 Implementing Systems in an FPGA: Systems FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-8K) Lecture 3, Page 46 Implementing Systems in an FPGA: Implementing Systems in an FPGA: FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-8K) Multiplier Blocks FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-8K) Multiplier Blocks High-Speed I/Os Lecture 3, Page 47 Lecture 3, Page 48 Lecture 3, Handouts Page 8

9 Implementing Systems in an FPGA: Implementing Systems in an FPGA FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-8K) Multiplier Blocks High-Speed I/Os Dedicated Clock Circuitry FPGA vendors embed fixed blocks to improve speed and density: Embedded Memories (blocks of 2K-8K) Multiplier Blocks High-Speed I/Os Dedicated Clock Circuitry CPU (eg. ARM,MIPS) Lecture 3, Page 49 Lecture 3, Page 50 Implementing Systems in an FPGA FPGA Fabric FPGA based design: Summary Two Sources of Flexibility in an FPGA: Embedded PowerPC Embedded memories Hardwired multipliers Xilinx Vertex-II Pro. Most FPGAs use Lookup-Tables as their basic logic resource - 4-LUT can implement any function of 4 inputs 2. Connections between logic blocks can be made using fixed metal tracks - these fixed tracks are connected to each other and to the logic blocks using programmable switches High-speed I/O Lecture 3, Page 5 Lecture 3, Page 52 of Logic Circuits of Logic Circuits Design Capture Behavioral Design Capture Behavioral Design Iteration Pre-Layout Post-Layout HDL HDL Logic Logic Synthesis Floorplanning Structural Physical Design Iteration Pre-Layout Post-Layout HDL HDL Logic Logic Synthesis Floorplanning Structural Physical Circuit Circuit Extraction Circuit Circuit Extraction Tape-out Tape-out Lecture 3, Page 53 Lecture 3, Page 54 Lecture 3, Handouts Page 9

10 of Logic Circuits Purpose -To check that the circuit produces the desired output What you have been doing so far? - Provide the inputs through a vector waveform file and then monitor outputs visually Disadvantages - Can only test the circuit for very limited cases - Time consuming - Exhaustive testing not possible What is usually done? - Use a Testbench to generate inputs and then verify the outputs Testbenches - Highest level in the design hierarchy - Instantiate the design under test (DUT) - Provides the input stimulus to DUT, which responds to it and generates the outputs - Some sort of comparison with some known results - Any VHDL construct can be used - VHDL Simulators - NCSim from Cadence - ModelSim from Mentor Graphics Top Level Stimulus Design Driver Under Test Lecture 3, Page 55 Lecture 3, Page 56 Testbenches Testbenches: Example -Stimulus only - Full Testbench Testbench Stimulus Driver DUT - Testbench for an Adder - Test cases specified in a text file - Inputs and Expected Outputs - Simulator Specific - Hybrid OK Errors - Note: Quartus does not support these kind of testbenches. Waveforms only! Known Results Lecture 3, Page 57 Lecture 3, Page 58 Testbenches: non-synthesizeable VHDL Summary wait until (clk event and clk= ) a <= b and c after 2 ns; for I in to 500 loop out(i):=out(i)+; end loop; Top Level Stimulus Design Driver Under Test - Implementation Approaches for Logic Circuits - Standard cell ASICs - FPGAs - Simulating Logic Circuits - How to setup testbenches? - Example testbench for an adder These statements cannot appear in the DUT Lecture 3, Page 59 Lecture 3, Page 60 Lecture 3, Handouts Page 0