Design Considerations for CMOS Digital Circuits with Improved Hot-Carrier Reliability

Transcription

1 1014 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996 Design Considerations for CMOS Digital Circuits with Improved Hot-Carrier Reliability Yusuf Leblebici, Member, IEEE Abstract The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nmos and pmos transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F ) and the transistor aspect ratio (r) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability. I. INTRODUCTION ADVANCES in CMOS very large scale integration (VLSI) fabrication technologies are primarily based on the reduction of device dimensions, such as the channel length, the junction depth, and the gate oxide thickness, without a proportional scaling of the power supply voltage. This decrease in critical device dimensions to submicron ranges, accompanied by increasing substrate doping densities, results in a significant increase of the horizontal and vertical electric fields in the channel region of MOS transistors. Electrons and holes gaining high kinetic energies in the electric field (hot-carriers) may be injected into the gate oxide and cause permanent changes in the oxide-interface charge distribution, hence degrading the current-voltage characteristics of the MOSFET [1], [2]. Since the likelihood of hot-carrier induced degradation increases with shrinking device dimensions, this problem was identified as one of the important factors that may impose strict limitations on maximum achievable device densities in VLSI circuits [3], [4]. The concept of gradual circuit performance degradation as a result of device aging must be carefully investigated in order to assess the true impact of hot-carrier effects. One of the problems encountered in assessing gradual degradation is the correct identification of failure. A simplistic approach would be to set specific limits for all device parameter variations Manuscript received October 23, 1995; revised February 9, This work was supported in part by the Turkish Scientific and Technological Research Council under the research Grant EEEAG-135. Theauthor iswiththedepartment ofelectrical andelectronics Engineering, Istanbul Technical University, Maslak, Istanbul, Turkey. Publisher Item Identifier S (96) and to declare a device failure if the parameter values of that device shift beyond the preset limits as a result of aging. But this approach has some drawbacks regarding the assessment of circuit performance. If a particular transistor has negligible influence upon the circuit performance characteristics, even larger parameter variations may be tolerable. On the other hand, a small variation of parameter values may have significant impact upon circuit performance, if that transistor has a large influence on performance characteristics. Therefore, the correct assessment of circuit failure must involve the joint evaluation of device-level degradation and its effects upon circuit performance. Most of the previous efforts to evaluate device and circuit degradation have focused on using circuit-level simulation tools such as some modified variants of SPICE and SPICElike simulators [5] [7]. These reliability simulation tools can be used to assess and to evaluate long-term circuit degradation and to improve the reliability by incremental design modifications. However, there is a growing need for topologybased and geometry-based design rules for improved reliability that can be readily applied in the early stages of circuit design. Rigorous application of such guidelines will become essential for reliable design of submicron CMOS structures. A simple parametric macro-modeling approach for the estimation of device degradation based on device geometries was given in [8]. In this paper, the parametric macro-model for reliability estimation is extended to include parasitic gate-drain overlap capacitances and the effects of the resulting drain voltage overshoots. Also, a reliability measure is presented for estimating the transient performance degradation in CMOS digital circuits. It is believed to be a more realistic indicator of circuit reliability than the simplistic device (current) degradation estimates, which were the focus of most previous efforts. The results obtained in the following are also applied to the optimization of cascaded CMOS digital circuits, and especially, of tapered (scaled) inverter-chain structures. It is shown that conventional design strategies for tapered structures may need to be modified in order to achieve a higher reliability. A number of simple design rules and guidelines based on device geometries, circuit topology, and power supply voltage are presented to improve hot-carrier related reliability in CMOS digital circuits. II. HOT-CARRIER INDUCED DEVICE DEGRADATION IN CMOS INVERTERS The hot-carrier induced degradation of MOS transistors is caused by the injection of high-energy electrons and holes /96$ IEEE

2 LEBLEBICI: DESIGN CONSIDERATIONS FOR CMOS DIGITAL CIRCUITS WITH IMPROVED HOT-CARRIER RELIABILITY 1015 Fig. 1. Typical input output voltage waveforms of a CMOS inverter and the bond-breaking current of the nmos transistor, without gate-drain parasitics (dashed lines) and with a gate-drain parasitic capacitance of C g =0:2C L (solid lines). The output voltage overshoot caused by the gate-drain significantly increases the hot-carrier damage. into the gate oxide region near the drain. The damage is in the form of localized oxide charge trapping and/or interface trap generation, which gradually builds up and permanently changes the oxide-interface charge distribution. In digital logic circuits, the degradation of the MOS current-voltage characteristics is attributed primarily to the generation of interface traps near the drain [7], [9]. The time-dependent increase of the interface trap density can be described as a simple function of the average bond-breaking current density over one period [5], [6]. The bond-breaking current density is defined as, where and represent the drain current and the substrate current, respectively, and represents the channel width of the MOS transistor. Since the amount of generated interface trap density is a direct indication of the hot-carrier damage experienced by the MOS transistor, the average bond-breaking current density over one period provides an accurate measure of the dynamic device degradation. The relatively less significant degradation of MOS transistors will be neglected in the following. The extent of the hot-carrier damage that each MOS transistor experiences during dynamic circuit operation is determined primarily by its terminal voltage waveforms, and it is influenced by such parameters as gate voltage rise time, drain voltage fall time, channel length, channel width, and input signal frequency. It can be shown that in a CMOS inverter driven by a ramp input, hot-carrier induced degradation occurs predominantly during the rising-input transient, when the MOS transistor operates in saturation (Fig. 1). In the presence of parasitic gate-drain overlap capacitances, the output (drain) voltage exhibits an overshoot behavior which further increases the amount of hot-carrier induced degradation [9]. In the following analysis, represents the lumped output capacitance of the CMOS inverter excluding gate-drain parasitics, and represents the total parasitic gate-drain Fig. 2. Normalized degradation of the nmos transistor in a CMOS inverter circuit, as a function of the input signal slope and the (W n=c L ) ratio. overlap capacitance associated with both MOS and MOS transistors. The input voltage is assumed to be a ramp function, described as, where the input signal slope is. As the output load capacitance is discharged through the MOS transistor, that transistor initially operates in saturation Here, is a function of the channel electron mobility, the gate oxide thickness, and the channel length. Hence Substituting (2) in the drain and substrate current expressions, the bond-breaking current density of the inverter MOS (1) (2)

3 1016 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996 Fig. 3. The degradation surface associated with the nmos transistor in a CMOS inverter circuit, as a function of the input signal slope and the (W n=c L ) ratio. transistor is obtained as a function of time, as follows: where and represent process-dependent constants. Assuming that all other parameters are constants (for simple comparison purposes), the average bond-breaking current density over one period can be found as a function of four circuit parameters, i.e., the input signal slope, the power supply voltage, the ratio, and the ratio (4) It should be noted that two of these parameters, and, can be viewed as locally designable circuit parameters, whereas can be used as a global design parameter to achieve better reliability. The capacitance ratio cannot be used as a design parameter. However, its strong influence upon degradation characteristics should be taken into account in the estimates. Fig. 2 shows the expected degradation of the MOS transistor in a CMOS inverter as (3) a function of the two locally designable parameters, at a constant power supply voltage of 5 V and for.it can be seen that device degradation decreases with increasing input signal slope (because the MOS transistor gets out of deep saturation faster), and with increasing ratio. It is also seen that the influence of the input signal slope upon degradation is stronger than that of, by about a factor of five. This means that the relative increase in, which is necessary for reducing the degradation by a certain amount, is about five times as large as the relative increase in the input slope to achieve the same reduction. The strong influence of input signal slope on degradation was also reported earlier by Weber et al. [9] as one of the results of dynamic degradation experiments. Fig. 3 depicts the normalized degradation of the inverter MOS transistor as a function of the input signal slope and the ratio, in the form of a degradation surface. Again, the power supply voltage is assumed to be 5 V, and. The relative influences of the two designable parameters upon device degradation are clearly visible in this representation. By obtaining vertical cross-sections of this surface at certain degradation levels and projecting the cutlines on the horizontal plane, one can generate a set of design curves in the parameter space, as shown in Fig. 4. Here, each curve corresponds to a constant level of device degradation. Thus, Fig. 4 can be used to determine and to optimize the limit values of the two design parameters, and, which satisfy a given (maximum) target value for hot-carrier induced device degradation. The input signal slope is primarily determined by the current drive capability of the pull-up devices in the preceding stage. Hence, special attention must be given to the design of pull-

4 LEBLEBICI: DESIGN CONSIDERATIONS FOR CMOS DIGITAL CIRCUITS WITH IMPROVED HOT-CARRIER RELIABILITY 1017 Fig. 4. Design curves for the CMOS inverter, obtained as a function of the input signal slope and the (W n=c L ) ratio. Each curve corresponds to a constant (normalized) level of nmos device degradation. up ( MOS) transistors in the driving stage for improving the hot-carrier reliability of CMOS inverters and logic gates. Circuits which are driven by stronger pull-up stages (i.e., larger ratios) experience significantly less stress. In a system consisting of cascaded stages with known capacitive loads, one may increase the ratios of both the MOS and the MOS transistors to improve the overall reliability. If the available area is limited, however, increasing the MOS transistor widths only will still provide a significant improvement of reliability. The parametric expression (3) also shows the strong influence of the capacitance ratio upon the degradation characteristics of the CMOS inverter. As shown in Fig. 1 above, the presence of the parasitic gate-drain capacitance results in a significant output voltage overshoot which increases the amount of bond-breaking current in the MOS transistor. Fig. 5 shows the amount of expected degradation level for the MOS transistor as a function of the input signal slope and the ratio. For larger ratios, the hot-carrier induced degradation is seen to increase considerably, which is in agreement with previously reported experimental results [9]. While the gate-drain parasitics enhance the dynamic aging of the MOS transistor, the relative dependence of degradation on the two locally designable parameters, and, is not essentially influenced by the presence of these parasitics. Consequently, the observations made above for still preserve their validity for nonzero values. Finally, the parametric expression given in (3) can be used to analytically assess the influence of the power supply voltage upon the hot-carrier induced degradation in a CMOS inverter circuit. It is quite obvious with simple inspection Fig. 5. Normalized degradation of the nmos transistor in a CMOS inverter circuit, as a function of the input signal slope and the (C g=c L ) ratio. Large gate-drain parasitics increase the amount of hot-carrier degradation. of (3) that the amount of degradation increases dramatically with, which leads to the conclusion that reducing the power supply voltage will improve hot-carrier reliability. In general, such a reduction involves careful consideration of various performance and reliability aspects, such as switching speed, interfacing, and noise immunity, and it may not be a trivial task in most cases. Fig. 6 shows the variation of the normalized degradation of the MOS transistor in a CMOS inverter, as a function of the power supply voltage and the input signal slope, which was identified above as the strong local design parameter. The very dominant influence of the

5 1018 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996 Fig. 6. The degradation surface associated with the nmos transistor in a CMOS inverter circuit, as a function of the input signal slope and the power supply voltage. Fig. 7. Design curves for the CMOS inverter, obtained as a function of the input signal slope and the power supply voltage. Each curve corresponds to a constant (normalized) level of nmos device degradation. supply voltage upon hot-carrier induced degradation is clearly visible. Even a small reduction of the power supply voltage can significantly lower the amount of device degradation. The nearly-exponential dependence of device aging on also suggests that the relative significance of hot-carrier induced degradation will diminish as the power supply voltage is dropped below the 2 V-range. Fig. 7 shows a set of design curves in the parameter space, which are again obtained by generating vertical cross-sections of the degradation surface at certain constant levels, and by projecting the cutlines on the horizontal plane. Hence, Fig. 7 can be used to optimize the global design parameter and the local design parameter to meet given target values for hot-carrier reliability.

6 LEBLEBICI: DESIGN CONSIDERATIONS FOR CMOS DIGITAL CIRCUITS WITH IMPROVED HOT-CARRIER RELIABILITY 1019 Fig. 9. Expected degradation of the CMOS inverter propagation delay time and the output fall time as a function of drain current degradation. step-input voltage. The transient behavior of the output voltage can be analyzed by calculating the discharge time of the inverter output capacitance through the conducting MOS transistor. Notice that the MOS transistor is initially operating in the saturation region. As the output voltage begins to fall, the transistor switches from saturation into linear operating region. The time required for the output voltage to fall from its initial value to the midpoint voltage level V can be found by using the well-known delay model [10], [11] as Fig. 8. Definitions of the propagation delay time and the output voltage fall time. Note that the nmos transistor operates longer in the linear region during fall time (shaded region), where the drain current degradation is more pronounced. III. DEGRADATION OF TRANSIENT PERFORMANCE In an MOS transistor experiencing hot-carrier induced degradation, the linear region drain current exhibits a much more pronounced decrease than the saturation region current [2]. The amount of current degradation in the linear operating region can be shown to be proportional to the generated interface trap density near the drain For simplicity, this current degradation can be attributed to a proportional decrease in the MOS transconductance as follows, where represents an empirical proportionality factor In the saturation region, on the other hand, the current degradation will be assumed to be negligible. This assumption greatly simplifies the analysis of transient performance degradation in CMOS inverter circuits while preserving the accuracy of the degradation model. The transient performance of the CMOS inverter circuit subject to hot-carrier degradation will be examined in the following. Consider the CMOS inverter circuit with a rising (5) (6) It can be seen that during the output voltage transition described by (7), the MOS transistor operates in the linear operating mode only for a relatively short amount of time. Consequently, the impact of current degradation in the linear operating region upon the propagation delay time is limited. In contrast, consider the output voltage fall time for the same CMOS inverter, under the same initial conditions. Since the MOS transistor operates for a longer time segment in the linear region while the output voltage falls from the 90%-point to the 10%-point, the impact of hot-carrier degradation upon the fall time is expected to be more extensive The definitions of the propagation delay time and the output voltage fall time are shown in Fig. 8 for comparison purposes. In both cases, the degradation (increase) of the delay time can be expressed as a function of the linear-region (7) (8)

7 1020 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996 Fig. 10. A tapered (scaled) inverter chain. Fig. 11. Degradation of nmos transistors in the scaled inverter chain circuit as a function of F (scaling factor) and r (transistor aspect ratio). capacitive loads with an acceptable propagation delay. The first-stage inverter is built with minimum-sized transistors, and each consecutive inverter stage is built with transistors having -ratios timeslarger thanthoseofthepreviousstage transistors (Fig. 10). Assuming that the output load capacitance of each stage is primarily determined by the input (gate) capacitance of the next stage, it can be shown that the propagation delay times of all inverter stages are identical. The overall propagation delay of the scaled buffer is usually optimized by calculating the scaling factor, for which the propagation delay achieves its minimum [10], [11], [13]. The degradation macro-model presented in Section II for the simple CMOS inverter circuit can now be applied to the scaled inverter-chain structure. To accomplish this, the two design parameters identified earlier as being representative for the degradation of the CMOS inverter, namely the - ratio and the input signal slope, must be expressed in terms of the scaling factor. First, consider the -ratio of the th inverter stage. This ratio is expressed as [14] current degradation as where the dimensionless coefficient is typically between for propagation delay time, and between for output voltage fall time, depending on the exact value of the MOS threshold voltage. Fig. 9 shows the expected degradation of the CMOS inverter propagation delay time and the fall time as a function of drain current degradation. As explained in Section I, the transient performance degradation represents a realistic measure of circuit reliability under dynamic operating conditions. The relationship between the device current degradation and the transient performance degradation given in (9) is a more accurate model compared to the simple linear relationship used in [12], and it takes into account the different degradation rates for propagation delay and fall time. IV. DESIGN GUIDELINES FOR TAPERED (SCALED) BUFFER CIRCUITS The tapered buffer structure consisting of a scaled inverterchain is typically used for driving large on-chip and off-chip (9) (10) where represents the scaling factor and represents the aspect ratio of the MOS and MOS transistors. Notice that the -ratio is identical for all stages in the buffer chain. Now consider the rising input signal slope for the th inverter stage. It can be shown that the slope is proportional to the -ratio of the previous stage, i.e., (11) As for the -ratio, the input signal slope is also identical for all stages in the buffer chain. Consequently, it is expected that all stages in the buffer chain experience the same amount of hot-carrier induced degradation. Substituting (10) and (11) in (3), we obtain the hot-carrier degradation of each stage as a function of the scaling factor and the aspect ratio. Fig. 11 shows the variation of the normalized device degradation level as a function of and. It is seen that the degradation experienced by each inverter stage increases almost linearly with the scaling factor. Since the propagation delay is not a strong function of the scaling factor

8 LEBLEBICI: DESIGN CONSIDERATIONS FOR CMOS DIGITAL CIRCUITS WITH IMPROVED HOT-CARRIER RELIABILITY 1021 Fig. 12. Degradation of nmos transistor in the scaled inverter chain circuit as a function of F (scaling factor) and the power supply voltage V DD. Fig. 13. Design curves for the scaled inverter chain, obtained as a function of scaling factor F and the power supply voltage. Each curve corresponds to a constant (normalized) level of nmos device degradation., the conventional design approach for scaled buffer chains would allow a relatively high, i.e., a smaller number of stages, as a feasible solution in most cases [10], [11]. The linear dependence of degradation on, however, dictates that the buffer chain be designed with the lowest possible scaling factor which achieves the desired propagation delay. Thus, an inverter chain with a smaller scaling factor and with a larger number of stages is expected to have better reliability than an inverter chain with a larger scaling factor and a smaller number of stages to drive the same amount of output load [13], [14]. Also, small aspect ratios (especially, ) appear to have a very strong influence upon device degradation, whereas larger aspect ratios have almost no significant effect. The reason for this behavior is that the

9 1022 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996 Fig. 14. Some circuit-level design-for-reliability guidelines. input signal slope, which is determined by the MOS transistor size, drops sharply for smaller aspect ratios and thus, causes more pronounced device degradation. Hence, device aspect ratios smaller than unity should be avoided in order to reduce the amount of hot-carrier related degradation in scaled buffer stages. Fig. 12 shows the variation of the normalized degradation of the MOS transistor in any stage of the scaled inverter chain as a function of the power supply voltage and the scaling factor. Again, the supply voltage is seen to have a very dominant influence upon hot-carrier induced degradation, whereas the dependence of degradation on the scaling factor is nearly linear. Even a small reduction of the power supply voltage can thus allow the buffer chain to be designed with a larger scaling factor, and consequently, with a smaller number of stages to drive the same amount of load, without violating preset target values for hot-carrier induced device degradation. Fig. 13 shows a set of design curves in the -space, which can be used to optimize the global design parameter and the local design parameter, to meet given target values for hot-carrier reliability. V. GENERAL GUIDELINES FOR RELIABILITY In digital CMOS circuits, hot-carrier induced degradation of MOS and MOS devices occurs almost exclusively during switching transients, i.e., when the input and output voltage waveforms undergo low-to-high or high-to-low transitions. Therefore, the number of switching events that a particular device (or subcircuit) experiences in a given time period determines the actual degradation level. A very fundamental measure to improve overall reliability would be to reduce the number of switching events required to perform any given operation. Since a trivial solution, such as limiting the clock frequency, would severely impact the system performance, one may explore novel logic design strategies to achieve that objective without restricting performance. It is instructive to point out that some of the circuit design strategies suggested here for improving the overall reliability are also compatible with the design strategies implemented for low power dissipation. The results presented in Sections II and III indicate that the performance degradation becomes significantly smaller with shorter input rise times (larger signal slopes), since in this case, the MOS transistor leaves the saturation region faster. A larger ratio also tends to reduce the dynamic degradation experienced by the inverter, but the influence of the signal slope upon degradation is far stronger. Since the input signal slope is primarily determined by the current drive capability of the pull-up devices in the preceding stage, special attention must be given to the design of pull-up ( MOS) transistors in the driving stage for improving the hot-carrier

10 LEBLEBICI: DESIGN CONSIDERATIONS FOR CMOS DIGITAL CIRCUITS WITH IMPROVED HOT-CARRIER RELIABILITY 1023 reliability of CMOS inverters and logic gates. Circuits which are driven by stronger pull-up stages (i.e., larger ratios) experience significantly less hot-carrier stress. In CMOS NAND gates where the MOS transistors are connected in series between the output node and the ground, only the MOS transistor located nearest to the output node temporarily operates in deep saturation while the output load capacitance is being discharged. Also, the drain-to-source voltage of this uppermost transistor always remains less than the power supply voltage. Detailed analysis of the switching characteristics of NAND gates has shown that the amount of hot-carrier induced damage in the uppermost MOS transistor can be further reduced if the rising input signal of this transistor arrives earlier than the other inputs [7]. On the other hand, in CMOS NOR gates where the MOS transistors are connected in parallel between the output node and the ground, any one of the MOS transistors can enter deep saturation, depending on the relative arrival times of the rising input signals. Moreover, the drain-to-source voltages of all MOS transistors in a NOR gate are equal to the output voltage. These observations lead to the conclusion that the MOS transistors in a NAND gate are less susceptible to hot-carrier induced degradation during switching transients compared to the transistors in a NOR gate. Consequently, a NAND-based logic design approach can be recommended for better hotcarrier reliability. The advantage of drain voltage reduction in seriesconnected MOS transistors can be further exploited. In complex logic circuits, the hot-carrier induced degradation levels experienced by the MOS transistors are reduced significantly by inserting a normally-on MOS transistor between the output node and the MOS-block. Since the drain-to-source voltage drop across this dummy device absorbs a significant percentage of the total output node voltage, the hot-carrier constraints on the other switching transistors in the circuit can be relaxed. Fig. 14 shows some of the circuit-level reliability measures discussed here [15]. VI. CONCLUSION In this paper, a parametric reliability measure has been presented for estimating the transient performance degradation in CMOS digital circuits. Delay-time degradation is shown to be a more realistic indicator of circuit reliability than the simplistic device (current) degradation estimates, which were the focus of most previous efforts. For a wide class of circuits, the performance degradation due to dynamic hot-carrier effects has been expressed as a function of the MOS and MOS transistor channel widths, and the output load capacitance. Most significantly, it has been shown that the ratios of MOS transistors have a more pronounced impact upon circuit reliability, while the ratios of MOS transistors have marginal influence. This result supports the notion that circuits which are driven by stronger pull-up stages (i.e., larger MOS transistors) experience significantly lower hot-carrier stress. Hence, special attention must be given to the design of MOS pull-up transistors in the driving stage for improving the hot-carrier reliability of CMOS logic gates. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics has been investigated. Systematic guidelines for the reliable design of CMOS inverter circuits have been devised in terms of simple design curves, which delineate the influence of basic design parameters upon device aging. The parametric model developed here has also been used to analytically assess the influence of the power supply voltage upon the hot-carrier induced degradation in a CMOS inverter circuit. The results are applied to the optimization of cascaded inverter-chain structures, and other CMOS digital circuit structures with respect to reliability and dynamic performance. It has been shown that conventional circuit design and tapering strategies may need to be modified in order to achieve better reliability in such circuits. A number of simple design rules and guidelines based on device geometries and circuit topology were also presented to improve the long-term reliability with respect to hot-carrier induced aging effects. ACKNOWLEDGMENT The author thanks H. Öner for his extensive and invaluable help during the preparation of the manuscript. REFERENCES [1] C. Hu, S. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, Hot-electron-induced MOSFET degradation Model, monitor and improvement, IEEE Trans. Electron Devices, vol. ED-32, pp , Feb [2] A. Schwerin, W. Haensch, and W. Weber, The relationship between oxide charge and device degradation: A comparative study of n- and p-channel MOSFET s, IEEE Trans. Electron Devices, vol. ED-34, pp , Dec [3] C. Hu, Reliability issues of MOS and bipolar IC s, in Proc IEEE Int. Conf. Comput. Design, Oct, 1989, pp [4] J. E. Chung, M. C. Jeng, J. E. Moon, P. K. Ko, and C. Hu, Performance and reliability design issues for deep-submicrometer MOSFET s, IEEE Trans. Electron Devices, vol. 38, pp , Mar [5] P. M. Lee, M. M. Kuo, K. Seki, P. K. Ko, and C. Hu, Circuit aging simulator (CAS), in Proc IEEE Int. Electron Devices Meeting, Dec. 1988, pp [6] B. J. Sheu, W.-J. Hsu, and B. W. Lee, An integrated-circuit reliability simulator RELY, IEEE J. Solid-State Circuits, vol. 24, pp , Apr [7] Y. Leblebici and S. M. Kang, Modeling and simulation of hot-carrier induced device degradation in MOS circuits, IEEE J. Solid-State Circuits, vol. 28, pp , May [8] Y. Leblebici, W. Sun, and S. M. Kang, Parametric macro-modeling of hot-carrier induced dynamic degradation in MOS VLSI circuits, IEEE Trans. Electron Devices, vol. 40, pp , Mar [9] W. Weber, M. Brox, T. Kuenemund, H. M. Muehlhoff, and D. Schmitt- Landsiedel, Dynamic degradation in MOSFET s Part II: Application in the circuit environment, IEEE Trans. Electron Devices, vol. 38, pp , Aug [10] S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design. New York: McGraw-Hill, [11] N. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, [12] K. N. Quader, E. R. Minami, W.-J. Huang, P. K. Ko, and C. Hu, Hotcarrier-reliability design guidelines for CMOS logic circuits, IEEE J. Solid-State Circuits, vol. 29, pp , Mar [13] B. S. Cherkauer and E. G. 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11 1024 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996 Yusuf Leblebici (S 88 M 91) received the B.S. and M.S. degrees in electrical engineering from Istanbul Technical University, Maslak, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in From 1991 to 1993, he worked as a Visiting Assistant Professor of Electrical and Computer Engineering and Visiting Research Assistant Professor of Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. In 1993 he joined the faculty of Istanbul Technical University as an Associate Professor of Electrical Engineering. He also works as a Senior Designer and Project Manager at ETA ASIC Design Center, Istanbul. He is co-author of two books, Hot-Carrier Reliability of MOS VLSI Circuits (Kluwer, 1993) and CMOS Digital Integrated Circuits: Analysis and Design (McGraw-Hill, 1996). His research interests include modeling and simulation of semiconductor devices, computer-aided design of VLSI circuits, and VLSI reliability analysis. Dr. Leblebici served on the organizing committee of the 1995 European Conference on Circuit Theory and Design. He received a NATO Science Fellowship award in 1986, he has been an Honors Scholar of the Turkish Scientific and Technological Research Council in , and he received the Junior Scientist Award of the same council in 1995.