Low Power and High Speed Multi Threshold Voltage Interface Circuits Sherif A. Tawfik and Volkan Kursun, Member, IEEE

Transcription

1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Low Power and High Speed Multi Threshold Voltage Interface Circuits Sherif A. Tawfik and Volkan Kursun, Member, IEEE Abstract Employing multiple supply voltages (multi- DD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multithreshold voltage (multi- th) level converters are proposed in this paper. The new multi- th level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a m TSMC CMOS technology. Index Terms High-performance, multiple supply voltages, multiple threshold voltages, parameter variations, power efficiency, voltage level converters. I. INTRODUCTION T ECHNOLOGY scaling is the main thrust behind the advancement of CMOS technology. More and faster transistors are crammed onto integrated circuits with each new technology generation. The increased number of transistors and the enhanced clock frequency lead to a significant increase in the power consumption with each new technology generation. Furthermore, deviation from the constant field scaling due to the non-scaling parameters of the MOS transistors (the thermal voltage, the silicon energy band gap, and the source/drain doping levels) leads to an increase in the power density. The higher power dissipation coupled with the imbalanced utilization and the diversity of circuitry elevates the temperature and produces local hot-spots across a die [1], [3]. The increased power dissipation degrades the reliability, increases the cost of the packaging and cooling system, and lowers the battery lifetime in portable electronic devices. An effective method for reducing the power consumption is scaling the supply voltage. Dynamic, short-circuit, and leakage components of power consumption are simultaneously reduced with the scaling of the supply voltage in a CMOS circuit. Lowering the supply voltage, however, also degrades Manuscript received December 07, 2007; revised March 09, S. Tawfik is with the Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI USA ( tawfik@wisc.edu). V. Kursun is with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong. Digital Object Identifier /TVLSI the circuit speed. The multi- circuit technique exploits the delay differences among the different signal propagation paths within an integrated circuit (IC) [1], [5]. The supply voltages of the gates on the noncritical delay paths are selectively lowered while a higher supply voltage is maintained on the critical delay paths in order to satisfy a target clock frequency in a multicircuit. Similarly, in systems-on-chips (SoCs), different circuits operating at different supply voltages exist [11]. When a low voltage swing signal drives a CMOS gate connected to a higher supply voltage, static dc power is consumed as the transistors in the pull-up and the pull-down networks are simultaneously turned on [1]. Furthermore, the output voltage swing of the receiver degrades, thereby leading to a static dc current in the fan-out gates of the receiver. In order to transfer signals among these circuits operating at different voltage levels, specialized voltage interface circuits are required. Level converters impose additional power consumption and propagation delay overhead in a multi- system. High-speed and lowpower voltage interfacing is critical for effective power reduction with minimum effect on speed in a multi- IC. Several factors such as the path propagation delay statistics, the power and delay overhead of the level converters, and the availability and efficiency of the different power supplies determine the choice of the supply voltages in a multi- system [5] [10]. The number and the voltages of the multiple power supplies therefore vary with the type of the IC and the target set of applications. In this paper, a wide range of supply voltages are considered in order to address the speed, power, and area tradeoffs in the design of voltage level conversion circuits. The previously published level converters rely on some form of feedback circuitry for controlling the operation of the pull-up network transistors in order to avoid static dc current within the level converter. These circuits, however, suffer from significant amount of short-circuit current and degraded speed characteristics due to the typically slow response of the feedback circuitry. Furthermore, to achieve functionality with a very low voltage transmitter, transistor resizing (significant increase in the device widths) is required in these feedback-based level converters, thereby further increasing the power consumption and the propagation delay. In this paper, two novel level converters based on a multithreshold voltage CMOS technology are presented. Unlike the conventional level conversion techniques based on feedback, the proposed level converters eliminate the static dc current using multi- devices. The new level converters are compared with two previously published feedback-based level converters for different supply voltages. The effectiveness of the proposed circuits for reducing power consumption, propagation delay, and /$ IEEE

2 2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS area is evaluated at scaled supply voltages down to the subthreshold regime. The paper is organized as follows. The operation of the proposed level converters is described in Section II. The power consumption and the propagation delay characteristics of the level converters at the nominal process corner and under parameter variations are presented in Section III. Finally, some conclusions are provided in Section IV. II. LEVEL CONVERTERS In this section various level conversion techniques are described. The issues related to the standard feedback-based level converters are discussed in Section II-A. Two new level converters based on a multi- CMOS technology are presented in Section II-B. A. Feedback-Based Level Converters The conventional feedback-based level converters are discussed in this section. When a low swing signal directly drives a gate that is connected to a higher supply voltage, the pull-up network of the receiver cannot be fully turned off. A receiver driven by a low voltage swing signal therefore produces static dc current. In order to suppress this dc current, specialized voltage interface circuits are employed between a low voltage driver and a full voltage swing receiver [2], [4] [10]. In the standard feedback-based voltage interface circuits, the pull-up network transistors are not directly driven by the low voltage swing signal provided by the driver. The operation of the pull-up network transistors is controlled by an internal feedback mechanism isolated from the low voltage swing input signal, thereby avoiding the formation of static dc current paths within the circuit. These traditional level converters, however, suffer from high short-circuit power and long propagation delay due to the typically slow response of the internal feedback circuitry that controls the operation of the pull-up transistors. Furthermore, the pull-down network transistors in these circuits are driven by low voltage swing signals unlike the pull-up network transistors that receive higher gate overdrive voltages from the full-voltage swing feedback paths. Particularly, at very low input voltages, the widths of the transistors that are directly driven by the low-swing signals need to be significantly increased in order to balance the strength of the pull-up and the pull-down networks. This causes further degradation in the speed and the power efficiency of the conventional level converters when utilized with very low input voltages. The standard feedback-based level converter (LC1) [2] is shown in Fig. 1. and experience a low gate overdrive voltage during the operation of the circuit. and need to be sized larger to produce more current as compared to and, respectively, for functionality. The circuit operates as follows. When the input is at 0 V is turned off. is charged to. is turned on. is discharged to 0 V turning on. is charged to turning off. The output is pulled down to 0 V. When the input transitions to, is turned on. is discharged, turning off. is discharged, turning on. is charged up to turning off. The output Fig. 1. Standard level converter (LC1) presented in [2]. V is the lower supply voltage. V is the higher supply voltage. transitions to. A feedback loop, isolated from the input, controls the operation of and during both transitions of the output. Due to the transitory contention between the pull-up and the pull-down networks and the large size of the nmos transistors ( and ), however, LC1 consumes significant short-circuit and dynamic switching power. To maintain functionality with the lower values of, the sizes of and need to be further increased in order compensate for the gate overdrive degradation. The load seen by the previous stage (driver circuit) is therefore increased, thereby further degrading the speed and increasing the power consumption. Tapered buffers are required to drive and at very low voltages. These tapered buffers further increase the power consumption of LC1. Another level converter (LC2) is presented in [4] for enhanced speed as compared to LC1. LC2 is shown in Fig. 2. maintains the voltage of between and in order to enhance the current produced by. The capacitor 8fF stabilizes the voltage of against the noise induced by the nearby switching events. The circuit operates as follows. When the input is at 0 V, is discharged through. is turned on. is turned off. is charged to, turning off. The output is discharged to 0 V. When the input transitions to, is turned on. is initially charged to a voltage between and through. is not completely cutoff (weakly active). is sized to be stronger than for the circuit to function properly. is discharged, turning on. is charged all the way up to, thereby eventually turning off. The output transitions to. When the input switches from 0 V to there is a direct current path from to through the path. This direct current path exists until is charged to through and. Similarly, when the input switches from to 0 V, there is a direct current path from to through the path. This direct current path exists until is pulled up to and is turned off. LC2 therefore consumes significant short-circuit power, similar to LC1, during both low-to-high and high-to-low transitions of the output. Furthermore, when is reduced, a significant increase in the size of is required for maintaining functionality. The load seen by the driver circuit therefore increases at lower. Tapered buffers are required for driving LC2 at

3 TAWFIK AND KURSUN: LOW POWER AND HIGH SPEED MULTI THRESHOLD VOLTAGE INTERFACE CIRCUITS 3 Fig. 2. Level converter (LC2) presented in [4]. be more negative (higher- ) in order to suppress the static dc current. Provided that a multi- CMOS technology is available, no increase in the size of is required for achieving functionality at lower input voltages with the proposed circuit (unlike LC1 and LC2). Therefore, particularly for the very low values of, PC1 consumes lower power, occupies significantly smaller area, and imposes a much smaller load capacitance on the input driver as compared to LC1 and LC2. The circuit configurations of the second proposed level converter (PC2) for operation at different supply voltages are shown in Fig. 4. is required to be higher than for eliminating the static dc current when the input is low ( is at ). needs to be cutoff after a 1 is successfully propagated to the output (the input is at and the output is at ) in order to avoid the formation of a static dc current path between and though. The peripheral circuitry composed of,, and C, shown in Fig. 4(a), is employed to maintain the voltage in the range of in order to enhance the speed of charge transfer through while avoiding the formation of a static dc current path within the level converter. maintains the voltage of at provided that (1) (2) Fig. 3. First proposed level converter (PC1). Thick line in the channel area indicates a high-v device. very low voltages. These tapered input drivers further increase the power consumption of LC2. B. Multi- Level Converters Two new multi- level converters are described in this section. Unlike the previously published level converters that rely on feedback, the proposed level converters employ a multi- CMOS technology in order to eliminate the static dc current. The high threshold voltage pull-up network transistors in the new level converters are directly driven by the low-swing signals without producing a static dc current problem. The first proposed level converter (PC1) is shown in Fig. 3. PC1 is composed of two cascaded inverters with dual- transistors. The threshold voltage of is more negative (higher ) for avoiding static dc current in the first inverter when the input is at. is required to be higher than for eliminating the static dc current. PC1 operates as follows. When the input is at 0 V, is turned on. is cutoff. is pulled up to. The output is discharged to 0 V. When the input transitions to, is turned on. is turned off since. is discharged to 0 V. The output is charged to. PC1 has fewer transistors as compared LC1 and LC2. Furthermore, the elimination of the slow feedback circuitry reduces the short-circuit power of PC1 as compared to LC1 and LC2. For the lower values of, the threshold voltage of M2 needs to If (3) is satisfied, is maintained cutoff under normal operating conditions with no external noise coupling onto. The purpose of is to provide a discharge path for if the voltage on temporarily exceeds due to nearby switching events and crosstalk. The capacitor 6fF stabilizes the voltage of against the noise induced by the nearby switching events. The value of the capacitor is determined by circuit simulation such that the voltage of does not vary by more than 10% due to the coupling noise generated from within the level converter by the switching input signal. The capacitor is implemented by a MOSFET. If, however, (3) is not satisfied for the very low values of, a dc current path exists between and through and. In order to avoid a static dc current path within the level converter,, and the capacitor C are eliminated and is directly connected to for the voltages that do not satisfy (3), as shown in Fig. 4(b). Similarly, if (1) is not satisfied for certain values of and, is directly connected to, eliminating the need for,, and C as shown in Fig. 4(b). PC2 operates as follows. When the input is at 0 V, is pulled high to turning off (note that has a high- ). The output node is discharged to 0 V through the pass transistor. When the input transitions to, the output node is initially charged to and through with the circuit configurations shown in Fig. 4(a) and (b), respectively. is turned on after the high-to-low propagation delay of the inverter. The (3)

4 4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fig. 5. Simulation setup for characterizing the level converters. Power is measured for the entire test circuit including the driver and the load inverters. Delay is measured from the input of the driver inverter (I ) to Node. and the target application. The simulations are carried out for the following values of : 0.5, 1, and 1.2 V. The standard nominal supply voltage is 1.8 V in this m CMOS technology. All the transistors of LC1 and LC2 have nominal-. Comparison between the level converters at the nominal process corner is presented in Section III-A. The characteristics of the level converters under supply voltage and process parameter variations are given in Section III-B. The superiority of the proposed multi- circuits for achieving higher-speed and lower-power voltage level conversion is confirmed in Section III-C for a wide range of available threshold voltages. Fig. 4. Second proposed level converter (PC2). Thick line in the channel area indicates a high-v device. (a) Circuit configuration for V and V that satisfy both (1) and (3). (b) Circuit configuration for the supply voltages that do not satisfy either (1) or (3). output is pulled high all the way up to through. is turned off isolating the two power supplies. Both and assist the output low-to-high transition, thereby eliminating the contention current and enhancing the low-to-high propagation speed. The small transistor count and the elimination of the feedback reduce the power consumption of the proposed level converter as compared to LC1 and LC2. Furthermore, the speed of PC2 is enhanced due to the shorter input-to-output signal propagation path (composed of only one pass transistor) and the elimination of the contention current during the output low-to-high transition. III. SPEED AND POWER CONSUMPTION CHARACTERISTICS In this section, the two new level converters are compared to the previously published standard feedback-based level converters for average power consumption and propagation delay. The available slacks in the propagation delay paths, the power consumption and delay overhead of the level converters, the availability of high efficiency power supplies, and the availability of a multi- CMOS technology with adequate threshold voltages are the important factors that determine the optimum supply voltages in a multi- system [2], [4] [10]. A wide range of lower supply voltages is considered in this paper since the factors that determine the desirable and feasible optimum supply voltages vary with the available technology A. Comparison at the Nominal Process Corner The level converters are characterized at the nominal process corner in this section. LC1 is redesigned for proper functionality at 0.5 V. and are driven by low-swing signals while M3 and M4 are biased with full-swing signals (see Fig. 1). At very low, the currents conducted by and are significantly reduced. and are resized for producing higher current as compared to and. Tapered inverters are employed in order to drive and after the resizing. The sizing of these tapered inverters is included in the optimization process. Similarly, LC2 is redesigned for proper functionality at 0.5 V. The size of is increased significantly for functionality with LC2 at 0.5 V (see Fig. 2). An inverter that is large enough for driving is used. The resizing of the new inverter is included in the optimization process. is removed to maintain the output polarity. At 0.5 V, the second configuration of PC2 shown in Fig. 4(b) is used since both (1) and (3) are violated. Two cascaded inverters are added at the output of PC2 before the load. The simulation setup is depicted in Fig. 5. The size of the driver and the load inverters are 4 the size of a minimum size inverter (minimum sized inverter:, and 2.5 W ). The temperature is 125 C. The activity factor of the input signal is 0.1 (a typical value for the logic core of an IC [4]). The propagation delay is measured from the input of to in order to include the loading effect of the level converter on the driver circuit when optimizing the level converter for minimum propagation delay. Reducing the sizes of the transistors in the level converter decreases the dynamic switching power consumption by lowering the switched capacitance. However, the level converter output rise and fall times are increased with the reduced size of the transistors, thereby increasing the short-circuit power consumption of the load. The average power consumption is measured for the whole circuit (including the power consumed by the driver and the load ) in order to evaluate the tradeoff between the dynamic

5 TAWFIK AND KURSUN: LOW POWER AND HIGH SPEED MULTI THRESHOLD VOLTAGE INTERFACE CIRCUITS 5 TABLE I TOTAL TRANSISTOR WIDTH (W), AVERAGE PROPAGATION DELAY (D), AND AVERAGE POWER CONSUMPTION (P) OF THE LEVEL CONVERTERS TABLE III NORMALIZED TOTAL TRANSISTOR WIDTH (W), AVERAGE PROPAGATION DELAY (D), AND AVERAGE POWER CONSUMPTION (P) OF THE LEVEL CONVERTERS TABLE II OPTIMUM THRESHOLD VOLTAGES WITH THE PROPOSED LEVEL CONVERTERS switching power consumption of the level converter and the short-circuit power consumption of the load. The circuits are optimized with two different design criteria for each value of. Minimizing the average power consumption and minimizing the average propagation delay are the goals of the first and the second sets of optimizations, respectively. The design and optimization of the circuits are carried out using HSPICE built-in optimizer in a m TSMC CMOS technology. The optimization results are listed in Table I. The optimum threshold voltages of and are listed in Table II for the proposed circuits at different input voltages and optimization goals. As described in Section II-B, the threshold voltage of is required to be higher than 0.6, 0.8, and 1.3 V for 1.2, 1, and 0.5 V, respectively, for both PC1 and PC2. Similarly, from (1) (3), the ranges of for 1.2 V and 1 V are 0.13 V 0.6 and 0.33 V 0.8 V, respectively. As listed in Table I, when the circuits are individually optimized for minimum power consumption, PC1 and PC2 consume lower power as compared to LC1 and LC2 for all values of. Alternatively, when the circuits are optimized for minimum average propagation delay, PC1 and PC2 are faster as compared to LC1 and LC2 for all values of. From this point on, the proposed circuits are compared only with LC2 since LC2 is faster and consumes lower power as compared to LC1. The normalized total transistor width, average propagation delay, and power consumption of LC2, PC1, and PC2 are listed in Table III. When the circuits are optimized for minimum power consumption, the power consumption of PC1 is 11% (3%), 13% (10%), and 58% (25%) lower as compared to LC2 (PC2) for 1.2, 1, and 0.5 V, respectively. When the circuits are optimized for minimum propagation delay, the propagation delay of PC2 is 41% (25%) and 22% (7%) lower as compared to LC2 (PC1) for 1.2 and 1 V, respectively. The propagation delay of PC1 is 70% (40%) lower as compared to LC2 (PC2) at 0.5 V. The total transistor width of PC1 is 54% to 96% (61% to 94%) smaller as compared to LC1 (LC2) for the various design objectives and values considered in this paper. B. Characterization Under Supply Voltage and Process Parameter Variations The robustness of the level converters is evaluated under process and supply voltage variations in this section. The channel length, the gate oxide thickness, the channel doping, and the supply voltages are assumed to have independent normal Gaussian distributions. Each parameter is assumed to have a three sigma variation of 10%. Monte Carlo simulations with 1500 samples are run to produce the statistical distributions of the propagation delay and the power consumption. The Monte Carlo simulation results are shown in Figs In the first phase of the analysis, LC2 and PC2, initially optimized for minimum propagation delay at 1.2 V at the nominal process corner and supply voltages, are characterized under supply voltage and process parameter variations. The mean of the propagation delay and the power consumption of PC2 are reduced by 40% and 14%, respectively, as compared to LC2 as shown in Fig. 6. The power consumption distributions of LC2 and PC2 intersect at 5.1 W. 85.4% of the statistical samples consume more than 5.1 W with LC2. Alternatively, with the proposed circuit PC2, 78.5% of the statistical samples consume less than 5.1 W, as illustrated in Fig. 6(b). In the second phase of analysis, LC2 and PC1, initially optimized for minimum power consumption at 1 V at the nominal process corner and supply voltages, are characterized

6 6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fig. 6. Statistical delay and power distributions of PC2 and LC2. (a) Propagation delay. (b) Power consumption. The level converters (LC2 and PC2) are optimized for minimum propagation delay at V = 1.2 V. SD: standard deviation. under process parameter and supply voltages fluctuations. The mean of the propagation delay and the power consumption of PC1 are reduced by 10% and 13%, respectively, as compared to LC2 as shown in Fig. 7. The propagation delay distributions of LC2 and PC1 intersect at 210 ps. With LC2, the propagation delay of 90% of the statistical samples is longer than 210 ps. Alternatively, with PC1, the propagation delay of 83% of the statistical samples is shorter than 210 ps as shown in Fig. 7(a). The power consumption distributions of LC2 and PC1 intersect at 4.07 W. With LC2, 80% of the statistical samples consume more than Alternatively, with PC2, 81% of the statistical samples consume less than 4.07 W, as illustrated in Fig. 7(b). Finally, LC2 and PC1, initially optimized for minimum power consumption at 0.5 V at the nominal process corner and supply voltages, are characterized under process parameter and supply voltages fluctuations. The mean (standard deviation) of the propagation delay and the power consumption of PC1 are 71% (78%) and 59% (74%) lower, respectively, as compared to LC2 as shown in Fig. 8. C. Multi- CMOS Technology In a multi- CMOS technology, the available threshold voltages are limited to a few discrete values. The speed and power consumption characteristics of the proposed level converters are optimized over a wide range of threshold voltages in this section in order to assess the effectiveness of the proposed Fig. 7. Statistical delay and power distributions of PC1 and LC2. (a) Propagation delay. (b) Power consumption. The level converters (LC2 and PC1) are optimized for minimum power consumption at V = 1 V. SD: standard deviation. circuits with different CMOS technologies. The variations of the power consumption and the propagation delay with the threshold voltages are plotted in Figs for different. In Figs the lower limit of the PMOS threshold voltage is the nominal threshold voltage minus the difference between and. The upper limit of the pmos threshold voltage is determined as either the nominal threshold voltage or the value at which the optimized characteristic of the proposed circuit starts to degrade as compared to LC2 or when the circuit fails to function due to the reduced voltage swing of the output signal. As shown in Figs. 9 11, the proposed circuits maintain higher speed and lower power consumption characteristics as compared to LC1 and LC2 for a wide range of the available threshold voltages. The power and speed overhead of the level converters limit the amount of feasible voltage scaling in multi- systems. The power consumption and propagation delay overheads are significantly reduced with the proposed level converters as compared to the previously published standard feedback-based circuits. The new multi- level converters therefore allow further supply voltage scaling beyond the low voltages that would be permitted in a multi- system based on the standard feedback-based level converters. Furthermore, with technology scaling, the threshold voltages are scaled less aggressively as compared to the supply voltages. The implementation of the proposed feedback-free circuit techniques therefore becomes more feasible as the gap between the supply and threshold voltages tends to become narrower with technology scaling.

7 TAWFIK AND KURSUN: LOW POWER AND HIGH SPEED MULTI THRESHOLD VOLTAGE INTERFACE CIRCUITS 7 Fig. 10. Variations of the propagation delay and the power consumption of PC1 with the threshold voltage of M (V ) at V = 1 V. For each V, PC1 is reoptimized/resized to minimize the power consumption. Fig. 8. Statistical delay and power distributions of PC1 and LC2. (a) Propagation delay. (b) Power consumption. The level converters (LC2 and PC1) are optimized for minimum power consumption at V = 0.5 V. SD: standard deviation. Fig. 11. Variations of the propagation delay and the power consumption of PC1 with the threshold voltage of M (V ) at V = 0.5 V. For each V, PC1 is reoptimized/resized to minimize the power consumption. Fig. 9. Variations of the propagation delay and the power consumption of PC2 with the threshold voltage of M (V ) and M (V ) at V = 1.2 V. For each V, PC2 is reoptimized/resized to minimize the propagation delay. system. When the circuits are individually optimized for minimum power consumption in a m TSMC CMOS technology, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, speed is enhanced by up to 78% with the proposed circuits. The proposed circuits maintain higher speed and lower power consumption characteristics as compared to the conventional feedback-based level converters for a wide range of available threshold voltages with different multi- CMOS technologies. IV. CONCLUSION In this paper, two novel level converters based on a multi- CMOS technology are proposed. Unlike the standard level converters based on feedback, the new circuits employ multitransistors in order to suppress the dc current paths in CMOS gates driven by low-swing input signals. The proposed level converters are compared with the previously published circuits for different values of the lower supply voltages in a multi- REFERENCES [1] V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design. New York: Wiley, [2] K. Usami et al., Automated low-power technique exploiting multiple supply voltages applied to a media processor, IEEE J. Solid-State Circuits, vol. 33, no. 3, pp , Mar [3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, MA: Cambridge University Press, [4] S. H. Kulkarni and D. Sylvester, High performance level conversion for dual VDD design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp , Sep

8 8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS [5] A. Srivastava and D. Sylvester, Minimizing total power by simultaneous Vdd/Vth Assignment, in Proc. IEEE Des. Autom. Conf., Jan. 2003, pp [6] S. H. Kulkarni, A. N. Srivastava, and D. Sylvester, A new algorithm for improved VDD assignment in low power dual VDD systems, in Proc. IEEE Int. Symp. Low Power Electron. Des., Aug. 2004, pp [7] F. Ishihara, F. Sheikh, and B. Nikolić, Level conversion for dualsupply systems, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp , Feb [8] V. Kursun, R. M. Secareanu, and E. G. Friedman, CMOS voltage interface circuit for low power systems, in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 3, pp [9] M. Takahashi et al., A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme, IEEE J. Solid- State Circuits, vol. 33, no. 11, pp , Nov [10] M. Hamada et al., A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme, in Proc. IEEE Custom Integr. Circuits Conf., May 1998, pp [11] D. E. Lackey et al., Managing power and performance for system-on-chip designs using voltage islands, in Proc. IEEE/ACM Int. Conf. Comput.Aided Des., Nov. 2002, pp Sherif A. Tawfik received the B.S. and M.S. degrees in electronics and communications engineering from Cairo University, Cairo, Egypt, in 2003 and 2005, respectively. He is currently pursuing the Ph.D. degree in electrical and computer engineering from the University of Wisconsin-Madison under the supervision of Prof. V. Kursun. His research interests include the area of low-power and variations-tolerant integrated circuit design and emerging integrated circuit technologies. He has more than 20 publications. Volkan Kursun (S 01 M 04) received the B.S. degree in electrical and electronics engineering from the Middle East Technical University, Ankara, Turkey, in 1999, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, Rochester, NY, in 2001 and 2004, respectively. He performed research on mixed-signal thermal inkjet integrated circuits with Xerox Corporation, Webster, NY, in During summers 2001 and 2002, he was with Intel Microprocessor Research Laboratories, Hillsboro, OR, where he was responsible for the modeling and design of high frequency monolithic power supplies. During summer 2008, he was a visiting Professor with the Chuo University, Tokyo, Japan. He served as an Assistant Professor with the Department of Electrical and Computer Engineering, University of Wisconsin-Madison, from August 2004 to August He has been an Assistant Professor with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, People s Republic of China, since August His current research interests include the areas of low voltage, low power, and high performance integrated circuit design, modeling of semiconductor devices, and emerging integrated circuit technologies. He has more than 80 publications and 4 issued and 2 pending patents in the areas of high performance integrated circuits and emerging semiconductor technologies. He is the author of the book Multi-Voltage CMOS Circuit Design (Wiley, 2006). Dr. Kursun serves on the technical program and organizing committees of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), the ACM/SIGDA Great Lakes Symposium on VLSI (GLSVLSI), the IEEE International Symposium on Circuits and Systems (ISCAS), the IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED), and the IEEE Asian Solid-State Circuits Conference (A-SSCC). He served on the editorial board of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II: EXPRESS BRIEFS from 2005 to He is an Associate Editor of the Journal of Circuits, Systems, and Computers (JCSC), the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I: REGULAR PAPERS.