Implementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell

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1 International Journal of Electronics and Computer Science Engineering 333 Available Online at ISSN: Implementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell Arun Prakash Singh 1, Rohit Kumar 2 1 Electronics and Communication Engineering Department, Northern India Engineering College, Lucknow, Uttar Pradesh, India. 2 Electronics and Communication Engineering Department, Krishna Girls Engineering College, Kanpur Uttar Pradesh, India arun_prakash_singh@yahoo.co.in, 2 rohit.hbti@rediffmail.com Abstract- Now a-days in digital circuits design high speed, high throughput, small silicon area, and at the same time, lowpower consumption of digital circuit is most important things for digital circuit designers. In this paper a novel design method of a low power digital circuit is discussed, where the GATE DIFFUSION INPUT (GDI) technique has been used for the simultaneous generation of digital logic functions. Simulation results are performed by AIMSPICE based on 0.18µm CMOS technology, shows GDI technique of low power digital circuit design. Simulation results shows up to 45% reduction in power-delay product in GDI. GDI approach allows implementation of a wide range of complex logic functions using only two transistors. This method is suitable for designing of fast, low power circuits, using reduced number of transistor (as compared to CMOS techniques), while improving power characteristics. Keywords: Gate Diffusion Input (GDI), Low Power Design, complex logic, Power characteristic 1. INTRODUCTION Most of the VLSI applications, such as DSP, image & video processing, and microprocessors, extensively use logic gates and arithmetic circuits. AND, OR, addition, subtraction, and multiplication are examples of the most commonly used operations by these circuits. Logic gates are the building block of all digital circuits also 1-bit full adder cell is the extensively use in arithmetic circuits. Thus, enhancing their performance is critical for enhancing the overall module performance. Recently, building low-power VLSI systems has emerged as highly in demand because of the fast growing technology in mobile communication and computation. The battery technology does not advance at the same rate as the microelectronics technology. There is a limited amount of power available for the mobile systems. So designers are faced with more constraints: high speed, high throughput, small silicon area, and at the same time, low-power consumption. So building low-power, high performance adder cells are of great interest. A structured approach for designing and analyzing an adder cell is based on decomposing it into smaller modules. Each of these modules is implemented, optimized, and tested separately. Several full adder cells are composed by connecting these modules. For addition performed in DSP applications, latency and throughput are the two major constraints from delay perspective. Adder is not only a high-delay block but also a significant source of power dissipation. That s why, if one also aims to minimize power consumption, it is of great interest to identify the techniques to be applied to reduce delay by using various delay optimizations. Minimizing power consumption for digital systems involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control, which allows the reduction of supply voltage without significant impact on logic speed. Since energy is consumed only when capacitance is being switched, power can be reduced by minimizing this capacitance through operation reduction, choice of number representation, exploitation of signal correlations. 1.1-WHY LOW POWER? Power dissipation limitations come in two ways. The first is related to cooling considerations when implementing high performance systems. High-speed circuits dissipate large amounts of energy in a short amount of time, generating a great deal of heat. This heat needs to be removed by the package on which integrated circuits are

2 IJECSE, Volume1, Number 2 Arun Prakash Singh and Rohit Kumar mounted. Heat removal may become a limiting factor if the package cannot sufficiently dissipate this heat or if the required thermal components are too expensive for the application. The second failure of high-power circuits relates to the increasing popularity of portable electronic devices. Laptop computers, portable video players and cellular phones all use batteries as a power source. These devices provide a limited time of operation before they require recharging. To extend the battery life, low power operation is desirable in integrated circuits ADVANTAGES OF GDI OVER CMOS TECHNOLOGY 1. Low power circuit design 2. Allows reducing power consumption. 3. Reducing propagation delay. 4. Reducing area of digital circuit. 5. Maintaining low complexity of logic design. 2. BASIC GATE DIFFUSION INPUT (GDI CELL) FUNCTIONS Gate Diffusion Input (GDI CELL) method is based on the use of a simple cell as shown in Figure -1 [1]. At a first glance the basic cell reminds the standard CMOS inverter, but there are some important differences: (1) Gate Diffusion Input (GDI CELL) contains three inputs G (common gate input of NMOS and PMOS), P (input to the source/drain of PMOS), and N (input to the source/drain of NMOS). (2) Bulks of both NMOS and PMOS are connected to N or P (respectively), so it can be arbitrarily biased at contrast with CMOS inverter. It must be remarked, that not all the functions are possible in standard P-Well CMOS process, but can be successfully implemented in Twin-Well CMOS technologies. A simple change of the input configuration of the simple Gate Diffusion Input (GDI) CELL as shown in figure -1 corresponds to six different Boolean functions. 1. When input N=0, P=B, and G=A then output D= AB which is function F1. 2. When input N=B, P=1, and G=A then output D= A + B which is function F2. 3. When input N=1, P=B, and G=A then output D=A+B which is OR function. 4. When input N=B, P=0, and G=A then output D=AB which is AND function. 5. When input N=C, P=B, and G=A then output D= AB + AC which is MUX function and When input N=0, P=1, and G=A then output D= A which is NOT function. Figure -1: Gate Diffusion INPUT (GDI) Basic Cell Table -1 also shows a simple change of the input configuration of the simple Gate Diffusion Input (GDI) CELL corresponds to six different Boolean functions. Most of these functions are complex (6-12 transistors) in CMOS, as well as in standard CMOS implementations, but very simple (only 2 transistors per function) in Gate Diffusion Input (GDI CELL) design method. As can be seen in [1], Gate Diffusion Input (GDI CELL) structure is different from the

3 Implementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell 335 existing CMOS techniques and has some important features, which allows improvements in design complexity level, N P G OUTPUT FUNCTION 0(0V) B(3.3V) A(0V) AB (3.05V) F1 B(0V) 1(3.3V) A(0V) A +B (3.3V) F2 1(3.3V) B(3.3V) A(0V) A+B(2.53V) OR B(3.3V) 0(0V) A(0V) AB(0V) AND C(3.3V) B(3.3V) A(0V) 0(0V) 1(3.3V) A(0V) A (3.3V) transistor counts, static power dissipation and logic level swing TRANSIENT ANALYSIS OF BASIC GATE DIFFUSION INPUT (GDI) FUNCTIONS Figure 2-7 shows the transient analysis of basic Gate Diffusion Input (GDI) functions given in table -1. Here V(1) is input voltage at G, V(2) is input voltage at P, V(4) is input voltage at N and V(3) is output voltage at D of basic Gate Diffusion Input (GDI) CELL as shown in figure 2.1. (i) FUNCTION F1 ( AB ) AB + AC (2.53V) MUX NOT (ii) FUNCTION F2 ( A +B) Figure -2: TRANSIENT ANALYSIS OF FUNCTION F1 ( AB ) (iii) OR GATE (A+B) Figure -3: TRANSIENT ANALYSIS OF FUNCTION F2 ( A +B)

4 IJECSE, Volume1, Number 2 Arun Prakash Singh and Rohit Kumar (iv) AND GATE (AB) Figure -4: TRANSIENT ANALYSIS OF OR GATE (A+B) Figure -5: TRANSIENT ANALYSIS OF AND GATE (AB) (v) MUX ( AB + AC ) (vi) NOT ( A ) Figure -6: TRANSIENT ANALYSIS OF MUX Figure -7: TRANSIENT ANALYSIS OF NOT ( A )

5 Implementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell OPERATIONAL ANALYSIS OF GATE DIFFUSION INPUT (GDI) CIRCUITS To understand the effects of the low swing problem in a Gate Diffusion Input (GDI) cell as shown in figure -1, the following analysis is given, based on the example of F1 function, and can be easily extended to use in other Gate Diffusion Input (GDI) functions. Table -2 presents a full set of logic states and related functionality modes of F1. Transient analysis of this function is shown in figure -2. As can be seen from Table -2, the only state where low swing occurs in the output value is A= 0 and B= 0. In this case, the voltage level of F1 is V =.50V (instead of the expected 0 V) because of the poor high-to-low transition tp characteristics of the PMOS pass transistor. It is obvious that the only case (among all the possible transitions) where the effect occurs is the transition from A= 0 and B= V to A= 0 and B= 0. This is also shown in figure 3. The fact that demands special emphasis is that in about 50% of the cases (for), the Gate Diffusion Input (GDI) cell operates as a regular CMOS inverter, which is widely used as a digital buffer for logic-level restoration. In some of these cases, when V = 1 without a swing drop from the previous stages, a Gate Diffusion Input (GDI) cell functions as an inverter buffer and recovers the voltage swing. Table- 2: INPUT LOGIC STATES vs. FUNCTIONALITY SWING OF F1 FUNCTION. A(Input at G) B(Input at P) Functionality 0 0 pmos Trans Gate 0 V CMOS Inverter V 0 nmos Trans Gate F1( AB,Output at D) Voltage level V.50V Tp V 3.05V 0 0V V V CMOS Inverter 0 0V 2.3. COMPARISONS WITH CMOS LOGIC STYLES In this work a variety of logic gates have been implemented in 0.35µm technology to compare the Gate Diffusion Input (GDI) technique with CMOS. Five sets of comparisons were carried out on different logic gates. Circuits were designed at the transistor-level in a 0.35 µm twin-well CMOS process technology. The circuits were simulated using AIMSPICE at 3.3V with load capacitance of 100fF. Each set includes a logic cell implemented in two different techniques: Gate Diffusion Input (GDI) and CMOS. Cells were designed for a minimal number of transistors. Several examples of logic gates in both techniques are shown in Table 2.3.circuits were implemented with W/L ratio of 3, to achieve the best power-delay performance. Same transitions of logic values were supplied to the inputs of the test circuits in both techniques. Measured values apply to transitions in inputs connected to gate of transistors, in order to achieve a consistent comparison. Measurements were performed on test circuits that were placed between two blocks, which contain circuits similar to the device under test. This allows more realistic environment conditions for test circuit, instead of the ideal input transitions of simulator's voltage sources.

6 IJECSE, Volume1, Number 2 Arun Prakash Singh and Rohit Kumar Table -3: AND and OR CELLS USING GATE DIFFUSION INPUT and CMOS DESIGN TECHNIQUES In order to perform a fair comparison between the both techniques, the measurements were carried out from cells series with buffers and not from a single cell. Gate Diffusion Input (GDI) test circuits contain two basic cells with one output buffer. CMOS has no buffers in test circuits. As can be seen from Table 2.3, between the both design techniques, Gate Diffusion Input (GDI) proves to have the lowest transistor count. Power and Delay comparison between both techniques is given in table 2.4. This comparison shows that CMOS delays compared to Gate Diffusion Input (GDI), in most cases are bounded according to expression given in equation 2.1. t (2.1) t PHL( cmos) PHL( GDI ) Table - 4: LOGIC GATES COMPARISIONS of GDI and CMOS Gate type in series Logic expression GDI CMOS MUX AB + AC Power( µ w ) Delay(ns ec) Power( µ w ) Delay(ns ec) OR A+B AND AB F1 AB F2 A +B CONVETIONAL CMOS 1-BIT FULL AER In most VLSI applications, arithmetic operations play an important role. Commonly used operations are addition, subtraction, multiplication and accumulation, and the 1-bit Full Adder (FA) cell is the building block for most implementations of these operations. Conventional CMOS Style a basic cell in digital computing systems is the 1-bit full adder which has three 1-bit inputs (A, B, and Cin ) and two 1-bit outputs (sum and carry). The relations between the inputs and the outputs are expressed as: SUM = A B Cin.(3.1) CARRY = A B + Cin( A B)...(3.2)

7 Implementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell 339 The internal structure of 1-bit conventional CMOS full adder cell is shown in Figure 8 [2]. The 1-bit conventional CMOS full adder cell has 28 transistors. Different logic styles can be investigated from different points of view. Evidently, they tend to favor one performance aspect at the expense of others. In other words, it is different design constraints imposed by the application that each logic style has its place in the cell library development. Even a selected style appropriate for a specific function may not be suitable for another one. For example, static approach presents robustness against noise effects, so automatically provides a reliable operation. The issue of ease of design is not always attained easily. The CMOS design style is not area efficient for complex gates with large fan-ins. Thus, care must be taken when a static logic style is selected to realize a logic function. Pseudo NMOS technique is straightforward, yet it compromises noise margin and suffers from static power dissipation. Pass transistor logic style is known to be a popular method for implementing some specific circuits such as multiplexers and XOR-based circuits, like adders. On the other hand, dynamic logic facilitates the realization of fast, small and complex gates. However, this advantage is gained at the expense of parasitic effects such as load sharing, which makes the design process hazardous. Charge leakage necessitates frequent refreshing, reducing the operational frequency of the circuit. In general, none of the mentioned styles can compete with CMOS style in robustness and stability. The CMOS structure combines PMOS pull-up and NMOS pull-down networks to produce considered outputs. In this style all transistors (either PMOS or NMOS) are arranged in completely separate branches, each may consist of several sub-branches. Mutually exclusiveness of pull-up and pull-down networks is of a great concern. Figure 8 shows the conventional CMOS 28- transistor full adder. Table -8 : INTERNAL STRUCTURE 1-BIT CONVENTIONAL CMOS FULL AER [2] 3.1. XOR BASED FULL AER Equation (3.2) can be modify and written as given in equation (3.3). CARRY = ( X Y ) Y + ( X Y ) CIN.....(3.3) And these equation can be implemented by two XOR gate and one Gate Diffusion Input (GDI) MUX as shown in figure 9, 2-input XOR gate shown in figure 10. A B Figure -9: 2-INPUT XOR GATE

8 IJECSE, Volume1, Number 2 Arun Prakash Singh and Rohit Kumar Figure -10: XOR BASED FULL AER 3.2. GATE DIFFUSION INPUT (GDI CELL) XOR GATE XOR function is the key variables in adder equations. If the generation of them is optimized, this could greatly enhance the performance of the full adder cell. In this new cell, we have used the Gate Diffusion Input (GDI CELL) technique for generating of XOR function. The GDI XOR gate is shown as Figure below where only 4 transistors are used. Compare the Gate Diffusion Input (GDI CELL) XOR with the conventional CMOS counterpart, it is obvious that Gate Diffusion Input (GDI CELL) XOR gate requires less transistor. Figure -11: GATE DIFFUSION INPUT (GDI) XOR GATE 3.3 GATE DIFFUSION INPUT (GDI CELL) 1- BIT FULL AER According to figure 11, 1-bit full adder circuit requires two XOR gate and one MUX. Gate Diffusion Input (GDI CELL) XOR gate is shown in figure 11, which can be implemented by 4-transistor and MUX function is given in table 2, which can be implemented by 2-transistor. So according to figure 12 Gate Diffusion Input (GDI CELL) 1-bit full adder requires only 10-transistor. Hence attempt to create 10-transistor based full adder is achieved. 10-transistor full adder is shown in figure -12. Simulation result and power-delay comparison is given by figure 13 and table 5 respectively. Figure -12: GATE DIFFUSION INPUT (GDI CELL) BASED 1-BIT FULL AER

9 Implementation of 1-bit Full Adder using Gate Difuision Input (GDI) cell 341 From figure 8 and 12 we can see that Gate Diffusion Input (GDI CELL) 1-bit full adder requires less number of transistors than its conventional CMOS counterpart. 3.4: TRANSIENT ANALYSIS OF GATE DIFFUSION INPUT (GDI CELL) BASED 1-BIT FULL AER Transient analysis of sum and C out is shown in figure 13. The circuit is simulated using AIMSPICE at 3.3V with load capacitance of 100fF. Also all circuits were implemented with W/L ratio of 3. Here V(1) is input at A, V(4) is input at B, V(7) is input at C, V(8) is output at sum and V(9) is output at C as shown in figure 13. (i) SUM V(8) in out (ii) Cout V(9) (a) (b) Figure -13: TRANSIENT ANALYSIS OF GATE DIFFUSION INPUT (GDI CELL) BASED 1-BIT FULL AER 3.5: POWER-DELAY COMPARISON OF CMOS AND GATE DIFFUSION INPUT (GDI) 1- BIT FULL AER Power-delay comparison of CMOS and GATE DIFFUSION INPUT (GDI) 1- bit full adder is given in table -5. CHARCTERSTICS G DI POWER( µ w ) DELAY (nsec) NUMBER TRANSISTORS OF CM OS Table -5: COMPARISION OF GDI AND CMOS 1-BIT FULL AER CIRCUITS 2.087

10 IJECSE, Volume1, Number 2 Arun Prakash Singh and Rohit Kumar 4: CONCLUSIONS AND FUTURE SCOPE The advantages of Gate Diffusion Input (GDI CELL) technique, 2-transistors implementation of complex logic functions and in-cell swing restoration under certain operating conditions are unique within existing low-power design techniques. This together with positive measurement and simulation results, provide evidence that Gate Diffusion Input (GDI CELL) design might enrich the toolbox of VLSI designers. In this work, a new low-power full adder capable of operating down to 0.5V has been given. In this cell, the Gate Diffusion Input (GDI CELL) technique has been used for generating of intermediate function of XOR. The new circuit is the most energy efficient cell compared to several CMOS circuits We hope that the given results will encourage further research activities on Gate Diffusion Input (GDI CELL) technique. The issue of sequential logic design with Gate Diffusion Input (GDI CELL) is currently being explored, as well as technology compatibility for twin-well CMOS process. More work was done in automation of a logic design methodology based on Gate Diffusion Input (GDI) cells. References [1]. A. Morgenshtein, A. Fish, I. A. Wagner, Gate Diffusion Input (GDI) A Novel Power Efficient Method for Digital Circuits: A Design Methodology, 14th ASIC/SOC Conference, Washington D.C., USA, September [2]. A. M. Shams, T. K. Darwish and M. A. Bayoumi, Performance Analysis of Low-Power 1-Bit CMOS Full-Adder Cells, IEEE Trans. on VLSI Systems, vol. 10, Feb [3]. J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits, Reading, Addison-Wesley, pp [4]. N. Zhuang and H. Wu, A New Design of the CMOS Full-Adder, IEEE J. Solid-State Circuits, pp , May [5]. A. M. Shams and M. A. Bayoumi, A Novel High Performance CMOS 1-Bit Full-Adder Cell, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, pp ,May [6]. E. Abu Shama, A. Elechouemi, S. Sayed and M. Bayoumi, An Efficient Low Power Basic Cell for Adders, Proc. 38th Midwest Symposium on Circuits and Systems, pp , [7]. A. A. Fayed and M. A. Bayoumi, A Low Power 10 Transistor Full-Adder Cell for Embedded Architectures, IEEE International Symposium on Circuits and Systems, pp , [8]. Lu Junming, Shu Yan, Lin Zhenghui and Wang Ling, A Novel 10 Transistor low Power high Speed Full-Adder cell, Proc. of the 6th International Conference on Solid State and Integrated Circuit Technology, pp , [9]. Hanho Lee and G. E. Sobelman, A New Low Voltage Full-Adder Circuit, Proc. of the 7th Great Lakes Symposium on VLSI, 1997.