A Structured Approach for Designing Low Power Adders

Transcription

1 A Structured Approach for Designing Low Power Adders Ahmed M. Shams, Magdy A. Bayoumi (axs8245,mab 8 cacs.usl.edu) Abstract- A performance analysis of a general 1-bit full adder cell is presented. The adder cell is anatomized into smaller modules using the proposed structured approach. The modules are studied extensively and several designs of each of them are shown. Connecting combinations of designs of these modules together we construct 24 different 1-bit full adder cells (some of them are novel1 circuits). Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Some of the new cells outperform existing standard designs of the full adder cell. 1. Introduction Addition is one of the fundamental arithmetic operations, it is used extensively in many VLSI systems such DSP chips, and microprocessors. In addition to its main task which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division, address calculation,... etc. In most of these systems the adder is a main component in the critical path that determines the overall speed of the system. That is why enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal. The demand for low power circuits increases due to the emergence of many mobile products which have a limited source of power. So building low-power adder cells is another significant goal. Mainly there are three major components of power dissipation in CMOS circuits: (1)Switching power consumed by the circuit node capacitances during transistor switching, (2)Short circuit power consumed because of the current flowing from power supply to ground during transistor switching, and (3)Static power due to leakage current. The first two components are refered to as dynamic power. Dynamic power consitutes about The authors are with the Center for Advanced Computer Studies, University of Southwestern Louisiana, P.O. Box 44330, Lafayette, LA % of the power dissipated in CMOS VLSI circuits. It is given by the following equation: Pdynamic = (XI CI load-vi swing.pi).fclk.vdd + xi Ij sc. Vdd where Ciload is the load capacitance at node i, Vi swing is the voltage swing at node i (ideally it is equal to Vdd which is the power supply voltage), pi is the switching activity factor at node i, fclk is the system clock frequency, and Ii sc is the short circuit current at node i. The summation is over all the nodes of the circuit. Reducing any of these components will end up with lower power consumption, although we are always interested in increasing the clock frequency. Estimating the power of a large circuit is a complex task. It is better to decompose it into smaller modules, then use simulation to measure the power consumption of each of them. Following this strategy we find the best design of a given module, then by connecting the modules together we form a larger circuit which will be optimized for low power. We follow this approach in this paper, and we choose the full adder cell as a case study to demonstrate it. The remainder of this paper is structured as follows, in section I1 we define the building modules of the full adder cell. In section I11 we build and simulate different designs of each of these modules. Then we build 24 different full adder cells in Section IV using different combinations of designs of each of the building modules. Finally we present the full adder cells simulation results in section V and compare these adder cells based on power consumption, speed, power delay product, area and driving capability. II. Full Adder Building Modules First we review the full adder functions, given the three 1-bit inputs A, B, and Cin, it is desired /98 $ IEEE 757

2 to calculate the two 1-bit outputs Sum and Cout, where Sum = (A xor B) xor Cin Cout = A. B + Cin. (A xor B) Standard adder cells which are used in current VLSI circuits implement these equations, such as the standard CMOS full adder shown in Fig. l(a) which is based on the CMOS transmission gates and has 20 transistors [3], and the transmission function full adder cell shown in Fig. l(b) which is based on the transmission function theory and has 16 transistors [l]. k-74 :..... U Module 2 1- ut S A IH Module 3 i Cout Figure 3. The building modules of the full adder cell Figure 1. Standard full adder cells (a) The Conventional CMOS full adder. (b) The Transmission Function full adder These designs look at the equations as a whole so no further optimization can be done to come up with new ideas aiming for better performance. Recently, few enhancements were published, as an example the 14 transistors adder presented in [2] and shown in Fig. 2. Using the structured approach we try to figure out how to decompose the full adder cell (al- though it is small) into smaller and easier modules. Rewriting the equations as Sum = H xor Cin = H. Cin + H. Cin Cout = A. H + Cin. H where H is the half sum (A xor B). From the new equations we can figure out that a module is needed to calculate H and its complement H, which are the key variables in both equations. If we optimize the generation of H and H, this could greatly enhance the performance of the full adder cell. Another module is needed to generate the sum using H, H and Cin. A third module is needed to generate Cout given H, H, A, and Cin. Each module is analyzed, enhanced, optimized, and tested separately. A block diagram of the full adder cell and its building blocks is shown in Fig. 3. The inputs and outputs of each module are clear from the figure. Beginning with the first module, it is required to generate both the XOR and XNOR functions. Six different designs are shown in Fig. 4. A minimum of six transistors are used (the least known so far) [4], while we impose a maximum 75 8

3 ! 8$ H Table I. Simulation Results for first module. H Figure 4. Six different designs of the first module (XOR and XNOR functions). Figure 5. Four different designs of the second module (XOR function). of 10 transistors because designs with more than this figure will not be competitive for low power. The results of the simulation are shown in table I. The second module is required to generate the Sum given the inputs H, H (generated by the first module), and Cin. It is an XOR function too, so most of the designs given here are the same ones used in the first module. We present four different designs of the second module which are shown in Fig. 5. The results of the simulation are shown in table 11. The third module is required to Table 11. Simulation Results for second module. generate Cout, given H, H, A (or B) and Cin as inputs. All the standard adders as well as the new designs shown in [2,5] use the same approach to generate the Cout. Only one design is followed 759

4 H ut U Figure 6. One design of the third module. for the third module, it is shown in Fig. 6, and its simulation result is shown in table 111. T U Table 111. Simulation Results of the third module. uilding the I-bit Gout Choosing one design from the available designs for each module and connecting them as shown in Fig. 3 one can build 24 different adder cells (most of them are novel circuits). We will use the following convention for naming adder cell: An adder cell will be reffered to by two letters, the first letter denotes the first module design shown in Fig. 4, and the second letter denotes the second module design shown in Fig. 5. Two of these cells are shown in Fig. 7 as an example. The first one shown in Fig. 7(a) is cell AB (uses designs 4(a), 5(b) and 6), while the second, shown in Fig. 7(b) is cell CC. Adder cells with a minimum of 14 transistors are formed, one of them is cell CB, which happens to be the same adder as the one shown in Fig. 2 [2], while the other is cell CA. Another combination of designs forms the transmission function full adder shown in Fig. l(b); cell BB. A maximum of 20 transistors cells are formed, which are cells AC, EC, FC. All the other adder cells have transistor counts ranging from 15 to 19 transistors. This is a good range for comparison between different designs of adder cells. The standard CMOS adder is not one of the 24 adder cells built using our approach, but we had to build it in order to compare it with our adder cells. So a total of 25 adder cells are built, Figure 7. Two examples of building the 1-bit full adder cell. each of them exhibits its own figures for power consumption, delay, area, and driving capability. IV. Simulation Results The simulation results for the 24 full adder cells regarding power consumption are shown in table IV. From the table we can see that the designs that exhibit the lowest power consumption for the first and second modules (4(d), and 5(b)) when combined together give the lowest power adder cell DB, this validates the benefits of the structured approach. The best cell consumes 20% less power than the 14 transistors adder cell CB (ranked 6th), 27% less power than the transmission function adder cell BB (ranked loth), 56% less power than the standard CMOS adder cell (ranked 21st), and 79% less than the worst cell. V. Conclusions We have proposed a structured approach for decomposing large systems into smaller and easier to handle modules. Studying each of these modules separately and optimizing its performance 760

5 11 1 I DB I 2.76 I 1.00 I 16 I U 2 I DA I 2.84 I 1.03 I DD CA // 5 I BA I 3.18 I 1.15 I 16 I 3.37 CD EB BB BD ED DC FA AA CC FB CMOS I I 20 I Table IV. Simulation results for the 24 1-bit full adders sorted ascendingly by average power. I will end up enhancing the big system when connecting these modules together. As a case study we used the full adder cell and we decomposed it into three smaller modules. Each module was studied separately, several designs of each module were examined and compared from the power consumption point of view. By connecting different combinations of the designs of each module we built 24 different adder cells, some of them outperform existing full adder cell designs. VI. Acknowledgment The authors acknowledge the support of U.S. Departement of Energy (DOE), EETAPP program. VII. References Nan Zhuang and Haomin Wu, A new design of the CMOS full adder, IEEE J. of solidstate circuits, Vol. 27, No. 5, pp , May E. Abu-Shama and M. Bayoumi, A new cell for low power adders, proceedings of the International Midwest Symposium for Circuits and Systems, N. Weste and K. Eshraghian, Principles of CMOS VLSI design, a system perspective, Reading, MA: Addison-Wesley, Jyh-Ming Wang, Sung-Chuan Fang, Wu- Shiung Feng, New Efficient Designs for XOR and XNOR Functions on the Transistor Leve1, IEEE J. of solid-state circuits, Vol. 29, No. 7, pp , July Hanho Lee and Gerald E. Sobelman, A new Low-Voltage Adder Circuit, proceedings of the Seventh Great Lakes Symposium on VLSI,