Bridging the Gap between Dreams and Nano-Scale Reality

Transcription

1 Bridging the Gap between Dreams and Nano-Scale Reality Ban P. Wong Design Methodology, Chartered Semiconductor 28 July 2006

2 Outline Deficiencies in Boolean-based Design Rules in the sub-wavelength regime Patterning Distortion effect on Design Strain Si demands Layout discipline Nano-scaled CMOS matching issues CD control critical but getting difficult Wire (Litho & CMP) distortion changes designed characteristics, timing and even causes yield loss How do we Bridge the gap Summary 2

3 DRC Clean Alone is Not Sufficient Bridging on Silicon Found 3

4 Shorts Paradox 4

5 Layout Sensitivities of DSL Tensile nit Contact Compr nit N P ST oxide Buried tensile Compr N P Dual Stress Liner Fig. 5. SEM cross-section of an SRAM cell features tensile and compressive liner in NMOS and PMOS respectively. Poly pitch Contact space to Poly Contact Pitch Affects the channel strain and Mobility 5

6 Effect of Contact Perforation on CESL Stress Contact perforation of CESL can result in drive current variation Stress Simulation courtesy of V. Moroz (Synopsis) 6

7 Poly CD variation impact on yields & performance 6% decrease in Lpoly causes Iddq failures

8 Poly CD variation impact on yields Increases mean Vt but decreases sigma Large reduction in mean Vt & significantly increases sigma 0V Vt

9 Random Doping Effect Both devices have V threshold dopants in the channel 0.56V threshold depletion region Source: Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 um MOSFET s: A 3-D Atomistic Simulation Study, Asen Asenov, IEEE Trans on Electron Devices, Vol 45, No 12, pp , Dec

10 Compounding the problem Chip surface compounding the problem Caused by Design s Impact on CMP Eats into DOF margin compounding the problem Chip Surface Wafer Surface Source: Praesagus (Cadence) Source: PRAESAGUS 10

11 A Growing Problem Additional Metal Layers Compound the Topographical Impact of CMP induced variability Additional Metal Layers Compound the Topographical Impact Source: Praesagus (Cadence) Source: PRAESAGUS 11

12 Bridging the Gap Design solutions 12

13 Design participation to reduce CD variation Uni-direction Poly ~4% Critical circuits on 3 predetermined pitches or less ~4% Minimizes IDsat variations as well (more later) Wider Poly CD for hold time cells as well as large slack paths Blaze Timing aware poly length targetting 13

14 Bridging the Gap: Litho Friendly Design LFD Min diff opening Min diff to poly space Min diff corner to poly space A) B) Improved layout Figure 10.1 Source: Nano-CMOS Circuit and Physical Design 14

15 Layout styles need to change in the Sub-wavelength regime diffusion Potential short for shorts Source: Nano-CMOS Circuit and Physical Design 15

16 Litho Friendly Design Improves Yield No short Diffusion short A) Figure 10.7 B) Improved Source: Nano-CMOS Circuit and Physical Design 16

17 Layout effect on Transistor drive Contact (CA) and adjacent Poly (PC) which relaxes the strain in adjacent transistor PC to PC distance CA CD PC to CA F F At min contacted pitch, most of the CA nitride is consumed by the CA Force applied by strain nitride film is proportional to volume and proximity of the film to the channel The film volume & proximity is modulated by : Poly-to-Poly distance CA CD and CA-to-PC distance CA pitch 17

18 Stress Distribution Around Contacts Top view of an scesl MOSFET with 3 contacts Stress distribution before contact etch Contact-induced stress relaxation Stress Simulation courtesy of V. Moroz (Synopsys) 18

19 Remote Versus Nearby Contacts Low channel stress High channel stress Contacts are 60nm from the gate Contacts are 90nm from the gate Contacts are 180nm from the gate Stress Simulation courtesy of V. Moroz (Synopsys) 19

20 Stress Variation Caused by Contact-to-Poly Spacing Tensile stress liner assumed. Source: Synopsys 20

21 Effect of Contact & Dummy Poly on Channel stress 1.2 Normalized Average Channel Stress min PC pitch min PC pitch Self stress Dummy PC Layout All PC and CA pitch are minimum pitch Dummy PC+CA contacts 21

22 PMOS with e-sige Structure in S/D 22

23 45nm library cell Source: Synopsys 23

24 Low Vt Mismatch σ Vtn Low Vt Regular Vt nmos pmos Distance to n-well Distance to n-well Source: Greg Starr 24

25 Shallow Trench Isolation STI STI STI Amount of stress varies depending on Active size and trench size Larger the spacing between trenches, the less the overall stress 1. Need dummy active to keep trench size consistent 2. Use dummy transistors to increase spacing between trenches Source: Nano-CMOS Circuit and Physical Design 25

26 Use of Dummy Devices to Reduce STI effect device0 device1 device2 Thin Oxide Device dummies device0 device1 device2 dummies % difference in IDsat from no STI dummies device0 device1 device2 dummies device0 & 2 device Number of Dummy Devices Source: Greg Starr 26

27 Decoupling Capacitor Choice of decoupling cap layout matters - A LOT! Capacitor has too much series resistance Parasitic resistance will make the effective capacitance small Source: Greg Starr Significantly reduces the channel resistance making the cap more effective 27

28 Proximity to well and orientation: change in Vt Preferred orientation to well edge 1 2 Better matching Bad for matching Source: Nano-CMOS Circuit and Physical Design 28

29 Bridging the Gap New Design Tools 29

30 A Flipflop or a Litho Test Pattern? Cell Layout Poly-Diffusion Contours Print Simulation courtesy of ClearShape 30

31 Gate and diffusion sensitive area: Layout #1 #2 31

32 Gate and diffusion sensitive area #1 #2 Print Simulation courtesy of ClearShape 32

33 Gate and diffusion sensitive area #3 33

34 Gate and diffusion sensitive area #3: Contours Print Simulation courtesy of ClearShape 34

35 OPC Recipe Very Important if Design is Challenging Print Simulation courtesy of Brion 35

36 Slight OPC change can have an impact on CD 126nm 133nm 125nm 130nm 159nm 130nm 129nm 129nm 126nm 156nm Blue: Diff, Black:Poly OPC_1, Red: Poly OPC_2 36

37 OPC Recipe Critical These transistors are supposed to be identical, they are not This causes cell imbalance and result in reduced SNM Soft failures at low Vdd OPC accuracy is critical Can operate at lower Vdd Better yield 37

38 OPC Recipe is Critical A B Misalignment Beta diff (A) Beta diff (B) sigma CD (A) sigma CD (B) % 1.44% % -0.59% % 5.04%

39 Automatic Hotspot Correction Source: Takumi-Tech 39

40 Example 2: Automatic Hotspot Correction FR = 96.3 ppb FR = 79.3 ppb Source: Takumi-Tech 40

41 Calibrated Print Simulation Source: Chartered Semiconductor 41

42 65nm Vth Variability versus Width L=0.06 W: 3.2um 1.6um Geometry 1 Geometry 2 0.8um 0.4um 0.2um 0.12um 0.1um

43 65nm Vth Mismatch (nmos) SPICE s(dvth) Measured L=0.6um Measured L=0.06um /squrt(LW) [1/um] Vth mismatch shows strong L-dependency This effect needs to be taken into account in design 43

44 Process Can Shift Entire Chip Along Curve Global CD bias moves the chip along the process s chip-level IDDQ-FMAX curve Nominal Log (IDDQ) Pushed Global Bias FMAX Source: Chartered Semiconductor and Blaze 44

45 Blaze Can Shift Each Device Independently Move each device along the Ioff-Ion curve e.g., 30% leakage savings with minimal or no timing impact Chip moves off the process s chip-level IDDQ-FMAX curve to achieve lower IDDQ for the same FMAX Nominal Log (IDDQ) Pushed Global Bias Ideal Result of Blaze Bias: IDDQ reduction with no FMAX hit Actual Result of Blaze Bias: Better IDDQ reduction than in simulation but slight FMAX hit FMAX Source: Chartered Semiconductor and Blaze 45

46 LFD: Parametric Benefits - Timing Optimized Cell Pattern robustness translates into more consistent timing Source: Mentor Graphics 46

47 LFD: Parametric Benefit - Power Better CD control across Focus & exposure window Leakage robustness Power predictability Move this edge away from the active edge After Layout changes OPC can be less aggressive - pinching & flaring into active avoided resulting in a more constant CD across the entire channel This design results in higher CD variability due to Patterning distortion Pinching here can result from the need for more aggressive OPC to correct for the channel length Source: Mentor Graphics 47

48 CMP Related Yield Loss: Praesagus Bridging/Pooling Prediction pinpointed the short Metal X+1 Metal X Short Between Lines on M5 1.5 um Space too small for dummy fill. Passes all design rules Source: Praesagus 48

49 Pass functional intent to manufacturing flow Preferential treatment of critical circuits etc Leads to improvement of MDP and Mask build TAT without sacrificing patterning accuracy Pass limits of manufacturing flow to the designers Avoid shapes that cannot be manufactured or verified Limit Poly orientation & pitch for lower variation New tools will be needed to make this work With embedded mfg limits much like DRC decks Timing aware Poly CD biasing (IDDQ improvement, min timing impact) Tools to guide physical design for better print distortion tolerance Stress Proximity Effects Summary Must be considered in race circuits (hold time; self timed etc) 49

50 Anomalous Behavior of Channel Length in Vt Must be designed for especially in matched devices Contour based extraction Summary (cont) Captures device size distortions in extracted simulations 50

51 Bibliography References: 1. C. Spence, AMD, Mask Data Preparation Issues for the 90 nm Node: OPC Becomes a Critical Manufacturing Technology, Future Fab Intl. Vol B. Lee et al, IBM, A Fixed Abrasive CMP Model, Proc. CMP-MIC, pp , Santa Clara, CA, Mar et al., Nano-CMOS circuit and physical design, John Wiley and Sons, Inc Chapter 10 and M. Rencher and C. McAndrew, It all begins and ends with Spice, pp , What s Yield Got To Do With IC Design?, EE Times 51