Manufacturing Characterization for DFM

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1 Manufacturing Characterization for DFM 2006 SW DFT Conference Austin, TX Greg Yeric, Ph. D. Synopsys

2 Outline What is DFM? Today? Tomorrow? Fab Characterization for DFM Information Goals General Infrastructure 2006 Synopsys, Inc. (2)

3 Glossary BEOL Back End Of Line process: Contacts and Interconnect Layers Critical Area Circuit area susceptible to a defect of a certain size CAA Critical Area Analysis D 0 (N 0 ) Number of defects per cm 2 DOE Design of Experiments: Variations in a group of Test Structures DUT Device Under Test: A Single Electrical Test Structure FEOL Front End Of Line process: Up to Contacts M/A Layer-to-Layer Misalignment OCV On Chip Variation OPC Optical Proximity Correction: Adjust Rectangles for known litho bias PFA Physical Failure Analysis RET Reticle Enhancement Technology: Broader term, includes phase shifting TEG Test Element Group: TestChip WAT Wafer Acceptance Test For your reference 2006 Synopsys, Inc. (3)

4 Origins of DFM DFM (Design for Manufacture) is not an invention of semiconductor industry marketing managers Design for Manufacture Strategies, Corbett, Dooner, Meleka, and Pym, Addison-Wesley, Towards Next-Generation Design-for-Manufacturability (DFM) Frameworks for Electronics Product Realization, Bajaj, et. al., 2003 IEEE/CPMT/SEMI Intl. Electronics Manufacturing Technology Symposium For your reference 2006 Synopsys, Inc. (4)

5 Key concepts of DFM 70% of cost is established in design phase Protect manufacturing from unreasonable design demands Serial Design-to-Manufacture flow increases cost Semiconductor DFM Management of the design s sensitivity to the manufacturing process Tradeoffs between Manufacturability and Yield RE-Integrated CAD Applying DFM to the Semiconductor Industry, White, Athay and Trybula, 1995 IEEE Intl. Electronics Manufacturing Technology Symposium 2006 Synopsys, Inc. (5)

6 DFM in the Semiconductor Industry DFM is not a foreign concept to us Many components exist as separate pieces DRC Decks and OPC are an example of advanced DFM practice Uniqueness of Semiconductor Industry Rate of Change Manufacturing efficiency Complexity (Kudos for being here!) Design for Semiconductor Manufacturing Perspective, White, Jr., Trybula, and Athay, IEEE Trans. on Components, Packaging and Man. Tech. Part C, VOL. 20, NO. 1, Jan Synopsys, Inc. (6)

7 Why do we need DFM? Manufacturing yields are reducing Yield learning rate is not increasing Yield excursions are increasing Verification, Tape-out, and Mask are becoming prohibitive in cost and time Reducing Predictability Designs are not taking full advantage of nanometer processes (Min. Pitch following Moore s Law, circuit size is not) Trends in Systematic non-particulate yield loss mechanisms and the implications for IC Design, Berglund, SPIE Synopsys, Inc. (7)

8 Design-Manufacturing Chain Functional Specification Schematic Physical Layout DRC (& now LCC) OPC Fracture Mask Wafer Test TCAD Design Manufacturing 2006 Synopsys, Inc. (8)

9 Place and Route and DFM Standard Cells optimized, then placed Cell 1 Cell 2 Cell 1 Cell 2 What are the lithographic implications on both cells? One Proposal: Exclusion regions What interconnection issues arise? Power supply issues? Product Design for Manufacture and Assembly, Boothrod, Dewhurst and Knight, Marcel Dekker, Synopsys, Inc. (9)

10 Example Band-aid DFM Design Rules Via Array Density rules Wide Metal (< 0.8 um is wide ) DFM Recommended Rules Redundant Vias Non-Minimum Contact-Contact spacing in S/Ds Design Intent Marking Layers Today s s Design rules are too complex for effective communication from Fab to Design 2006 Synopsys, Inc. (10)

11 Tomorrow s DFM (not next year s) Functional Specification Schematic Standard Cells Place and Route Physical Layout DRC OPC Fracture Mask Wafer Test Design Optimized / Verified Simultaneously Against Area, Power, Timing, and Yield! 2006 Synopsys, Inc. (11)

12 Tomorrow s DFM Conundrum Why is the yield low? What should it be? How do I fix it? DESIGN DAM MAD Better CAD Tools Require Better Fab Information 2006 Synopsys, Inc. (12)

13 Synopsys circa 2005 Synopsys circa 2006 Which Comes First in DFM? 2006 Synopsys, Inc. (13) Fab Data CAD Designer

14 Eggmen: TestChips for DFM DFM-Capable CAD Tools need silicon calibration Quantified information on yield loss by specific mechanism Statistically relevant sampling Correlation to actual product yield Usable Information, not just data The Key Slide! 2006 Synopsys, Inc. (14)

15 Random Yield DFM Requirements Functional Specification Schematic Standard Cells Place and Route Physical Layout DRC OPC Fracture Mask Wafer Test CAD Yield Entitlement (CAA) Wire Spreading TestChips Critical Area Calibration Yield by Layer Defect Clustering Single/Redundant Via Yield 2006 Synopsys, Inc. (15)

16 2005 ITRS 2005 ITRS: Analyzing Smaller Defects Faster Laura Peters, Senior Editor -- Semiconductor International, 1/1/2006 For your reference 2006 Synopsys, Inc. (16)

Random Yield Characterization Requirements Needs Large Critical Areas D 0 /N 0 by Layer Soft Failure Detection Defect Size Distribution Down to

17 Random Yield Characterization Requirements Needs Large Critical Areas D 0 /N 0 by Layer Soft Failure Detection Defect Size Distribution Down to Critical Feature Sizes Spatial Results (Clustering) Conductive Barrier Layer Yeric, et al., IEEE Infrastructure IP Workshp, Synopsys, Inc. (17)

Soft Via Fail example Close Up of Electrical Fail Map Via Fail without

voltage contrast for one of two fails PFA of site which showed no

2B Vias per wafer (200mm) Test time 40 minutes/wafer Infrastructure for

18 Soft Via Fail example Close Up of Electrical Fail Map Via Fail without voltage contrast Via Fail with voltage contrast Top down SEM showing voltage contrast for one of two fails PFA of site which showed no voltage contrast. 65nm, 8Mb, 3.2B Vias per wafer (200mm) Test time 40 minutes/wafer Infrastructure for Successful BEOL Characterization and Yield Ramp at the 65 nm Node and Below, IEEE IITC 2005, paper Synopsys, Inc. (18)

Random Defectivity PFA Example A 65nm Random and Systematic Yield Ramp Infrastructure

IBM and Synopsys GROUP_NAME Block DIE_ COOR Bin2 FAIL COUNT Row (0-255) Column (0-255)

4 32 33 20 99 DD_CA-RXopen_nest 56 10 108 80 162 4_7 3 158 231 40 225

19 Random Defectivity PFA Example A 65nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array with Integrated Analysis Software, ICMTS 2006, IBM and Synopsys GROUP_NAME Block DIE_ COOR Bin2 FAIL COUNT Row (0-255) Column (0-255) DD_CA-RXopen_iso 49 10_ DD_V3open_nested 53 10_ _ DD_CA-RXopen_nest _ DD_CA-RXopen_semiiso 48 8_ DD_CA-V2stkviaopen 2 9_ _ Synopsys, Inc. (19)

20 Today s Yield Challenges 100% 80% Yield Loss 60% 40% 20% Random Systematic 0% Synopsys, Inc. (20) Technology Node (nm) Source:

21 Systematic Yield DFM Requirements Functional Specification Schematic Standard Cells Place and Route Physical Layout DRC OPC Fracture Mask Wafer Test CAD P&R, STA, Cell Grading Avoid Known Fab Prob s Yield Tradeoff Calc s TestChips Quantified DRs Identified RET weaknesses 2006 Synopsys, Inc. (21)

22 Systematic Yield Characterization Requirements Metal and via printability vs. design rules, by layer Quantify the full process capability on each die Minimum line width at multiple pitches (photo and etch) Key RET issues: End-to-end, minimum area, etc. Opens and shorts as a function of CD, M/A Orientation Effects CMP Density Effects Critical Feature Identification Quantification of Yield as a function of DR (Min, Rec d) Over 8,000 different electrical open/short tests for 65nm! A 65nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array with Integrated Analysis Software, Karthikeyan, et al., ICMTS Synopsys, Inc. (22)

23 Random Systematic Critical Area Critical Feature Must provide quantified yield information to feed next generation CAD 2006 Synopsys, Inc. (23)

24 Parametric Yield DFM Requirements 2006 Synopsys, Inc. (24) Functional Specification Schematic Standard Cells Place and Route Physical Layout DRC OPC Fracture Mask Wafer Test CAD P&R, STA, Cell Grading, Calibrated TCAD Quantified Components of Variation Yield Tradeoff Calc s TestChips DUT Repetition for OCV Parametric DR tests MOS Parasitic

25 Parametric Array OCV Test Block Comprehensive MOSFET Matching as a function of Area Separation Dummy cells Cross-coupling style 2006 Synopsys, Inc. (25)

26 Must Quantify Variation due to Physical Implementation Scanner Astigmatism Optical Proximity Effects Gate Leakage, RF bias 2D Contour Effects, Resist Stress CMP Effects, Active Stress 2006 Synopsys, Inc. (26)

27 Parametric Array OCV Test Block (cont.) Full Active and Poly Linewidth monitoring Isolated vs. dense, densities through forbidden pitches Orientation mid-range density (etch effects) Other components of MOS Variation (permuted with misalignment) Proximal active and poly corners Proximal implant edges Partial S/D contacting 2006 Synopsys, Inc. (27)

28 Parametric Array OCV Test Block (cont.) A/C MOS metrics NAND and NOR Oscillators help decouple NMOS/PMOS issues Enable function provides off-state leakage info Interconnect Loading (easy to compare to extractions) CBCM for direct capacitance RF Design Rules and Characterization 2006 Synopsys, Inc. (28)

29 Parametric Array OCV Test Block (cont.) Circuit-level validation: PLL, VCO, Op-Amp, Converter, Mixer Key device repetition required to mitigate OCV Resistors, MOSFETs, Capacitors repeated every 100µm Requires hundreds of tests in an OCV interaction distance: ~ 1mm Synopsys, Inc. (29)

30 Parametric Circuit/Model Correlation Device models are verified with results designers can trust BGR Op-amps Oscillators Data Converters Other circuits Device and Circuit Variations Offset Bandwidth Timing Variation Noise Cross-talk 2006 Synopsys, Inc. (30)

31 Example 65nm Parametric Characterization Set Characterization Objective 1-D OPC (gate pitch) MOSFET Matching Gate Proximity and Density Layout-based parasitic variation Interconnect Capacitance POLY and ACTIVE Corner Rules Implant Edge Rules Circuit-level variability Sub-total of Experiments Synopsys, Inc. (31)

32 Other areas of Systematic/Parametric Yield Loss Cross-talk Inductance Reflectance Noise Heat dissipation IR drop SEU Reshaping the SoC Power Design Flow, Yang and Lin, EEdesign.com 2006 Synopsys, Inc. (32)

33 Yield Solution Infrastructure 1. Test Chip 2. Data Analysis Software 3. Incoming Design Analysis 4. Product Limited Yield Characterization 5. Silicon Validation 2006 Synopsys, Inc. (33)

34 Focused Test Chip Analysis for Reduced Time to Results Increased amount of data from each 45nm wafer will be overwhelming (Terabytes per month at 65nm) Need for specialized, automated data reduction that is design aware and analysis requirement aware Set-up time lags are not tolerable for real time DFM To achieve this successfully, both the TEG features and the analysis software features must be holistic 2006 Synopsys, Inc. (34)

35 Where Does Test Fit In? With the very deep micron technologies, the impact of test is widening from a screening technology to one that helps debugging the first silicon, to a basis for repairing chips during manufacturing and in the field, to an infrastructure for diagnosis and fault tolerance. DATE Program, Synopsys, Inc. (35)

36 Summary Test is the key link between design and manufacturing (product and scribe) All CAD tools need yield info quantified in silicon for successful DFM Test / Test Chip infrastructure must be readdressed to keep up with vast information demands of DFM VLSI level design complexity Terabytes of data per wafer Required integrated data reduction 2006 Synopsys, Inc. (36)

Bridging the Gap between Dreams and Nano-Scale Reality

Bridging the Gap between Dreams and Nano-Scale Reality Ban P. Wong Design Methodology, Chartered Semiconductor wongb@charteredsemi.com 28 July 2006 Outline Deficiencies in Boolean-based Design Rules in