Design for Reliability --

Transcription

1 Design for Reliability -- From Self-Test to Self-Recovery Tim Cheng Electrical and Computer Engineering University of California, Santa Barbara

2 Increasing Failure Sources and Failure Rates design errors soft errors random defects parametric variations SEU Temperature (C) On-Die Temperature variations

3 Harder to Design Reliable Chips First-silicon success rate has been dropping ~30% for complex (according to an ASIC vendor) Pre-silicon logic bugs have been increasing at 3X-4X per generation for Intel s processors Yield has been dropping for volume production and takes longer to ramp up the yield IBM s 8-core Cell-Processor chips: ~10-20% yield (July 2006) Better than worst-case design resulting in failures w/o defects Increase in variation of process parameters with scaling Worst-case design getting way too conservative

4 Design for Reliability Systems must be designed to cope with failures Efficient silicon debug is becoming a must Design for debugging would become necessary Must have embedded self-test for error detection For both testing in manufacturing line and in-the-field testing Both on-line and off-line testing Re-configurability and adaptability for error recovery make better sense Using spares to replace defective parts Using redundancy to mask errors Using tuning to compensate variations

5 From Test to Recovery/Reconfiguration Some Examples Memory: BIST BISD BISR a common practice On-Line sensing and tuning On-chip leakage sensing Leakage control (adaptive body bias) On-chip thermal sensing Cooling adjustment On-chip delay sensing Performance tuning Analog/RF/High-speed IO components Digitally-assisted analog design and test Multicore system with spares

6 Analog Circuit Design Trade-offs Power dissipation vs. speed and precision trade-offs feature size ratio of power dissipation of analog to digital E.g., a 12-bit ADC consumes as much energy as switching 300K gates in 90nm technology Source: B. Murmann, IEEE Micro, March-April 2006.

7 Digitally-Assisted Analog Design Leverage powerful digital computing capability Pros: improve precision and/or speed of analog circuit without dramatically increasing its power dissipation Use a less-precise/lower-performance analog circuit plus a digital processor which: measures errors of analog block then compensates its errors and tune its performance Analog Input Measure Error Relaxed Analog circuit Complex Digital processor Adjust/ Compensate Analog/Digital Output

8 Example: Pipelined ADC ADC suffers from nonlinearity due to capacitor mismatch, finite opamp gain, etc. System output is down-sampled, and compared with signal from slow-but-accurate ADC Update tap values in digital FIR filter to minimize the errors of inaccurate ADC Analog Digital Input TH Inaccurate ADC Digital Filter Output Down Sample N Slow-but- Accurate ADC Adaptation ε N

9 Example: RF Polar Transmitter VCO-gain and loop linearity in PLL are critical to accuracy of the polar modulator Adjust capacitance in VCO and current in CP to calibrate VCO-gain and tune loop-gain Polar Modulator Ampitude Digital Coordinate TX Data Rotation Phase Modulator Ref PLL PA RF Out TX Data Divider FD Ref Frequency Measurement Alignment Algorithm CP Analog Digital LPF VCO TX Out

10 Example: Adaptive Equalizer in High- Speed Serial-Link (HSSL) Receiver EQ in RX is realized by a FIR filter Tap coefficients (C 1, C 2, ) in EQ are adjusted by Adaptation engine (A) (B) Delay Delay EQ Input C 1 C 2 C EQ 3 Output (C) Channel - induce ISI (B) EQ (C) CDR Clock (D) (A) (B) (C) Adaptation ε RX (D)

11 Observability Problem of Embedded Analog Blocks Direct observation of analog signal is problematic Self-compensation by digital block causes masking of defects in analog block SOC Hard to observe & Fault masking Analog Input Relaxed Analog circuit Analog Output Next Stage Measure Error Adjust/Compensate Complex Digital processor

12 Digitally-Assisted Analog Testing Proposed solution: Applying specific stimulus to analog block and analyzing the digital calibration and adaptation results stored in digital block for fault detection and diagnosis Analog Input/ Test Stimulus Measure Error Relaxed Analog circuit Complex Digital processor Adjust/ Compensate Analog/Digital Output Analyze Digital Calibration/Adaptation Result Digitally Assisted Analog Design Digitally Assisted Analog Testing

13 Fault Detection for Pipelined ADC & PLL of RF Transmitter Analyze tap values in the digital filter of ADC Analyze calibration data in self-alignment unit of PLL Capture calibration results Input TH Analog Digital Inaccurate ADC Digital Filter Output TX Data Divider Frequency Measurement Analog Digital TX Out Down Sample N Slow-but- Accurate ADC Adaptation ε N FD Alignment Algorithm CP LPF VCO Ref

14 Existing Methods for Testing Adaptive EQ in HSSL RX External scope to capture EQ output via access point Signal integrity is degraded due to extra loading On-chip waveform monitor Increase circuitry complexity and device cost Signal RX EQ Clock Equalized Signal CDR Data Eye-diagram Drive Circuit On-Chip Monitor Access Point

15 Testable Design for Adaptive EQ Insert extra DfT circuitry: FF chain to store digital tap coefficients c i A switch and a pattern generator to replace the slicer output DfT circuitry are all digital Input EQ Output CDR Clock Adaptation ε Pattern Generator FF FF C i Scan Out

16 Experiment: Detecting Defects in a 5-Tap Feed-forward EQ Illustrating 3 types of single-fault instances: Fault (a): Stuck-at faults at one of the 5 taps Fault (b): 20% gain error at one of the 5 taps Fault (c): 10% DC offset due to nonzero common input EQ Input Main Cursor Tap D D D D C 5 Fault(a) C 1 C 2 C 3 C 4 EQ Output 80% Adaptation Fault(b)

17 Fault Masking of Fault (a) if Detection is Made by Examining EQ Output The difference in eye-diagrams between fault-free and faulty EQ is small η = EQ Input Main Cursor Tap D D D D Fault-Free EQ C 5 1-bit period C 1 C 2 C 3 C 4 η = Fault(a) Adaptation EQ Output Faulty EQ

18 Testing Faults (a) & (b) by Proposed Method EQ Input Fault(a) Test Fault (a): with stimuli AI(1) & DI Test Fault (b): with stimuli AI(2) & DI Locate the fault in the 1 st tap D D D C 1 C 2 C 3 80% Fault(b) C 4 D Adaptation C 5 PE Card ATE DSP AI EQ Adaptation c i DUT CDR ε Clock DI Pattern Gen AI (1) AI (2) AI (3) DI Tap Number 1-bit period repeat higher level Tap Weight Without Stuck-At Fault With Stuck-At Fault Tap Number Tap Weight 1 Without Gain Error 0.8 With Gain Error Tap Number Tap Weight 1 Without Gain Error 0.8 With Gain Error Tap Number Stimuli : AI(1) & DI Stimuli : AI(1) & DI Stimuli : AI(2) & DI

19 From Test to Recovery/Reconfiguration Some Examples Memory: BIST BISD BISR a common practice On-Line sensing and tuning On-chip leakage sensing Leakage control (adaptive body bias) On-chip thermal sensing Cooling adjustment On-chip delay sensing Performance tuning Analog/RF/High-speed IO components Digitally-assisted analog design and test Multicore system with spares

20 Could 10-20% yields for Cell processors lead to problems for Sony PS3? * With standard SiGe single-core processors, IBM can achieve yields of up to 95%. But with a chip like the Cell processor, you're lucky to get 10 or 20 percent." If you really want to be focused on reliability and up-time availability, you can design one of these chips to self-detect. You can ship it with eight cores working, blow one of them, and from a user perspective you would have self-healed it in the field. With such systems in place, yields could conceivably increase in a best-case scenario to 40% - still significantly lower than the 95% yields that IBM and others enjoyed during the single-core, "one-byone" era. * Electronic News 7/7/06 and TGDaily 7/14/06, Interview of Tom Reeves, VP of semiconductor and technology services at IBM

21 Need New Test Strategy and Yield Analysis for Multi-core Systems with Spares Understanding impact of core yield, test quality and spare scheme on final system yield and cost How many spare cores should be included? How many working spares in a shipped chip would be sufficient? What is the required core defect quality to achieve required system reliability? Can we skip burn-in and repair infant mortality in the field? Intel 80-tile network on chip (ISSCC07) IBM CELL Processor (8 SPE) (ISSCC05) Sun Niagara (8 Sparc cores) (IEEE Micro 2005)

22 M-out-of-N-core System Definition: A system that has totally N cores and requires at least M defect-free cores for operation Cell for PS3 is a 7-out-of-8-core system System effective yield is a function of: core yield number of active cores (M) total number of cores (N) number of partitions of a core defect coverage Finer spare granularity, better spare utilization but lower core yield B1 B3 B2 Core 1 Core 2 B4 partitioning requires additional control and configuring logic, thus increasing core area

23 Scenarios for Consideration 1. Manufacturing testing and repair in the manufacturing line Screening defective chips from shipping Improving effective yield 2. Self-testing (on-line or off-line) and repair in the field Covering defects missed by manufacturing testing and new failures in-the-field Reducing service cost

24 Yield Model for One Core Raw yield of a core, Y Ci, is a function of area, defect λ A density, and clustering factor (α): y i (A, λ, α ) = ( 1 + α c ) α is the degree to which defects are clustered α Prob (core C i is defect free C i passes testing): Y Ci Prob(C i passing testing)=y Ci y' C i A λ Ω ( A, λ, α, Ω ) = (1 + ) α α * de Sousa and Agrawal, DATE 2000 * Kuo and Kim, Proc. of IEEE 1999

25 Example: 1-out-of-2-Core System A chip could be shipped if: Default core C1 passes testing: Prob=y C1 C1 fails testing and spare C2 passes: Prob= (1-y C1 )xy C2 A shipped chip is indeed a working chip if: C1 passes testing and indeed fault-free: Prob=y C1 C1 fails testing, C2 passes & indeed fault-free: Prob=(1-y C1 )xy C2 Effective yield (Probability of a chip that can be shipped and indeed working): y C1 +(1-y C1 )xy C2 The reject ratio can be easily calculated

26 Effective Yield for M-out-of-N System ), ( ) ( ) ' (1 ) ',,, ( 0 i M N P y y i M y y M N y i M C i C M i C C e = = j C j S C S i j y y j S i S P ) ( ) ' (1 ), ( = = Probability that (M-i) out of M default cores are fault-free Probability that at least i out of (N -M) spares are fault-free.

27 System Yield vs Core Yield (9-out-of-N-core Systems) Aug. 14, 2007 IC-DFN Core yield=80% Core yield=70% Core yield=60% Core yield=50%

28 Example: 3-out-of-6-Core System Sample assumptions: Manufacturing test defect coverage: 100% Core yield: 0.65 Effective chip yield: 88.2% Shipped chips with S remaining spares default cores C1 C2 C4 C5 (A) = 8.5%, (B) = 27.7%, (C) = 37.2%, (D) = 26.6% spares C1 C2C3 C4C5C6 C3 C1C2C3 C6 C4C5C6 C1C2C3 C4C5C6 total 3 cases C1C2C3 C4 C4C6 C1C2C3 C4C5C6 C1C2C3 C4C5C6 total 6 cases C1C2C3 C4C5C6 C1C2C3 C4C5C6 C1C2C3 C4C5C6 total 7 cases 3 remaining spares 2 remaining spares 1 remaining spare No remaining spare (A) (B) (C) (D) Should we ship chips without remaining spares?

29 Scenarios for Consideration 1. Manufacturing testing and repair in the manufacturing line Screening defective chips from shipping Improving effective yield 2. Self-testing (on-line or off-line) and repair in the field Off-line BIST or on-line checking for fault detection in the field Covering defects missed by manufacturing testing as well as new failures occurred after chip shipment Reconfiguration in the field

30 Should We Ship Chips Without Fault-Free Spares? Not shipping them reduces effective yield and, thus, increases unit manufacturing cost Shipping them increases field return rate and, thus, increases unit service cost Factors for consideration: Core failure rate in the field r = cost of replacing/servicing an irreparable chip in the field manufacturing cost per shipped chip Number of fault-free spares

31 Core Failure Rate in the Field Weibul distribution model for a core s lifecycle*: 2 parameters: shape (β) & scale (λ) Scale parameter: the time at which 63.2% of units will fail Shape parameter: β (; λ, β t β 1 f t ) = ( ) < 1, infant mortality λ λ = 1, grace period > 1, breakdown period Failure rate (f) Infant Mortality Grace Period Time (t) Breakdown Period * Carulli and Anderson, IEEE Design & Test Computers March/April 2006

32 Failure Rate for M-out-of-N Systems Core field-failure-rate over the time t: F C = y y' C C e ( t β /λ) Probability of a M-out-of-N chip NOT failing at time t: M RM out of N( t) = PS ( i) i= N 0 R( i, t) probability of a shipped chip with i spares passing test probability of a chip with i available spares not failing at time t

33 Yield Analysis Framework for Multicore Systems with Spares We developed an analysis framework that can be used to: Calculate effective system yield Determine the number of spares for cost minimization Analyze feasibility of eliminating burn-in for multi-core systems Determine whether to ship chips with no or few working spares High-quality testing (both manufacturing testing and infield testing) remains one of most critical requirements for multi-core systems

34 Conclusions Systems must be designed to cope with failures Cost-effective embedded self-test will replace existing manufacturing test methodologies for heterogeneous SoC/SiP Post-silicon tuning/calibration/reconfiguration is becoming promising, and necessary, for Si nano systems