In the previous chapters, efficient and new methods and. algorithms have been presented in analog fault diagnosis. Also a
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1 118 CHAPTER 6 Mixed Signal Integrated Circuits Testing - A Study 6.0 Introduction In the previous chapters, efficient and new methods and algorithms have been presented in analog fault diagnosis. Also a reconfigurable hardware model to test different analog circuits is developed. New methods and approaches have to be developed in mixedsignal systems. In this chapter a brief introduction to different methods available to test mixed signal systems is presented. Also proper illustrations using some popular mixed-signal circuits like ADC and Software Defined radio (SDR) are discussed. Mixed Signal technology combines analog and digital signals together. This combination results in devices which are powerful in performance and have huge potential. A mixed signal circuit can be defined as a circuit consisting of both digital and analog elements. A mixed signal system processes analog information into digital form or processes digital information into analog information or both. Integrated circuits with analog, digital and mixed signal circuits are now fabricated on the same substrate, thus reducing the cost of packaging and assembly.
2 119 The continuous decrease in the cost to manufacture a transistor, mainly due to the exponential decrease in the CMOS technology minimum feature length, has enabled higher levels of integration and the creation of extremely sophisticated and complex designs and systems on chip (SOCs). This increase in packing density has been coupled with a cost-of-test function that has remained fairly constant over the past two decades. Many reasons have contributed to a fairly flat cost-of-test function over the past years. Although transistor dimensions have been shrinking, the same cannot be said about the number of input and output operations needed. In fact, the increased packing density and operational speeds have been inevitably linked to an increased pin count. First, maintaining a constant pin count bandwidth ratio can be achieved through parallelism. Second, the increased power consumption implies an increased number of dedicated supply and ground pins for reliability reasons. Third, the increased complexity and the multiple functionalities implemented in today s SOCs entail the need for an increased number of probing pins for debugging and testing purposes. All the abovementioned reasons, among others, have resulted in an increased test cost. Testing high-speed analogue and mixed-signal designs in particular, is difficult task. Also observing critical nodes in a system is becoming increasingly challenging. As the technology keeps scaling,
3 120 especially past the 90 nm technology, metal layers and packing densities are increasing as a function of signal bandwidth and rise times extending beyond the Gigahertz range. Viewing tools such as wafer or on-chip probing are no longer feasible since the large parasitic capacitance loading of a contacting probe would dramatically disturb the normal operation of the circuit. On the other hand, the automatic test equipment (ATE) interface has become a major bottleneck to deliver signals with high fidelity, due to the significant distances the signals have to travel at such operational speeds. In addition, the ATE cost is exploding to keep up with the ability to test complex integrated SOCs. Embedded test techniques, benefitting from electrical proximity, area over head scaling and bandwidth improvements, lead to at-speed testing, therefore constitute the key to an economically viable test platform. When test solutions are placed on the chip, they are known as a structural test or built-in self test (BIST). The test solutions can also be on the board level or as part of the requirements of the ATE. Each solution will entail verification of signal fidelity and responsibility to different people (the designer, the test engineer or the ATE manufacturer), different calibration techniques and different test instruments, all of which directly impact the test cost, and therefore the overall part cost to the consumer. It is important to point out that there is a lot of effort on placing more components on the board, as well as trying to combat the exploding
4 121 costs of big ATE systems through low-cost ones, specifically to combat the volume or production testing of semiconductor devices. Most complex mixed-signal devices include at least some stand-alone analog circuits that do not interact with the digital logic at all. Thus, the testing of op amps, comparators, voltage references, and other purely analog circuits must be included in mixed-signal testing. Digital design is the most predominant in integrated chip technology because of its small size, low power and reliability. Invariably all the digital technology will have some analog components. This is because signals emanating from storage media, transmission media, and physical sensors are basically analog. Moreover, digital systems may have to output analog signals to actuators, displays, and transmission media. Clearly, the need for analog interface functions like filters, analogto-digital converters (ADC s), phase-locked loops, etc., is inherent in such systems. The explosion in telecommunications, consumer and automotive electronics industry has resulted in more and more mixed signal devices being designed. The integration of digital and analog components on the same chip is done to improve performance, reduce the size and cost of fabrication. This type of mixed signal design has thrown new challenges in testing these circuits. One possible way of testing mixed signal circuits is to test separately the digital system and the analog system. The
5 122 increased integration of circuits into a single semiconductor die is one of the most challenging aspects of mixed-signal test engineering. 6.1 Types of Analog and Mixed-Signal Circuits Some Analog circuits are Operational Amplifiers, Active or passive filters, comparators, voltage regulators, analog mixers, and analog switches. A simplest mixed signal circuit can be CMOS analog switch. In this circuit the resistance of a CMOS transistor is varied between high and low impedance under control of a digital signal. Another simple type of mixed signal circuit is the programmable gain amplifier (PGA). The PGA is used at the front end of a mixed signal circuit to allow for a wide range of input signal amplitudes. The most common circuits that can truly be considered mixed signal devices are analog to digital converters (ADC s) and digital to analog converters (DAC s). An ADC is a circuit that samples a continuous analog signal at specific points in time and converts the sampled voltages or currents into a digital representation. This digital representation is called a sample. A DAC is a circuit that converts the digital samples into analog signals. These two circuits ADC and DAC form the interface between the real world signals and the digital part. Another complex mixed-signal system is a digital cellular telephone. The cellular telephone consists of many analog, digital and mixed-signal circuits working together in a complex fashion. The cellular telephone user interfaces with the keyboard and the display to answer
6 123 incoming calls or to initiate the outgoing calls. The control microprocessor is used to handle the user interfaces. The various circuit blocks of the cellular telephone may be grouped into a small number of individual integrated circuits called chipsets. The test engineer must be ready to test the individual pieces of the cellular telephone or to test the telephone as a whole. 6.2 Testing The digital part of the mixed signal system can be tested with the several standard methods available. The digital testing is aided by software for automatic test pattern generation, scan chains and built in self test methods. The digital testing domain is mature, efficient and cost effective. The testing of analog parts of the mixed signal set up is more complex as the fault models are not well established. Also the statistical distribution of analog faults is generally not known with precision. This makes prediction of faults in a test set difficult. The testing of the analog parts of the combined mixed signal system is thus not well understood. The test sets are typically based on the designers experience and specifications of the circuit. A typical test set up is shown in Figure 6.1 below.
7 124 Figure 6.1: Mixed-Signal Device Test Set up As seen from the figure, digital inputs are applied to the digital block. Signal generator is used to excite the analog portion of the mixed signal circuit. The signal applied can be a dc signal, sinusoidal signal, square wave or can be a random signal with a known probability distribution function. The output response of the system is measured with a RMS power meter. The operating range is narrow band which is tunable. Sinusoidal inputs are generally used to test linear analog circuits such as amplifiers, data converters and filters. The output magnitude and phase are measured as a function of the input frequency. Also non deterministic input signals can be used as inputs to test the analog circuits transfer characteristics Limitations The approach discussed in the earlier section is too straight forward and many factors limit such type of approach. The limitations are:
8 125 Efficient development of bug-free test sets to check for the functionality of the analog components. This should be at-speed operation of the entire system. At- speed testing depends on the interactions between the analog and digital portions of the chip, which is not generic. The testing is very intensive and decides the time to market of the system. Generally the testing of the analog part of the mixed signal system is done after the design is complete. The main reason for this is the absence of a comprehensive CAD test tool. To realize a design which satisfies the given specifications, the system has to be tested number of times, which require changes in the design. In contrast the digital design is fully automated and CAD test tools are available which generate test patterns to test the prototypes of the design. The circuit can be tested at the register transfer level or at the gate level. The standard test methodologies for testing digital circuits are simple and consist of largely scan chains, automatic test pattern generators and are generally used to test catastrophic faults, processing and manufacturing errors. The digital testing consists of cost effective digital BIST. Analog testing is done to meet the design specifications under process variations, mismatches and loading effects. Digital circuits testing is binary i.e. either faulty or not faulty. In analog circuits the
9 126 circuit behavior is categorized into nominal and uncertainty range. The deviation from the nominal is dependent on the type of application and can be ±0.1% from the nominal. The Figure 6.2 shows the functional behavior of the digital and analog circuits. Figure 6.2: Functional Behavioral description (a) Digital (b) Analog Efficient development of complete and full testing of the analog circuits in a mixed signal system can be cost wise prohibitive. To illustrate take an example of a 13-bit ADC. To measure its integral nonlinearity (INL) it requires locating 8192 (2 13 ) input voltages. This large number of inputs for testing takes lot of time. To expedite the process of testing parallel test stations have to be used. This increases the cost of testing a mixed-signal system. This increases the production cost and also the time to market. It is desired to diagnose all faults at a low cost and in a very short time. In some cases the inputs to the analog components may not be accessible to the test engineer. One solution to this problem is to bring the required number of test nodes to the package pins. But this has a main disadvantage, as the testing probe loading effects can degrade the measurements made. Another solution to increase the testability is to
10 127 add extra components to access the input and outputs of the analog system. Even though this method increases the testability of the system, it may increase the parasitic effects and degrade the performance of the circuit in some cases. 6.3 Analog and Mixed Signal BIST The challenges faced by Mixed-signal BIST designers are many, when compared to the digital BIST. The analog BIST sometimes lack robust traceability, the use of un-calibrated on-chip analog stimulus and measurement circuits throws doubts into the accuracy of the measurements. An analog BIST designer must define a calibration strategy for the analog circuits. Another problem with the DAC and ADC based BIST is that the on chip instrumentation is often inferior to types of programmable equipment available on the ATE equipment. Finally the circuit overhead required to implement an efficient BIST has to be looked into. For example in ADC or DAC circuits, a processor is needed to generate sine waves to the DAC. This processor may be used to collect samples from the ADC. So the BIST operation must perform FFT on the results, evaluating signal-to-noise ratio, fundamental amplitude, distortion components etc. To perform such wide range of operations a powerful DSP processor is needed. The Input stimuli to a mixed- signal can be from a ROM or DSP circuitry, rather than an LFSR. The main aim of these approaches is to keep the hardware overhead to minimum. This is done by reconfiguring
11 128 and reusing the circuitry on the chip during the test mode. In the test mode the outputs of the analog block is measured by routing the analog input pins, as shown in Figure 6.3. Figure 6.3: BIST Implementation The outputs of the analog input block are embedded on the chip as such are not accessible. During the test mode, the outputs are measured after converting the signals into digital form. This is done by the ADC present on the chip. The outputs are captured and stored, by using the built in logic block observers (BILBO). The stored signals are then fed in to the multiple input signature register (MISR). The MISR performs the task of on chip data compaction using signature analysis.
12 129 Now the same procedure used in analyzing the on chip digital response is used to analyze the analog test results also. This is possible because the analog signals have been converted into digital form by the on chip ADC. The response of the analog block is used to diagnose the circuit for faults. One of the methods used are signature analysis of the digitized response of the analog block. Another method is to compare the output response of the analog block with the known fault free response of the system. Thus the fault status of the analog block is decided. The nominal state or the fault-free state of the analog block is stored in the ROM. The signals stored in the ROM can be pre processed or post processed depending on the functional characteristics of the analog blocks. A BIST circuit can also be used to detect abnormal changes in the power supply current. This circuit can be used to detect the upper and lower limits of the input peak current. Then the BIST will generate an appropriate digital signal to indicate the drastic changes in power supply current. The BIST can also be made to indicate faults. The generic methods have been presented in mixed-signal integrated circuits testing [123]. The scan path method in association with BIST is generally used to test digital circuitry. The analog cell test strategy adopted here is based on the evaluation of the transfer function of the cell under test by transient response techniques. The response of the cell to the transient response completely specifies the functionality of
13 130 the circuit. This results in minimum scan path data loading, simple test vector generation and the ability to directly propagate these test vectors. The proposed method is shown in Figure 6.4 below. Figure 6.4: Mixed Signal Model with interface scan testability As shown in the figure above, special interface scan paths are provided to access analog test points. The system is partitioned into digital and analog parts and an interface is provided between the scan path and the analog part of the mixed-signal IC. 6.4 Testing of Mixed-Signal Systems Testing of some mixed-signal systems is illustrated in this section. Some important mixed-signal systems are the ADC and Software Defined Radio (SDR) Testing ADC The IEEE Std [124] is the new standard for ADC terminology and testing. This strongly relies on the frequency domain techniques. Frequency domain techniques tend to be favored in
14 131 manufacturing because two records of data can produce a robust characterization of the data. Analogue-to-digital converters (ADC) are mixed-signal functions that are frequently used to create an interface between sensing and actuation devices in industrial control, transportation, consumer electronics and instrumentation industries. They are also used in the conversion of analogue voice and video data in the computing and communications. In control applications, the trend is towards medium speed ( khz) and high resolution (>16 bits) and the test requirements are focused towards linearity testing. In communications applications, trends are similar. However, dynamic performance tends to be critical, especially in voice processing applications. Consumer goods are another important application where a high conversion speed (up to hundreds of megahertz) and low-to-medium resolution (8 12 bits) are the norm. For test engineers, optimization of the test programs for verification of key specifications. The most popular method of testing ADC is based on DSP. This is done by injecting the DSP with a known stimulus and then the output which is digital is processed. The output data is processed using FFT, thus extracting the dynamic specifications of the system. A generic test set up is shown in Figure 6.3. A suitable stimulus is applied to the ADC under test by using a suitable test access
15 132 mechanism. The test stimulus generator block corresponds to one or more sine waves, arbitrary waveforms or pulse generator(s) depending on the type of test to be executed. Generally, the response is captured for processing in a test sink. Figure 6.5: ADC Test Set Up As shown in the Fig. 6.5, the conventional ADC test set-up has a test source and test sink. These are part of the external ATE and are centrally controlled. The ATE interfaces with the IC via a device interface board. The input output pins and the internal interconnections of the IC are used as test access mechanism. But this may not be always possible. Generally some other means of accessing the test points is provided. These test access points have to be incorporated into the chip during early stages of the IC design. This method is particularly helpful in cases where there is a limited pin count or the ADC is deeply embedded in to the SOC. Systematic design methodologies that increase test access, referred to as design-for-testability (DFT), are standardized at various system levels. The IEEE standard , also known as boundary-scan,
16 133 supports digital IC and board level tests [125]. Its extension to analogue and mixed-signal systems, IEEE standard , adds an analogue test bus to increase access to analogue IC pins and internal nodes [126]. The ADC performance is verified by two methods: i) Static performance parameter Test and ii) Dynamic performance parameter test. The ADC performance is verified in terms of the static performance parameters. This is done by computing the transfer function. There are two popular methodologies Feedback-Loop test methodology and the Histogram testing methodology. In the Feedback-Loop test methodology a feed back loop is incorporated into the ADC to force the input voltage to oscillate around a desired code transition level. At the test source side an analog integrator is employed to continuously integrate the positive or negative reference voltage. This is done to generate the stimulus. The reference voltage to integrate is toggled depending on a comparison result between the A/D converter s output code, C and a set desired output code, D, after each conversion. If C < D, the positive reference voltage is connected to the analogue integrator to set a positive slope in the test stimulus. If C > D, the negative reference voltage is chosen to obtain a negative slope in the test stimulus. Once the input stimulus has reached the desired code transition level T [D], the feedback from the digital comparator enforces oscillation
17 134 around T [D] at the converter input. Measuring the average voltage at the ADC input yields the value of the particular code transition level. In the Histogram test methodology, the ADC code transition levels are determined through statistical analysis of the converter activity. A periodic stimulus is applied to the input. The histogram code counts for an integer number of input wave form periods are computed. There are two types of histograms used, based on the test stimuli employed. The first one is called ramp histogram or linear histogram and the second is known as sine-wave histogram or dynamic histogram. The ramp histogram is calculated for linear triangular waveform and the sine-wave histogram is collected for a sinusoidal input waveform. The Figure 6.6 shows the two types of Histogram methods. Another method is the dynamic performance parameter testing is to identify the signals components at the ADC output. In most of these parameters the transformation from the time domain to frequency domain is required to compute performance parameters. There are two types of methodologies used. These are: (a) Frequency Domain test methodology and (b) Sine wave Fitting test methodology.
18 135 Figure 6.6: Histogram generation (a) Linear and (b) Sine wave Testing of Software Defined Radio (SDR) A Software Defined Radio (SDR) technology facilitates implementation of some of the functional modules in a radio system such as modulation/demodulation, signal generation, coding, and link layer protocols in software. A SDR is required to have elements of reconfigurability, intelligence and software programmable hardware built into it [127]. A software radio system can be viewed through the aspects of hardware, software, application and user [128]. The analog parts of SDR are subjected to variable specifications like, dynamic range and signal-to-noise ratio for the ADC, automatic gain control, selectivity and linearity for the channel-select filter [129]. A Software Defined Radio (SDR) is a good example of a mixedsignal system. It consists of a digital subsystem and an analog
19 136 subsystem. The analog functions are an antenna, RF Filtering, combination of radio frequencies, pre amplification, power amplification and reference frequency generation. The Figure 6.7 shows the ideal SDR architecture. As seen from the figure the analog conversion stage is close to the antenna. Also this is prior to the power amplifier in the transmitter and after the low noise amplifier in the receiver. The separation of carriers and up-down frequency conversion to base band is performed by the digital block. Also the channel coding and modulation functions are performed digitally at base band by the same processing resources. Figure 6.7: Ideal SDR Architecture Conventional radio communication systems typically target one specific region of the available radio spectrum for transmitting wanted
20 137 signal information or receiving this information. These radio communications may span a wide range of frequencies but can process only one radio channel at a time. The software defined radio concept seeks to avoid this limitation by digitally processing wide allocations of spectral bandwidth containing multiple signals of interest. The conventional radio communication systems are usually inflexible in the modulation formats and associated signal band widths that can be accommodated. For example a communication receiver allows reception of SSB, DSB or AM but is incapable of processing digital modulation formats such as DQPSK, PSK, QAM, OFDM or CDMA. The SDR overcomes these limitations by using digital techniques. Some key desired features of the SDR are: Ability to process multiple radio signals at different frequencies. Ability to process signals at multiple non contagious radio spectrums like medium wave, short wave, HF, VHF etc. Ability to adjust to any modulation format. Ability to process signals which belong to different modulation bandwidths and data rates in parallel. The signal bandwidth can be defined by the software present in the digital domain. The performance is enhanced by just upgrading the software, without loss of service.
21 138 SDR is a technology, which implements both analog and digital systems and thus, there are more challenges in the testing of these devices. 6.5 Conclusions In this chapter a brief discussion of the issues in mixed-signal system is provided. Elaborate test methods in mixed signals are discussed. Also BIST for mixed signals has been dealt with in detail. The detailed testing methods of ADC have been presented. A brief discussion about the Software Defined Radio is also presented.
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