On-Chip Automatic Analog Functional Testing and Measurements

Transcription

1 On-Chip Automatic Analog Functional Testing and Measurements Chuck Stroud, Foster Dai, and Dayu Yang Electrical & Computer Engineering Auburn University from presentation to Select Universities Technology, Inc. (SUTI) May 26, 2005

2 The testing problem Outline Manufacture & system testing and cost Built-In Self-Test How does it work and how well Digital vs. analog testing Analog functional testing Measurements vs. fault detection BIST-based functional measurements Our approach vs. others Products & applications 5/26/05 Auburn University SUTI Presentation 2

3 The Testing Problem 2000 International Technology Roadmap for Semiconductors (by the Semiconductor Industry Association - SEMATECH) predicted by 2014: Test machines will cost more than $20M each! Many people say we are already there It will cost more to test a transistor than to manufacture it! Many people say we are already there Testing cost > 50% of product cost 5M-100M transistors on a chip 1 faulty transistor faulty chip Built-In Self-Test (BIST) is the most likely solution Analog BIST is needed for mixed-signal systems Fault diagnosis is needed with BIST Methods needed for automatic implementation of BIST 5/26/05 Auburn University SUTI Presentation 3

4 Manufacture Testing Where are the $20M testers? ¾ Wafer testing Ink dot defective chips Typically not done for RF analog devices 9 Too costly in time & equipment Package only good chips Eliminates packaging defective parts 9 Packaging costs can be high ¾ Package testing & handling defects Burn-in testing for infant mortality Packaging ¾ Board testing Assembly 5/26/05 & handling defects Auburn University SUTI Presentation 4

5 System Testing Manufacture system-level test Unit & system testing Defects due to assembly More customized testers specific to system System-level testing in the field Typically done periodically for High reliability systems High availability systems Done nightly for telephone switching systems Special system hardware/software needed Cost is in system design & development effort 5/26/05 Auburn University SUTI Presentation 5

6 The Testing Problem (continued) Automatic Test Equipment (ATE) cost is increasing High-speed testing needs more expensive ATE Chips are operating at higher speeds Longer test sequences for more complex chips Product testing goes on long after design is done Cumulative testing cost must be considered Cost of fault location/identification and repair Factor of 10 increase in cost Generally accepted Sun Microsystems says multiplier is greater than 10 for complex systems Cost per Fault $ $1000 $100 IC Test Board Test System Test Field Test 5/26/05 Auburn University SUTI Presentation 6 $10 $1

7 Digital vs. Analog Testing Digital testing is defect oriented Test development based on fault models that Attempt Attempt to accurately reflect behavior of defects Are Are computationally efficient for fault simulation Analog testing is specification oriented Functional test based on specifications Linearity, frequency response, signal-to to-noise ratio Recent attempts made in defect oriented testing Difficult Difficult to determine if a circuit is faulty or just outside of nominal operation range Chance of throwing away good product Functional testing is needed to compensate for analog circuit operational variation 5/26/05 Auburn University SUTI Presentation 7

8 Other Mixed-Signal BIST LFSR/accumulator (Stroud, 1987) LFSR/SAR (Ohletz( Ohletz,, 1991) Oscillation (Kaminska( Kaminska,, 1996) OPMAX later bought out by Fluence Multi-waveform/accumulator (Stroud, 1996) Histogram (Frisch, 1997) Tektronix Later Later offered by Logic Vision? Multi-waveform/accumulator (Stroud, 2001) FFT (Emmert( Emmert,, 2004) 5/26/05 Auburn University SUTI Presentation 8

9 Digital System Inputs Digital System Outputs BIST for Mixed-Signal Systems Digital circuitry tests analog circuitry Minimize area & performance penalty to analog circuitry Parameterized models (VHDL or Verilog) Automatic synthesis into any mixed-signal system BIST Start BIST Done Pass/Fail Digital Circuitry System Function Mux DAC TPG ORA Test Control System ADC Function Analog Circuitry Analog Circuit Analog Circuit Analog MUX Analog System Outputs Analog System Inputs 5/26/05 Auburn University SUTI Presentation 9

10 BIST for Mixed-Signal Systems Multiple BIST sequences with analog loopbacks Pass/fail results indicate location of faulty analog circuitry Location & number of analog loopback MUXs Determine analog diagnostic resolution & fault coverage Designer can trade-off analog area overhead & performance penalties TPG DAC Analog Cktry ORA ADC Analog Cktry 5/26/05 Auburn University SUTI Presentation 10

11 Application to RF Tranceiver Functionality of various components measured and compensated Reduce power consumption (extend battery life) Improve quality of communications 5/26/05 Auburn University SUTI Presentation 11

12 Important Analog Functional Tests Linearity 3 rd -order intermodulation (IP3) Quality of system Frequency Response Gain Phase Signal-to to-noise Ratio (SNR) Noise Figure S-parameters Input impedance Output impedance 5/26/05 Auburn University SUTI Presentation 12

13 f 1 f 2 Intermodulation f 1 f 2 f 2 - f 1 f 1 +f 2 2f 1 - f 2 2f 2 - f 1 2f 1 2f 2 3f 1 3f freq IM3 Two signals with different frequencies are applied to a nonlinear system Output exhibits components that are not harmonics of input fundamental frequencies 3 rd -order intermodulation (IM3) is critical Very close to fundamental frequencies 5/26/05 Auburn University SUTI Presentation 13 freq

14 Input 2-tone: 2 Mathematical Foundation x(t)=a 1 cos ω 1 t + A 2 cos ω 2 t Output of non-linear device: y(t)=α 0 +α 1 x(t)+α 2 x 2 (t)+α 3 x 3 (t)+ Substituting x(t) ) into y(t): y(t) ) = ½α 2 (A 12 +A 22 ) + [α 1 A 1 +¾α 3 A 1 (A 12 +2A 22 )]cosω 1 t + [α 1 A 2 +¾α 3 A 2 (2A 12 +A 22 )]cosω 2 t + ½α 2 (A 12 cos2ω 1 t+a 22 cos2ω 2 t ) + α 2 A 1 A 2 [cos(ω 1 +ω 2 )t+cos( +cos(ω 1 -ω 2 )t] P + ¼α 3 [A 13 cos3ω 1 t+a 22 cos3ω 2 t] + ¾α 3 {A 12 A 2 [cos(2ω 1 +ω 2 )t+cos(2ω 1 -ω 2 )t] +A 1 A 22 [cos(2ω 2 +ω 1 )t+cos(2ω 2 -ω 1 )t]} 2ω 1 -ω 2 α 1 A ω 1 ω 2 2ω 2 -ω 1 ¾ α 3 A 2 freq 5/26/05 Auburn University SUTI Presentation 14

15 Output Power (OIP3) P 3rd-order Intercept Point (IP3) IP3 is theoretical input power point where 3 rd -order distortion and fundamental output lines intercept P[dB] IIP 3 [dbm]= +P in [dbm] IM3 IP3 P/2 2 20log(¾α 3 A 3 ) 20log(α 1 A) fundamental Input Power (IIP3) Practical measurement with spectrum analyzer 2ω 1 -ω 2 α 1 A ω 1 ω 2 2ω 2 -ω 1 ¾ α 3 A 2 freq 5/26/05 Auburn University SUTI Presentation 15 P

16 Direct Digital Synthesis (DDS) DDS generating deterministic communication carrier/reference signals in discrete time using digital hardware converted into analog signals using a DAC Advantages Capable of generating a variety of waveforms High precision sub Hz Digital circuitry Small Small size fraction of analog synthesizer size Low Low cost Easy Easy implementation 5/26/05 Auburn University SUTI Presentation 16

17 Typical DDS Architecture Frequency Word N F r clk Accum -ulator Digital Circuits W Sine Lookup Table R D-to-A Conv. Low Pass Filter f out clk F r 2 N out = f clk Sine Wave 1/f out 1/f out 1/f out 1/f out 1/f clk 1/f clk 1/f clk 5/26/05 Auburn University SUTI Presentation 17

18 2-Tone Test Pattern Generator Two DDS circuits generate two fundamental tones F r 1 & F r 2 control frequencies tones DDS outputs are superimposed using adder to generate 2-tone 2 waveform for IP3 measurement DAC & LPF convert to actual analog test waveform F r 1 Accum -ulator #1 F r 2 Accum -ulator #2 Sine Lookup Table 1 Sine Lookup Table 2 Σ D-to-A Conv. Low Pass Filter 2-tone Waveform 5/26/05 Auburn University SUTI Presentation 18

19 Actual 2-Tone 2 IP3 Measurement Outputs of DAC and DUT taken with scope from our experimental hardware implementation Typical P measurement requires expensive, external spectrum analyzer For BIST we need an efficient output response analyzer DAC output x(t): DUT output y(t): P 5/26/05 Auburn University SUTI Presentation 19

20 Output Response Analyzer Multiplier/accumulator-based ORA Multiply the output response by a frequency N-bit multiplier, N = number of ADC bits Accumulate the multiplication result N+M-bit accumulator for < 2 M clock cycle samples Average by # of accumulation clock cycles Gives DC value proportional to power of signal at freq Advantages Easy to implement Low area overhead Exact frequency control More efficient than FFT y(t) f x multiplier X Σ accumulator DC 5/26/05 Auburn University SUTI Presentation 20

21 DC 1 Accumulator y(t) ) x f 2 DC 1 ½A 2 2 α 1 Ripple in slope due to low frequency components Longer accumulation reduces effect MATLAB Simulation Results slope = DC slope = DC 1 ½A 22 α 1 5/26/05 Auburn University SUTI Presentation Clock cycles (x50) y(t) f 2 X DC Σ 1 α 1 A P ¾ α 3 A 2 freq f 2 2f 2 -f 1 Actual Hardware Results

22 DC 2 Accumulator y(t) ) x 2f2 2 -f 1 DC 2 3 / 8 A 2 1 A 2 2 α 3 Ripple is bigger for DC 2 MATLAB Simulation Results 20 y(t) Signal is smaller Test controller obtains DC 2 at integral multiple of 2f 2 -f 1 2f 2 -f 1 X DC Σ 2 α 1 A P ¾ α 3 A 2 freq f 2 2f 2 -f 1 Actual Hardware Results slope = DC 2 3 / 8 A 12 A 22 α /26/05 Auburn University SUTI Presentation 22-5 Clock cycles (x50)

23 BIST-based P Measruement DC 1 & DC 2 are proportional to power at f 2 & 2f2 2 -f 1 Only need DC 1 & DC 2 from accumulators to calculate P = 20 log (DC 1 ) 20 log (DC 2 ) MATLAB Simulation Results 60 Actual Hardware Results Clock cycles (x50) 5/26/05 Auburn University SUTI Presentation 23

24 BIST Architecture BIST-based IP3 measurement Reduce circuit by repeating test sequence for DC 2 BIST-based frequency response needs subset f 1 Test Pattern Generator f 2 x(t)=cos( )=cos(f 1 )+cos(f 2 ) Accum Accum LUT1 LUT2 Σ DAC DUT X ADC y(t) Output Response Analyzer Accum DC1 DC2 2f 2 -f 1 Accum LUT3 X Accum DC2 5/26/05 Auburn University SUTI Presentation 24

25 Delta_P(dB) Hardware Results BIST measures P 14 Spectrum analyzer P Clock Cycles (x100) P P distribution for 1000 BIST measurements mean=13.97 db, σ =0.082 Measured Delta_P(dB) 5/26/05 Auburn University SUTI Presentation 25 Percentage(%)

26 Measurements in Noisy Test Set-up db P BIST measurement in noisy test set-up db P measurement in less noisy test set-up /26/05 Auburn University SUTI Presentation 26

27 Frequency (x0.001) Results for 1000 BIST measurements Better accuracy than spectrum analyzer More Measurements Spectrum Analyzer 14.3 db 24.5 db delta P delta P 5/26/05 Auburn University SUTI Presentation 27 Frequency (x0.001) BIST Measurement mean σ σ

28 BIST IP3 Measurement Results Good agreement with actual values for P < 30dB For measured P > 30dB, the actual P is greater 30dB limit due to 8-bit 8 DAC/ADC with 6-bit 6 resolution Good threshold since P < 30dB is of most interest 50 BIST measured delta P actual delta P 5/26/05 Auburn University SUTI Presentation 28

29 Frequency Response Gain and phase as a function of frequency Important analog function measruement Sweep through frequencies adjusting DDS f input Measure gain at output using BIST circuit Phase delay produces incorrect gain measurement results in ORA Gain Phase 5/26/05 Auburn University SUTI Presentation 29

30 Phase Delay ORA Multiplication unity gain sine wave sine X sine cosine wave (270 phase delay) cosine X sine /26/05 Auburn University SUTI Presentation 30

31 Phase Delay ORA Accumulation sine X sine accumulation sine X sine cosine X sine accumulation cosine X sine /26/05 Auburn University SUTI Presentation 31

32 Phase Delay Measruement y(t) x cos f DC 3 ½A 2 α cos φ y(t) x sin f DC 4 ½A 2 α sin φ Hence, we measure phase delay φ = tan -1 (DC 4 /DC 3 ) y(t) cos f y(t) sin f MATLAB simulation results for output φ = 135 X X Σ DC 3 Σ DC 4 5/26/05 Auburn University SUTI Presentation 32

33 BIST-Based Based Measurement Sweep through frequencies Measure phase delay Measure gain with correction for phase delay Gain Gain = DC3/cos φ = DC4/sin φ Subset of BIST circuit for IP3 measurement Gain Can time-share ORA f Test Pattern Generator f f Accum Accum x(t)= )=cos( cos(f) Cos LUT Sin LUT cos(f) sin(f) DAC DUT 5/26/05 Auburn University SUTI Presentation 33 X X ADC y(t) Output Response Analyzer Accum Accum DC3 DC4 DC4

34 Phase Delay Measurement Results Millions DC3 and DC4 measured for φ 79 Accumulator Value DC4 DC Accumulation Cycles Thousands 5/26/05 Auburn University SUTI Presentation 34

35 Phase Measurement P hase D elay degrees actualm easurem ent BIS T m easurem ent -100 Frequency K H z 5/26/05 Auburn University SUTI Presentation 35

36 Gain Measurement A m plitude db BIS T m easurem ent actualm easurem ent Frequency K H z 5/26/05 Auburn University SUTI Presentation 36

37 Experimental Implementation of BIST TPG, ORA, test controller, & PC interface circuits Three 8-bit 8 DDSs, two 17-bit ORAs,, serial interface Implementation in Verilog Synthesized into Xilinx Spartan 2S50 FPGA Amplifier device under test implemented in FPAA 1600 DAC-ADC ADC PCB PC FPAA DUT FPGA TPG/ORA DAC & ADC Total in FPGA Double ORA Single ORA Slices LUTs FFs 5/26/05 Auburn University SUTI Presentation 37

38 Comparison to Other Approaches FFT-based approach report for 2-tone 2 test Basis for IP3 measurement But this approach did not measure IP3 Required largest Xilinx FPGA 5,062 flip-flops flops & 106,553 combinational logic gates Ours fits in smallest Xilinx FPGA with 160 flip-flops flops & 1200 combinational logic gates FFT looks at all frequencies simultaneously Requires sufficient resolution for accurate test and measurements therefore, very large Ours looks at one frequency at a time which can be easily controlled therefore, no resolution issues Other approaches are based off-chip Including this FFT-based approach since it is too big for on-chip implementation 5/26/05 Auburn University SUTI Presentation 38