Digital Design Laboratory Lecture 7. A/D and D/A

Transcription

1 ECE 280 / CSE 280 Digital Design Laboratory Lecture 7 A/D and D/A

2 Analog/Digital Conversion A/D conversion is the process of sampling a continuous signal Two significant implications 1. The information content of the sampled signal is less than the continuous signal The continuous signal contains an infinite number of independent samples, the sampling process reduces that to a finite number of independent samples 2. Uncertainty is added to the sampled data. Quantization error is part of the sampling process since the number of intervals is finite. This is analogous to truncating a number after a specific number of places

3 Analog-to-digital converters V max = 7.5V 7.0V 6.5V 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 1.5V 1.0V 0.5V 0V analog input (V) time t1 t2 t3 t Digital output analog output (V) t1 t2 t3 t4 time Digital input proportionality analog to digital digital to analog Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

4 Analog/Digital Conversion Example Number of bits = 3 Number of intervals = 2 3 Range = 0-10 volts Resolution= 1.25 volts Quantization error= +/-.625 volts Variance =(1.25) 2 /12=.130 volts 2

5 Proportional Signals Simple Equation Assume minimum voltage of 0 V. V max = maximum voltage of the analog signal a = analog value n = number of bits for digital encoding 2 n = number of digital codes M = number of steps, either 2 n or 2 n 1 d = digital encoding a / V max = d / M Vmax 1..1 = 2 n -1 0 V 0..0 = 0

6 DAC vs. ADC DAC: n digital inputs for digital encoding d analog input for V max analog output a ADC: Given a V max analog input and an analog input a,, how does the converter know what binary value to assign to d in order to satisfy the ratio? Try and build circuitry that converts directly from a to d Not easy Use a guessing mechanisum Use DAC to generate analog values for comparison with a ADC guesses an encoding d,, then checks its guess by inputting d into the DAC and comparing the generated analog output a with original analog input a How does the ADC guess the correct encoding?

7 Bit Weight Each bit is weighted with an analog value, such that a 1 in that bit position adds its analog value to the total analog value represented by the digital encoding. Example: -5 V to +5 V analog range, n=8 Digital Bit Bit Weight (V) 10/2 = 5 10/4 = /8 = /16 = /32 = /64 = /128 = /256 = 0.039

8 Bit Weight Example (continued): -5 V to +5 V analog range, n=8 Digital numbers for a few analog values Values shown increment by 6 bits (weight for bit position 5 is 1.25 V) Maximum digital number only approximates the maximum analog value in the range Try (-5) + sum of all bit weights Analog (V) = Digital (hex) A0 C0 E0 FF

9 DAC: Binary weighted input Use inverting sum configuration of feedback opamps V 1 R R V 2 - V out = -V 1 - V 2 + R

10 DAC: Binary weighted input From AllAboutCircuits.com 2003

11 DAC: Binary weighted input Digital Input Analog Voltage 0.00V -1.25V -2.50V -3.75V -5.00V -6.25V -7.50V -8.75V

12 DAC: Binary weighted input Feedback resistor can be adjusted to change output voltage range DAC is highly sensitive to changes in resistor values All digital inputs must deliver the same voltage level for a logical high I.e. if bit 0 is 5.02V for a logical high, then bit 1 should be 5.02V as well - not 4.99V

13 ADC: Direct conversion Flash ADC Parallel ADC From AllAboutCircuits.com 2003

14 ADC: Digital Encoding Guessing the encoding is similar to finding an item in a list. 1. Sequential search counting up: start with an encoding of 0, then 1, then 2, etc. until find a match. 2 n comparisons: Slow! 2. Binary search successive approximation: start with an encoding for half of maximum; then compare analog result with original analog input; if result is greater (less) than the original, set the new encoding to halfway between this one and the minimum (maximum); continue dividing encoding range in half until the compared voltages are equal n comparisons: Faster, but more complex converter Takes time to guess the encoding: start conversion input, conversion complete output

15 ADC: Sequential Search Digital Ramp ADC

16 ADC: Digital Ramp ADC From AllAboutCircuits.com 2003

17 ADC: Binary Search Successive Approximation

18 ADC: Successive Approximation From AllAboutCircuits.com 2003

19 ADC: Successive Approximation Given an analog input signal whose voltage should range from 0 to 15 volts, and an 8-bit digital encoding, calculate the correct encoding for 5 volts. Then trace the successive-approximation approach to find the correct encoding. 5/15 = d/(2 8-1) d= 85 Encoding: Successive-approximation method M should be 2 n 1/2(V max + V min ) = 7.5V V max = 7.5 volts /2( ) = 5.16V V max = 5.16 volts /2( ) = 3.75V V min = 3.75 volts /2( ) = 4.92V V min = 4.92 volts /2( ) = 5.63V V max = 5.63 volts /2( ) = 5.04V V max = 5.04 volts /2( ) = 4.69V V min = 4.69 volts /2( ) = 4.98V Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

20 Analog/Digital Conversion Sampling Frequency Shannon s s Theorem Must sample at 2*f max to preserve information Nyquist Bandwidth Undersampling can cause aliasing in the frequency spectrum CD sampling frequency of 44.1KHz to capture all human- audible sound below 22KHz Different concept than MP3 bit rates

21 Terms & Equations Offset:: minimum analog value Span (or Range): difference between maximum and minimum analog values n:: number of bits in digital code (sometimes referred to as n-bit resolution) Bit Weight: : analog value corresponding to a bit in the digital number Step Size (or Resolution): : smallest analog change resulting from changing one bit in the digital number, or the analog difference between two consecutive digital numbers; also the bit weight of the LSB StepSize = Span 2 n Quantization Error: Maximum error due to a/d translation QuantizationError = ±StepSize 2 AV = DN StepSize + Offset = DN Span + Offset 2 n DN = AV Offset StepSize = (AV Offset) 2 n Span

22 FPGA DAC Can not use analog techniques Use digital techniques to generate a sequence of pulses - pulse width modulation (PWM) Pass through a low-pass filter to generate the analog signal

23 FPGA DAC PWM From 2816A-FPLSI Application Note Atmel

24 FPGA DAC PWM d is the duty cyle V is the maximum value f (t) = a a n cos 2nπt + b n sin 2nπt T T = 1 T Td 2 Td 2 n=1 Vdt + 2 T n=1 Td 2 n=1 Td 2 = Vd + 4Vd sin nπd a n = 2 T b n = 2 T V cos 2nπt dt cos 2nπt + T T ( ) cos 2nπt T T 2 T 2 T 2 T 2 Td 2 Td 2 f (t)cos 2nπt dt T f (t)sin 2nπt dt T V sin 2nπt dt sin 2nπt T T

25 FPGA DAC FPGA Low-Pass Filter Sampling Frequency = f CLK 2 n 16-bit 44KHz CD sampling would require a 2.9GHz clock

26 Lab 6 DTMF Tone Generator 1209 Hz 1336 Hz 1477 Hz _ ABC DEF 697 Hz _ GHI JKL MNO 770 Hz _ PRS TUV WXY 852 Hz _ 941 Hz * 0 # _

27 Lab 6 DTMF Tone Generator Keyboard reader Use from previous lab Should generate Ascii_available interrupt State machine Wait for ascii_available signal and then store ascii data

28 Lab 6 Signal Generator Use clock divider to generate 7 square waves Square waves are not ideal since they have higher frequency harmonics Optionally create a sine wave using a lookup table Use stored ascii data from state machine to decide which row and column frequencies to use Use adder to sum waves from row and column

29 Lab 6 PWM Module Take in an input value with sufficient resolution (4- bits minimum) Output a single waveform adjusting pulse widths based on the input value Speaker Module Must be connected to PIM which is connected to the B1 header Use data pin 1 for the speaker data Speaker module contains a low pass filter for PWM filtering.