Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below

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1 The New Face of Design for Manufacturability Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, and Gary Green HPL Technologies Editor s Note: Optimized test structures are necessary to measure and analyze the causes for systematic yield loss. This article introduces a novel test structure for BEOL an infrastructure IP for process monitoring. It also describes a method for characterizing and measuring yield ramp issues and solutions for improving silicon debug and DFM. Yervant Zorian, Virage Logic The challenges presented by deep-submicron interconnect back-end-of-line (BEOL) integration continue to grow in number, complexity, and required resolution at 90 nm and 65 nm. These challenges are causing industrywide delays in technology deployment as well as low and often unstable yields. The historically observed improvements in time to successful yield ramp and final manufacturing yield as the industry deploys new technology nodes disappeared at 90 nm. Such improvements have been significant factors in fueling the semiconductor industry s growth. In this article, we describe an infrastructure developed to specifically address BEOL deep-submicron yield-learning needs. These include the need to reduce the overall time to results and to provide information that manufacturers can successfully use in process and yield debug, and in higher-level design models. This infrastructure establishes a needed foundation for deepsubmicron technology nodes where design and manufacturing share yield entitlement. By building on this foundation, manufacturers can accelerate yield issue detection and correction, and realize yield-aware design flows. Deep-submicron BEOL yield challenges The International Technology Roadmap for Semiconductors 1 provides an excellent summary of the confounding combination of increased process complexity, reduced yield-learning cycles, and reduced defect visibility that confronts the industry. Accordingly, a yield ramp infrastructure must be available that can provide the following characteristics: parts-per-billion sensitivity to key yield-limiting topologies (not just to purely random defects); identification of nonvisual defects, such as defects in high-aspect-ratio features and interfacial defects; direct identification of defect location and layer; ability to generate vastly more data than has been possible with traditional technology characterization vehicles, to provide sufficient coverage of everexpanding design rule sets, interactions with resolution enhancement technologies (RETs), and so on; /05/$ IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers

2 the ability to distill this information as quickly as possible to true root-cause disposition; and the ability to assess both time-zero yield as well as early fail rate (EFR) yield limiters. In addition, design-manufacturing interactions are increasingly seen to increase product cost and delay successful product tape-out as well as final yield. These interactions are manifest as systematic yield issues. Systematic yield loss occurs when a process is not statistically robust when working with the given set of design rules. In the case of BEOL integration, this shortcoming is usually because of difficulties with No. of design rules Technology node (µm) Figure 1. Design rule count by technology node. 2 printing different via topologies, such as stacked vias or via arrays; effectively handling all cases of via topology in conjunction with the applied RET; effectively handling all cases of local pattern density and their interactions with etch and chemicalmechanical planarization processes; handling process excursions such as critical-dimension variations and misalignments; and combinations of these factors. Yield loss (%) Technology node (nm) Random Systematic These BEOL variations will result in large changes of R and C (and L) in the interconnect parasitics, which can have significant impact on yield. However, for the scope of this article, we concern ourselves with the simpler issues of simply making robust connections in the interconnect. Just considering RET assessment alone requires acquiring and understanding a large amount of data. The ability to print isolated and dense features, and the interaction between design rules such as line end via enclosure and minimum metal area for stacked-via landing pads, requires thorough monitoring. Figure 1 shows an indication of the increasing complexity of systematic yield loss, the number of design rules per technology node. The explosion of design rules below 150 nm is in some part a reflection of the interconnect-limited feature densities that require increasing levels of interconnect, but it is more driven by the systematic yield problems introduced by new materials, new processes, increased amounts of RET, and so on. Some examples of added classes of interconnect-specific design rules include pattern density window checks, multiple metal halation width checks, via optical-proximity (array) rules, corner or notch rules, and more complex minimum-feature-area checks. Figure 2. Systematic yield as a percentage of overall yield (data from Petersen Advanced Lithography). Figure 2 shows the relative importance of these systematic yield issues in overall circuit yield; it underscores the growing need to efficiently and comprehensively understand systematic yield loss as it occurs in deep-submicron technologies. These systematic effects are quickly swamping the chip yield. Traditional BEOL yield programs Traditional yield ramp infrastructures have been illequipped to handle this explosion of systematic yield issues, much less the increasingly challenging randomdefect detection requirements discussed earlier. Traditional yield ramp programs include a dedicated reticle set, which includes passive open-defect test structures (serpents and via chains) and passive shortingdefect test structures (combs). They also include a process qualification circuit, such as a suitably large SRAM or a production circuit that the company has characterized in prior technology nodes. Some open or May June

3 The New Face of Design for Manufacturability Relative ohm/via shift Probability of failue No. of vias in series Relative ohm/via shift Probability of failure Figure 3. Calculated via chain measurements of a 1-ppm, 250-ohm resistive defect, assuming 10-ohm nominal via resistance. short passive test structures are large (greater than 1 mm 2 ) to observe low-level random defectivity. Others are small to accommodate a large design of experiments that assess systematic-yield process windows associated with key topological variations and manufacturing variances. However, the size of these smaller passive test structures is limited to the area of one bond pad pitch (300 to 1,000 µm 2 ). At 90 nm and below, our experience has been that the list of systematic yield concerns is so large that technology development organizations must make difficult decisions about which subset of concerns to fit on the yield-learning test vehicle, even as it consumes a full reticle field (600 to 800 mm 2 ) dedicated exclusively to technology characterization. The passive test structures benefit from simplicity of design, from the ability to run short or partial flow wafers (and the commensurate reduction in mask costs), and, for the large random-defectivity structures, a highly efficient area utilization. For these and other reasons, they will always be a component of a thorough BEOL yield improvement program. However, several disadvantages of these basic test structures are becoming more glaring in the yield ramp needs below 130 nm. First, only extremely resistive, or hard failures, are detectible. This applies to either electrical or scanning-electron-microscope-based voltage contrast stressing of these types of structures. For example, consider the effect of a high-resistance via defect at the 1-ppm level that creates a 250-ohm resistance in a nominally 10-ohm via. This is an increasingly important yield issue at advanced technology nodes, where new materials and integrations are creating new defect mechanisms. Many defects in deep-submicron BEOL integrations do not create hard opens or shorts, which makes for difficult root-cause determination during circuit debug. Even worse, these defects can be latent, in that they can become worse under temperature or electrical stress, resulting in failures during burn-in or even later. Technology development schedules have no hope of success if failures remain undetectable until after process qualification begins. As Figure 3 shows, via string test structures that are long enough to have a reasonable probability of failure have absolutely no sensitivity to the defect mode just outlined. From the chart, we would target via strings of fewer than 100 vias, and then take measurements on millions of these strings. This argues clearly for an array-based approach. Such a circuit would provide the added benefit that when it detects a defect, it can easily localize the defect for failure analysis. An addressable array circuit in which the tested bits are such via strings is then an ideal vehicle for such deepsubmicron yield learning. Improved yield ramp infrastructure We will now describe our strategy for improving yield ramp at 90 nm and below, including the development of a specialized characterization circuit and case study. This circuit increases the random defects but also includes the detection of systematic yield issues. We combine it with integrated data analysis to increase the speed of yield understanding. Addressable characterization circuits The industry has discussed actively addressed technology characterization circuits for over 10 years. 3-6 Such circuits can circumvent the probe pad pitch limitation and provide more characterization information in a given wafer area. However, particularly for BEOL yield characterization, they are more costly to implement (more masks, more process steps, and increased cycle time) than single- or double-level passive test structures. Only in recent years have the benefits of addressable yield characterization arrays made them economically compelling, 7 resulting in renewed interest in specialized BEOL characterization arrays They inherently isolate defects 234 IEEE Design & Test of Computers

4 to a few microns in space, and to a specific level. They can also have significantly quicker test times than passive test circuits. This allows the testing of millions of vias in small groups, erasing the passive test structure limitation highlighted in Figure 3. BLB WL Random-defect case study (a) Strategies for studying random defects changed at the 90-nm node. At this under test (DUT). technology, more and more defects were soft, meaning that the interconnect defects were resistive vias but not complete opens or, conversely, small filament leakages. Large conventional (passive) test structures cannot resolve these defects at a suitably low defectivity rate due to averaging effects. Additionally, high-aspect-ratio defects, such as voids in vias and metal trenches, cannot be seen using defect scan techniques on the conventional test structures. Such defects can only be found electrically. Above 90-nm yield ramp. For benchmarking, we consider a program that introduced the addressable-array approach below the 90-nm technology node. At the prior (90 nm) technology node, we used a conventional test chip containing passive test structures and an SRAM-based yield driver circuit to ramp the technology yield to an acceptable point, which could supply data for EFR studies. With conventional structures sized appropriately to scan at least 1 billion vias per wafer, the characterization vehicle s test time was 240 minutes/wafer. This process missed identifying defects because of averaging effects; it also missed defects not visible to in-line inspection equipment. Thus, the yield driver circuits that went into EFR studies (a standard process qualification step) had an unacceptable level of time-zero and latent failures. Process fixes were implemented, but not until after the valuable time and cost of first EFR. This type of situation is common in industry, not just in yield ramp but in sustaining yield for deep-submicron metallization processes. 12 This situation is indicative of the challenges below 130 nm. AV DD DUT V SS Figure 4. SRAM (a) and TDROM (b) bits, showing placement of the test structure device Sub-90-nm yield ramp. For the current technology node, we designed a TDROM Technology Development ROM circuit to target the yield characterization limitations of the conventional infrastructure and improve visibility into observed BEOL yield issues. The TDROM is functionally much like a ROM in that each bit contains an access transistor that is programmed by a connection to the power supply or not. This is a ROM in the architecture, but is a technology development solution in that a targeted yield analysis element such as a serpent, comb, or via chain makes each bit s connection between the supply and the access transistor. By placing these structures into TDROM bits, we free up the bond pad limitation, greatly reduce the problem of resistance averaging, and significantly reduce test time per billion vias. Similar results are achievable using an SRAM as the base memory design and adding resistive test elements to various nodes. This is attractive given that SRAM design and test is so well known, and SRAMs are products used for many years. 13 However, as Figure 4 illustrates, TDROM has compelling advantages over an SRAM-based architecture. For example, it has a much smaller set of possible failure modes, which is advantageous in eliminating extraneous yield loss signals and therefore accelerating the desired BEOL yield understanding. Also, the TDROM requires only a single test pass, whereas an SRAM requires multiple test passes to understand the frequent multibit yield loss mechanisms. TDROM permits users to test 3.2 billion vias per wafer in 40 minutes/wafer, measuring and localizing failures in groups of 16 vias. Because of the clarity of electrical-defect results by location and by layer, we BL DUT BL DUT (b) WL May June

5 The New Face of Design for Manufacturability Fail map Via failure without voltage contrast Top-down SEM photograph showing voltage contrast for one of two failures Figure 5. Electrical failures with and without voltage contrast signatures. realized a 10 increase in physical-failure-analysis hit rate, resulting in a 5 increase in overall productivity in rootcause determination. Another major benefit is the ability to see small-failure-rate resistive-via yield issues. Even though the TDROM circuit is a pass/fail continuity tester, attention to design permits us to attain a coarse but adjustable resistance resolution. This in turn allows us to see resistive defects that conventional passive test structures or voltage contrast analysis missed. Further results have been attained and will be published soon. 14 Figure 5 shows a bitmap on the left with its corresponding voltage contrast image on the right. Both of the highlighted bits were electrical failures in the TDROM, and physical failure analysis later identified them to be partially etched vias. However, one failure was not resistive enough for voltage contrast to detect; it was the type of defect, as we just described, that might not have been found, diagnosed, and resolved until much later. An additional benefit of the ROM-based architecture is that its optimum bit cell size is not tied to minimum design rules, so we can use relaxed rules and even more robust devices (such as thick-oxide transistors) in the array design. This allows BEOL yield learning, including EFR studies, to be independent of FEOL yield learning, which is another advantage as compared to an SRAMbased yield vehicle. Systematic yield. The preceding discussion showed that our approach establishes a means of improved random-defect detection. However, a more compelling advantage of our infrastructure is its ability to monitor and detect systematic yield issues. An investigation of sub-90-nm systematic yield issues includes at least 12 conducting layers, most with Via failure some form of RET such as with voltage 1D and 2D optical proximity correction (OPC) or contrast phase shift masking. Systematic yield issues that require measurements by layer include process windows for critical-dimension bias and layer overlay. They also include design-manufacturing issues such as design rule windowing, and proximity, density, and orientation effects, to name a few. Monitoring these key topological concerns across realistic process windows necessitates a basic set of systematic yield-monitoring experiments ranging from 5,000 to 10,000 or more individual tests. Only through a fully automated infrastructure for design-of-experiment (DOE), layout, and test/analysis database creation are we able to organize, create, and analyze such a large number of systematic yield tests. This provides a needed advantage below 130 nm, where technology definition changes more often and later in the overall technology cycle. For example, design rule changes are becoming more common in advanced technology nodes, according to a recent keynote address by Synopsys CEO Aart de Geus ( org/wps/portal/_pagr/103/_pa.103/248?&dformat= application/msword&docname=p029804). In the case of a recent sub-90-nm TDROM deployment, the first wafers showed an unacceptable interaction between design rules and OPC, which required a modification to the design rule set. Since we had parameterized the bit DOE to the design rules, the design rule modification in question did not require a restatement of the DOE space. Thus, we were able to recompile the circuit and the overlaid bit DOE to account for the design rule change, and verify and ship the circuit to tape-out, all within five days. By erasing bond-pad pitch limitations, the array- 236 IEEE Design & Test of Computers

6 based solution allows the compaction of systematic yield tests over 1,000 more than possible for passive test structures. As a result, a comprehensive set of systematic yield tests consumes an area of approximately 1 mm 2. This circuit area includes room to place each systematic bit layout redundantly, 10 to 15 times, and also room for 10 to 20% of bits to be known check bits. Both strategies minimize noise in the test results and better mimic pattern densities beyond the range of lithographic proximity. Because of the small area involved, we can repeat a full, systematic-yield monitoring set in the reticle field like a small product die, enabling visibility into acrosschip variations. This repetition also allows the collection of significantly more data at the edge of the wafer increasingly important in 300-mm wafer technology because the partial reticle field shots along the edge of the wafer will contain full characterization sets. An additional advantage of our characterization circuit is that it leverages our layout and documentation generation platform (in use for 10 years), so that users can generate a very large bit DOE from a simple user interface and then quickly overlay it onto the memory circuit s regular array structure. Our bit design IP ties DOE creation to design rules, permitting us to quickly create the complex bit DOEs required to adequately evaluate key systematic-yield-loss mechanisms. Additionally, the design parameters of this DOE can go directly into our analysis software database so that they are available to the data analysis engine. In our BEOL yield program, we implement two key analysis circuits that complement the trade-off between information density and measurement accuracy. The digital I/O circuit discussed here is ideal for maximizing the experiment density of testing for hard defects. In addition to the continuity tests discussed here, the digital I/O circuit can contain A/C outputs (ring oscillators) and/or DC inputs for capacitance testing (via the charge-based capacitance measurement technique). Complementary to this, we implement a true analog I/O circuit, one which might be sensitive enough to measure small-void formation in copper interconnect schemes, but which has a much larger bitcell because of the need for access transistors enabling full-kelvin current-voltage measurement. In this circuit, we also typically create and measure a variety of resistance and capacitance tests for true parametric performance monitoring of the BEOL process. Completing the parametric yield measurement set is a suite of radio-frequencybased testers, including transmission line tests. May June 2005 Figure 6. Electrical vernier results in analysis application. Tightly integrated data analysis A key feature of our BEOL yield ramp infrastructure is the ability to generate large amounts of data per wafer, using thousands of heterogeneous bits within any array. Without linked and targeted analysis templates, this amount and variety of information would be overwhelming and unusable. For instance, although the TDROM array simply reports a collection of 1s and 0s, proper systematic-yield understanding dictates that we associate each bit result with 10 to 20 design parameters. Because of this, a TDROM database could easily grow to several hundred megabytes per wafer. Thus, a key feature of our infrastructure is the ability to aggregate failure signatures according to the designed-in bit variations and then directly convert these failure signature counts into root-cause Pareto diagrams and other final analysis views. In addition, with proper design of the systematic-yield DOE, our infrastructure can transfer layout DOE directly to analysis groups to quickly visualize the data from thousands of systematic-yield experiments. One example of this is analogous to that of a set of process capability metrics (C pk ), which we can monitor electrically, through failure statistics. The DOE-aware analysis software can then generate Pareto diagrams and electrical process windows in minutes instead of days. It is also possible to add these results to standard, interactive yield analysis features, such as an overlay to defect inspection results, a correlation to in-line metrology data, a correlation to product circuit sort/bin data, bitmapping, and wafer mapping. Figure 6 shows a snapshot of our analysis platform, displaying a set of electrical overlay verniers spanning layer, design rule, and intentional overlay. 237

7 The New Face of Design for Manufacturability (a) Sense Overlay (b) Those design parameters pass directly from the layout engine to the analysis database. Figure 7 is a clearer schematic of the electrical vernier view. Gnd + Overlay Figure 7. Variations in metal (sense and ground) overlay of via, shown as dashed lines (a), collected and summarized as an electrical vernier to determine process window. Each point in the resulting graph (b) is the failure rate of a collection of N bits with a set overlay value. Extension to design for manufacturability The infrastructure that we have described here can greatly aid design for manufacturability (DFM) awareness. The ability to generate unparalleled statistics in failure rates is useful for truly quantifying design-manufacturing yield trade-offs, especially in random logic applications that have extremely varied topologies, and complex and often unforeseen interactions with RET. Of course, it would be impossible to test a variety of key topologies to the part-per-billion level. However, we can use the process window results described earlier to assess relative process capability in the many systematic yield issues. By measuring these process windows, even qualitatively, we can provide yield trade-off information to use in creating systematic-yield models for next-generation yield-aware CAD tools. An example trade-off would be the relative yield improvement of relaxing metal overlaps on an isolated via, or adding a redundant via. Because systematic-yield experiments occupy such a small area in the array-based approach, we are also able to recast these same yield experiments into scribe line form factors to continue DFM visibility well into manufacturing. Instead of fitting a dozen or so conventional wafer acceptance tests into a manufacturing scribe area, we can fit hundreds of parametric or tens of thousands of continuity tests into the same area. This expanded set of process capability tests offered by the array-based scribe line approach has a very short test time, so it is a great improvement over the status quo. An example scribe line TDROM design for 90-nm characterization contained 51,000 continuity tests in an 80-µm 6.7-mm area. Ultimately, we expect that systematicyield-monitoring IP such as this will be justifiable as part of the chip overhead, just as an increasingly complex set of BIST technologies have proven valuable to overall yield. WE HAVE DESCRIBED a comprehensive approach to random and systematic BEOL yield learning and shown examples of successful applications below 90 nm. New horizons in the data obtained from valuable technology characterization wafers, if coupled with analysis templates that directly reduce the data to actionable results, can help improve the understanding of both random and systematic yield loss. We have discussed extensions that can greatly improve the ability to transfer a developed process into mature yield and also ultimately generate key wafer characterization views for use as a basis for DFM-enabling yield models. References Int l Technology Roadmap for Semiconductors, Semiconductor Industry Assoc., 2004; 2. M. Cote and P. Hurat, Layout Printability Optimization using a Silicon Simulation Methodology, Proc. 5th Int l Symp. Quality Electronic Design (ISQED 04), IEEE Press, 2004, pp A.J. Walton et al., A Novel Approach for Reducing the Area Occupied by Contact Pads on Process Control Chips, Proc Int l Conf. Microelectronic Test Structures (ICMTS 90), IEEE Press, 1990, pp T. Hamamoto et al., Measurement of Contact Resistance Distribution using a 4K-Contacts Array, IEEE Trans. Semiconductor Manufacturing, vol. 9, no. 1, Feb. 1996, pp R.E. Newhart and E.J. Sprogis, Defect Diagnostic Matrix : A Defect Learning Vehicle For Submicron Tech- 238 IEEE Design & Test of Computers

8 nologies, Proc Int l Conf. Microelectronic Test Structures (ICMTS 88), IEEE Press, pp D. Ward et al., The Use of a Digital Multiplexer to Reduce Process Control Chip Pad Count, Proc. IEEE Int l Conf. Microelectronic Test Structures (ICMTS 92), IEEE Press, 1992, pp C. Weber, Yield Learning and the Sources of Profitability in Semiconductor Manufacturing and Process Development, IEEE Trans. Semiconductor Manufacturing, vol. 17, no. 4, Nov. 2004, pp K.Y.-Y. Doong et al., The Short-Loop Process Tuning and Yield Evaluation by Using the Addressable Failure Site Test Structures (AFS-TS), Proc. 9th Int l Symp. Semiconductor Manufacturing (ISSM 2000), IEEE Press, 2000, pp F. Duan et al., Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability, Proc. 4th Int l Symp. Quality Electronic Design (ISQED 03), IEEE Press, 2003, pp M. Yamamoto, H. Endo, and H. Masuda, Development of a Large-Scale TEG for Evaluation and Analysis of Yield and Variation, IEEE Trans. Semiconductor Manufacturing, vol. 17, no. 2, May 2004, pp K. Miyamoto et al., Yield Management Methodology for SoC Vertical Yield Ramp, Tech. Digest Int l Electron Devices Meeting (IEDM 00), IEEE Press, 2000, pp R. Wilson, Failures Plague 130-Nanometer IC Processes, EE Times, 26 Aug M. Craig et al., A Technology Development SRAM Approach with DFM Considerations, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conf. and Workshop, IEEE Press, 2000, pp J.R.D. DeBord et al., Infrastructure for Successful BEOL Characterization and Yield Ramp at the 65nm Node and Below, to be published in Proc. IEEE 2005 Int l Interconnect Technology Conf., IEEE Press, Greg Yeric is chief technologist at HPL Technologies and responsible for technical guidance of the company s yield management, technology development IP, and DFM solutions. His experience includes the execution of technology development and yield enhancement programs across each technology node from 0.35 µm through 45 µm, over a spectrum of process technologies (CMOS, silicon on insulator, and mixed signal). Yeric has a PhD in microelectronics from the University of Texas at Austin. He is a senior member of the IEEE. Ethan Cohen is now a senior product development engineer at Advanced Micro Devices. He was with HPL Technologies when he did this work. His research interests include design for manufacturing and circuit design. Cohen has an MS in computer engineering from the University of Texas at Austin. John Garcia is a circuit design manager with HPL Technologies. His technical interests include radio frequency and mixed-signal design and modeling. Kurt Davis is the business development manager for Testchip Products at HPL Technologies and responsible for sales and go-to-market strategies for the company s technology development solutions. Davis has a BS in biomedical engineering from Texas A&M University. Esam Salem is a design engineer at HPL Technologies. His technical interests include the design and characterization of test chip circuits and parametrics for new and developed silicon technologies. Salem has a BS in electrical engineering from Louisiana Tech University. Gary Green is director of marketing for Yield Management Systems at HPL Technologies. His experience includes a variety of roles in business development and marketing. He co-holds a patent on the first commercially available wafer inspection tool in the semiconductor industry. Green has a BEE from Manhattan College and an MSEE from Northeastern University. Direct questions and comments about this article to Greg Yeric, HPL Technologies Inc., 2033 Gateway Place, Suite 400, San Jose, CA 95110; gyeric@ hpl.com. For further information on this or any other computing topic, visit our Digital Library at org/publications/dlib. May June