Oki 2BM6143 Microcontroller Unit Extracted from Casio GW2500 Watch 0.25 µm CMOS Process
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- Elmer Bennett
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1 Oki 2BM6143 Microcontroller Unit Extracted from Casio GW2500 Watch 0.25 µm CMOS Process Custom Process Review with TEM Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:
2 Custom Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Downstream Product and Package 2.2 Die 2.3 Die Features 3 Planar Analysis 3.1 Overview 3.2 Embedded SRAM Planar Analysis 3.3 Embedded Metal Mask ROM Planar Analysis 4 Cross Section Analysis 4.1 General Device Structure 4.2 Dielectrics 4.3 Metallization 4.4 Vias and Contacts 4.5 Logic and Analog Transistors and Poly 4.6 SRAM Transistors 4.7 Mask ROM Transistors 4.8 Poly Capacitors 4.9 Isolation 4.10 Wells and Substrate 5 Critical Dimensions 5.1 Package and Die 5.2 Vertical Dimensions 5.3 Horizontal Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
3 Overview Overview 1.1 List of Figures 2 Package and Die Casio GW2500 Watch Top Casio GW2500 Watch Bottom Inside of Casio GW2500 Watch Main Circuit Board of Casio GW2500 Watch Front Side Main Circuit Board of Casio GW2500 Watch Back Side Main Circuit Board of Casio GW2500 Watch Front Side (Customer Supplied) Main Circuit Board of Casio GW2500 Watch Back Side (Customer Supplied) X-Ray of Main Circuit Board Second Variant of Main Circuit Board from Casio GW2500 Watch Front Side (Customer Supplied) Second Variant of Main Circuit Board from Casio GW2500 Watch Back Side (Customer Supplied) X-Ray of Main Circuit Board Second Variant Die Photograph With Cu RDL and Flip-Chip Pads Intact Minimum Pitch Cu Flip-Chip Pads Die Photograph With Cu RDL and Flip-Chip Pads Removed Die Markings Flip-Chip Bonded MCU Die Photograph Second Variant with Wire Bonding Die Markings Wire Bonded MCU Annotated Die Photograph Delayered to Metal Analysis Sites Die Corner A Flip-Chip Die Die Corner B Flip-Chip Die Die Corner C Flip-Chip Die Die Corner D Flip-Chip Die Minimum Pitch Flip-Chip Bond Pads Flip-Chip Bond Pad Detail Die Corner A Wire Bond Die Die Corner B Wire Bond Die Die Corner C Wire Bond Die Die Corner D Wire Bond Die Minimum Pitch Wire Bond Pads Test Pad Detail General View of Logic Circuitry NAND Cell Resistor Poly Capacitor
4 Overview Planar Analysis Die Photograph Showing SRAM and Mask ROM Locations T SRAM Cell SRAM at Metal SRAM at Metal SRAM at Metal 2 Array Edge SRAM at Metal SRAM at Poly SRAM at Diffusion Mask ROM at Metal Mask ROM at Metal Mask ROM at Metal Mask ROM at Poly Mask ROM at Diffusion 4 Cross Section Analysis General Device Structure Die Thickness Die Edge Top Overview Die Edge Top Detail Passivation IMD IMD PMD Minimum Pitch Metal 3 SEM Metal 3 TEM Metal 3 Barrier TEM Minimum Pitch Metal Metal 2 Barrier TEM Minimum Pitch Metal 1 SEM Metal 1 TEM Metal 1 Barrier TEM Minimum Pitch Via 2s and Via 1s Minimum Pitch Contacts to Poly Minimum Pitch Contacts to Diffusion Bottom of Contact to Diffusion TEM Minimum Gate Length PMOS Transistor Minimum Gate Length NMOS Transistor Logic Transistor TEM Right Edge of Logic Transistor Poly TEM Logic Transistor Gate Oxide TEM Right Edge of Wide Gate Analog Transistor Poly TEM Transistor Thick Gate Oxide TEM
5 Overview SRAM Overview Parallel to Bitline SRAM NMOS Transistor and Minimum Contacted Gate Pitch SRAM Pull-Up (Pull-Down)Transistor TEM SRAM Transistor Gate Oxide TEM SRAM Transistor Overview Parallel to Wordline SRAM Access Transistor Gate Parallel to Wordline Mask ROM Overview at First Location Perpendicular to Poly Mask ROM Overview at a Second Location Perpendicular to Poly Mask ROM NMOS Transistor Mask ROM Overview Parallel to Poly Mask ROM Transistor Width Poly Capacitor Poly Capacitor Contact Minimum Width STI Poly Over STI Poly Over STI TEM STI Edge TEM SEM of N-Well SCM of N-Well SCM of P-Well P-Well and Substrate SRP
6 Overview List of Tables 1 Overview Device Identification Device Summary Summary of Major Findings 2 Package and Die Package and Die Dimensions 3 Planar Analysis Embedded SRAM and Mask ROM Memory Overview Embedded SRAM Transistor Sizes Embedded ROM Transistor Size 4 Cross Section Analysis Dielectric Composition and Thicknesses Metallization Measured Vertical Dimensions Metallization Measured Horizontal Dimensions Via and Contact Dimensions Transistor and Polysilicon Horizontal Dimensions Transistor and Polysilicon Vertical Dimensions Isolation Critical Dimensions Well and Die Vertical Dimensions 5 Critical Dimensions Package and Die Dimensions Dielectric Composition and Thicknesses Metallization Composition and Thicknesses Transistor and Polysilicon Vertical Dimensions Isolation Composition and Thicknesses Well and Die Vertical Dimensions Minimum Metal Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor and Polysilicon Horizontal Dimensions Isolation Horizontal Dimensions Embedded SRAM and Mask ROM Memory Horizontal Dimensions SRAM Transistor Sizes Embedded ROM Transistor Size
7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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