Samsung K4H510838C-UCCC 512Mbit DDR SDRAM Structural Analysis
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- Ariel Fisher
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1 July 26, 2005 Samsung K4H510838C-UCCC 512Mbit DDR SDRAM Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:
2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Company Profile 1.5 Device Summary 1.6 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 Recessed Channel Array Transistors (RCATs) 3.8 Isolation 3.9 Wells and Substrate 3.10 Redundancy Fuses 4 Memory Cell Analysis 4.1 DRAM Cross-Sectional Analysis (Parallel to Bit Line) 4.2 DRAM Cross-Sectional Analysis (Parallel to Word Line) 4.3 DRAM Plan-View Analysis
3 Structural Analysis 5 Materials Analysis 5.1 SIMS Analysis of Dielectrics 5.2 TEM EDS Analysis of IMDs and PMD 5.3 TEM EDS Analysis of Metallization 5.4 TEM EDS Analysis of Capacitors 5.5 TEM EDS Analysis of Transistors and Contact Implant 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions 7 References Report Evaluation
4 Overview Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom Plan-View Package X-Ray Die Photograph Annotated Die Photograph Die Marking Die Corner Die Corner Bond Pads 3 Process Analysis General Device Structure Die Edge Die Edge Seal Ball Bond Overview Bond Pad Edge Dielectric Layers Device Passivation Sub Layers (TEM) Overall View of IMD Detailed View of IMD 2 Sub Layers (TEM) Overall View of IMD Detailed View of IMD 1 Lower Levels and PMD Detailed View of IMD 1-2 Layer (TEM) Detailed View of PMD (TEM) Minimum Pitch Metal Metal 3 Composition (TEM) Minimum Pitch Metal Metal 2 Composition (TEM) Detail of Metal 2 Cap (TEM) Minimum Pitch Metal 1 Bit Lines Metal 1 Composition (TEM) Minimum Pitch Via 2s Via 1 Contacts to Poly 6 and Metal 1
5 Overview Via 1 Contacts to Poly 3 and Poly Minimum Pitch Via 1s and Contacts Detail of Top of Via Detail of Top of Via 1 (TEM) Detail of Tops of Minimum Pitch Via 1s (TEM) Detail of Bottom Via Detail of Bottom of Via 1 (TEM) Metal 1 Contact to Poly Minimum Pitch Poly 2 Contacts (TEM) Minimum Pitch Contacts to Polycide Detail of Tungsten Contact to Si (TEM) NMOS Peripheral Transistors PMOS Peripheral Transistor Peripheral Transistor Thin Gate Oxide (TEM) TEM Lattice Image of Thin Gate Oxide (Peripheral Transistor) Peripheral Transistor Thin Gate Oxide/STI Interface (TEM) Peripheral Transistor Thick Gate Oxide (TEM) TEM Lattice Image of Thick Gate Oxide (Periphal Transistor) Poly 3 Interconnect Plan-View Poly 3 Interconnect Recessed Channel Array Transistors (RCATs) Detail of RCATs (TEM) Detail of Recessed Channel (TEM) TEM Lattice Image of Gate Oxide Bottom of Recessed Channel Minimum Width STI STI Sidewall (TEM) SCM of Embedded P-Well Detail of Embedded P-Well Boundary SRP Plot of N-Well (Periphery) SRP Plot of P-Well (Periphery) SRP Plot of Well Structure Beneath DRAM Array Redundancy Fuses Fuse Window Redundancy Fuses Parallel to Fuse Link Detail of Redundancy Fuses Parallel to Fuse Link Redundancy Fuses Perpendicular Fuse Link Redundancy Fuses Perpendicular Fuse Link
6 Overview Memory Cell Analysis DRAM Parallel to Bit Line Overview Top of Storage Capacitors (TEM) Bottom Storage Capacitors (TEM) Capacitor Contacts (TEM) DRAM Parallel to Bit Line Bit Line Contacts (Edge of Memory Block) DRAM Parallel to Word Line Capacitor Contacts Capacitor Dielectric Dielectric Over Field Capacitor Contacts/Metal 1 Bit Lines (TEM) Capacitor Contacts Edge of Memory Block (TEM) DRAM Parallel to Word Line (Edge of Memory Block) Metal 1 Bit Lines and Poly 1 Word Line (TEM) Bit Line Contacts (TEM) Plan-View Analysis Reference Poly 6 Capacitor Top Plate Storage Capacitor Overview MIS Storage Capacitor Cylinders (TEM) MIS Storage Capacitor Cylinders (TEM) MIS Storage Capacitor Cylinder Composition (TEM) Poly 3 Capacitor Landing Pads Metal 1 Bit Lines Poly 2 Array Contacts Poly 1 Word Lines Diffusions and STI
7 Overview Materials Analysis SIMS Profile of Dielectrics TEM EDS Spectrum of Passivation TEM EDS Spectrum of IMD TEM EDS Spectrum of IMD TEM EDS Spectrum of IMD TEM EDS Spectrum of Metal 1 Hard Mask TEM EDS Spectrum of PMD TEM EDS Spectrum of Gate Capping Layer TEM EDS Spectrum of Metal 2 Cap TEM EDS Spectrum of Metal 2 Cap TEM EDS Spectrum of Metal 2 Ti:Al Alloy (Above Barrier) TEM EDS Spectrum of Metal 2 Barrier TEM EDS Spectrum of Metal 1 Body/Adhesion Layer TEM EDS Spectrum of Poly 6 Top Plate TEM EDS Spectrum of Poly 5 Inside Capacitor Cylinder TEM EDS Spectrum of TiN in Capacitor TEM EDS Spectrum of Al 2 O 3 Dielectric TEM EDS Spectrum of HfO 2 Dielectric TEM EDS Spectrum of Gate Silicide TEM EDS Spectrum of Contact Silicide 1.2 List of Tables Bond Pad Dimensions Dielectric Composition and Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Peripheral Transistor and Polycide Dimensions RCAT Dimensions Capacitor Dielectric Thicknesses (On Field)
8 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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